Harris HSP50210EVAL, User Manual

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The digital downconverted complex parallel bus output of the
HSP50110 Digital Quadrature Tuner is routed to the
HSP50210 Digital Costas Loop, U7. This parallel bus is also
routed through test header JP3. The baseband data ready
signal (BBDRDY#), HSP50210 input AGC signal
(DCLHI/LO), and the 68HC11 imbedded A/D input
(AGCLVL) are also provided on JP3. The BBDRDY# pro-
vides synchronization for the parts following the HSP50110.
The DCL HI/LO is provided to allow external filtering for use
of this signal in designing an AGC circuit around the A/D
converter when the HSP50110 is bypassed. The AGCLVL
signal is the return path for an external analog AGC signal.
The AGCLVL signal is digitized and read by the processor.
Test header JP2 contains the remaining output signals from
the HSP50110, control inputs for the HSP50110, and card
clock source/polarity jumpered selections.
The serial outputs of the Digital Quadrature Tuner, IBB0 and
QBB0, are routed to two HSP43124 Serial I/O filters, U4 and
U5, and then to the U7, Digital Costas Loop, serial input.
This filtered serial signal path is provided for those applica-
tions requiring special filtering beyond the Root Raised
Cosine (RRC) and Integrate & Dump (I&D) filters offered by
the HSP50210 Digital Costas Loop integrated circuit. An
octal register, U6, is provided to ensure that setup and hold
times are guaranteed up to the 45MHz maximum clock rate
of the FIR filters. Selection of signal routing to the FIR filters
is done in the DATA PATH/MODULATION MENU, item (14).
A set of .ARY files (two each for I and Q FIR filter) is gener-
ated by the program. Selecting the DATA PATH/MODULA-
TION MENU item (14) and identifying a .RPT file, sets the
FIR filter response. The HARDWARE INTERFACE MENU
item (3) allows the download of only the FIR filter files and is
useful when only the FIR filters need to be changed.
The I and Q output busses from the HSP50210, and the high
speed output clock are routed through the test header JP5 to
the 96 pin connector, P2. When a jumper is placed between
JP-5 pins 29 and 31, the data rate clock (DATACLK) is pro-
vided on both JP5 and P2. The I/Q output enable and loop
freeze control inputs, along with the loop tracking outputs of
the HSP50210, are routed to header JP4. Pin assignments
for all connectors and headers are provided in Appendices C
and D.
Clocking
Jumpered Options
The clock associated with the digitized IF samples can be
input at P1 pin 20 if the card is configured for external clock
(JP2 header pins 29-30). If the card is configured for internal
40MHz reference clock (JP2 header pins 29-31 and 30-32),
then the 40MHz reference clock is output on P1 pin 20.
Three ACT86 gates (U3) isolate the on-board and off-board
clock signals, allow different polarities for the clocks, and
provide the 3.0V minimum V
IH
required by the HSP parts.
Installing a jumper between J2-25 and 26 inverts clock for
the Digital Quadrature Tuner, the Digital PLL and the FIR Fil-
ters. Installing a jumper between J2-27 and 28 inverts the
high speed output clock.
Microcontroller
An on-board microcontroller, a 68HC11, provides the control
and status of the evaluation board. It includes RAM, EPROM
(programmed with Motorola’s BUFFALO™ monitor program),
EEPROM, a serial port, address decoding, a synchronous
serial port, an A/D converter, and other features. U8 provides
the RS232 drive levels for the serial port, JP7. U13 is an 8K x 8
static RAM for 68HC11 program and data storage. U14 pro-
vides the address decoding for the HSP parts. U15 provides
additional address decoding that is brought to JP9. U9 and U10
are the power-on reset and optional switch controlled reset volt-
age detectors. U11 is the 8MHz oscillator for the 68HC11. JP8
provides an RS232 port for the I channel received symbol data
stream when JP4 pins 31 and 32 are jumpered. JP6 provides
for jumpering the operating mode of the 68HC11, installing a
RESET switch, and applying 12.25V for the programming the
68HC11 EPROM.
The jumper options for JP6 are:
Pins 1-2 Description
No Jumper IRQB = 1 (Note 1)
Jumpered HSP50110 LKDET INT = IRQB
Pins 3-4 Pins 5-6 Description
Jumpered Jumpered Special HC11 Bootstrap Mode
No Jumper Jumpered Special HC11 Test Mode
Jumpered No Jumper Special HC11 Single Chip Mode
No Jumper No Jumper Expanded HC11 Mode (Note 1)
Pins 7-8 Description
No Jumper XIRQ = Program Voltage (pin 8) (Note 1)
Jumpered XIRQ = 0 (GND)
Pins 9-10 Description
No Jumper OPERATE (Note 1)
Jumpered Microprocessor RESET (temporary connec-
tion only, is required for RESET)
NOTE:
1. Indicates normal operational mode for the evaluation board
JP9 is provided for monitoring the microcontroller and pro-
vides access to the address bus, the data bus, the SPI port,
control signals, and general purpose I/O signals.
Power Supply Connections
The +5V input jack is J1. The +5V can be supplied from any
g5VDC/500mA AC/DC power adapter. A cable that
has the mating connector to J1 is provided with the evaluation
kit for use with a standard laboratory power supply. A zener
diode provides some protection against overvoltage or polar-
ity reversal. The J1 input is fused for protection from excessive
current draw. V
CC
and GND connections can also be made at
the JP10 header, or at either the P1 or P2 connectors. The
supply pins on these 96 pin connectors match VME P2 pins
for +5V and ground and also are compatible with the supply
pins on other Harris evaluation boards. The evaluation board
draws approximately 400mA at 40MHz.
HSP50110/210EVAL
BUFFALO™ is a trademark of Motorola.