Harris HSP50210EVAL, User Manual

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Item 3: Bit Sync Loop Order
(0; 1; 2)
0 = disabled, 1 = 1st, 2 = 2nd
When symbol tracking is disabled, the feedback path from
the HSP50210 in the HSP50110 is disabled. In first order
mode, the phase error input to the bit sync lag accumulator
in the loop filter is zeroed. In second order mode, the loop fil-
ter is a lead/lag type.
Item 4: Bit Sync Acquisition Fractional Loop Bandwidth
(0.0 to 0.125)
This is the single-sided loop noise bandwidth used for acqui-
sition. Enter the bandwidth desired at the design SNR (it will
narrow as SNR decreases. Fractional loop bandwidth is the
ratio of the loop bandwidth to the baud rate (or the rate that
the loop filter is updated). For example a loop bandwidth of
1kHz at 100kbaud would have a FLBW of 0.01.
Item 5: Bit Sync Tracking Fractional Loop Bandwidth
(0.0 to 0.125)
This is the single-sided loop noise bandwidth used for tracking.
Enter the bandwidth desired at the design SNR. Fractional loop
bandwidth is the ratio of the loop bandwidth to the baud rate (or
the rate that the loop filter is updated). For example a loop
bandwidth of 1kHz at 100kbaud would have a FLBW of 0.01.
Item 6: Bit Sync Loop Damping Factor
(0.0 to 1.5)
This damping factor is used for acquisition and tracking.
Enter the damping desired at the design SNR.
Item 7: Symbol Tracking Bits
(0; 1; 2; 3)
0 = 8, 1 = 16, 2 = 24, and 3 = 32.
This is the number of bits of the offset frequency sent from
the HSP50210 to the HSP50110. At higher data rates, fewer
bits can be used since the ratio between the clock rate and
the loop bandwidth can be lower. This allows for faster
updates and less delay around the loop.
Item 8: Bit Sync Serial Output at
(0; 1)
0 = Fclk (master clock);
1 = Serial clock (the SLOCLK output pin)
If the frequency offset serial output from the HSP50210 is
routed to a destination other than the HSP50110 (a D/A, an
NCO), the serial data can be output at a submultiple of the
master clock. The master clock/slower clock selection is
done here, and the speed of the slower clock slow clock is
selected in menu item 14 of the carrier loop menu. If the
tracking is done via the HSP50110, the master clock must
be used.
Lock Detector Menu
Item 1: Lock Detector Integration Time (Acquisition)
(1 to 1025)
This is the number of baud times that the magnitude of the
carrier phase error is integrated before making decisions
when searching for potential lock points during acquisition.
Item 2: Lock Detector Integration Time (Tracking)
(2 to 1025)
This is the number of baud times that the magnitude of the
carrier phase error is integrated to when verifying a potential
lock points and during tracking.
Item 3: Lock Detector Acquisition Threshold
(In Degrees)
(0 to 180)
This is the average magnitude of the carrier phase error over
the acquisition integration time. This is the decision thresh-
old for potential lock points.
Item 4: Lock Detector Tracking Threshold (In Degrees)
(0 to 180)
This is the average magnitude of the carrier phase error over
the verification and tracking integration. This is the threshold
used to switch back to acquisition mode.
Item 5: Lock Verify Cycles (TRK Integration times)
(0 to 15)
This is the number of lock detector integration periods that
loop must be in lock before the state machine transitions
from the verify to the lock state.
Item 6: False Lock/Frequency Error Integ
(0; 1)
0 = freq error; 1 = false lock
This item selects whether the false lock accumulator inte-
grates the magnitude of the frequency error or the (square
wave) false lock decisions when deciding whether a potential
lock point is actually a false lock point.
Item 7: False Lock Detector
(0; 1)
0 = off; 1 = on
This item enables/disables false lock detection.
Item 8: False Lock Threshold
(0 to Discriminator Range)
This sets the false lock threshold in % of symbols that indi-
cate (square wave) false lock or Hz of freq error.
Item 9: False Lock Sweep Count
(0 to 15)
This is the number of lock detector integration times that
sweep is forced to move beyond a false lock point.
HSP50110/210EVAL