Harris HSP50210EVAL, User Manual

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10
Appendix D
JP1 through JP10 Test Header Pin Assignments
JP1 TEST HEADER PIN ASSIGNMENTS
PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION
1 DQTHI/LO DQT HI/LO Signal 2 GND Ground
3 CLKIN Input Clock to Board 4 GND Ground
5 II9 I Input Bus Bit 9 (MSB) 6 II8 I Input Bus Bit 8
7 II7 I Input Bus BIT 7 8 II6 I Input Bus Bit 6
9 II5 I Input Bus BIT 5 10 II4 I Input Bus Bit 4
11 II3 I Input Bus BIT 3 12 II2 I Input Bus Bit 2
13 II1 I Input Bus BIT 1 14 II0 I Input Bus Bit 0 (LSB)
15 GND Ground 16 GND Ground
17 QI9 Q Input Bus Bit 9 (MSB) 18 QI8 Q Input Bus Bit 8
19 QI7 Q Input Bus Bit 7 20 QI6 Q Input Bus Bit 6
21 QI5 Q Input Bus Bit 5 22 QI4 Q Input Bus Bit 4
23 QI3 Q Input Bus Bit 3 24 QI2 Q Input Bus Bit 2
25 QI1 Q Input Bus Bit 1 26 QI0 Q Input Bus Bit 0(LSB)
27 GND Ground 28 GND Ground
29 DQTENI# DQT Input Enable 30 GND Ground
31 AGCLVL A/D Input to 68HC11 32 GND Ground
JP2 TEST HEADER PIN ASSIGNMENTS
PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION
1 GND Ground 2 DQTPH1 DQT Phase Shift Bit1
3 GND Ground 4 DQTPH0 DQT Phase Shift Bit 0
5 GND Ground 6 DQTCFLD DQT Center Freq Load
7 GND Ground 8 DQTOEI# DQT Output Enable I
9 GND Ground 10 DQTOEQ# DQT Output Enable Q
11 GND Ground 12 DQTLOTP DQT L.O. Test Point
13 GND Ground 14 SPH0 Bit Sync Phase Bit 0
15 GND Ground 16 SPH1 Bit Sync Phase Bit 1
17 GND Ground 18 SPH2 Bit Sync Phase Bit 2
19 GND Ground 20 SPH3 Bit Sync Phase Bit 3
21 GND Ground 22 SPH4 Bit Sync Phase Bit 4
23 GND Ground 24 SSTRB# Bit Sync Strobe
25 GND Ground 26 INVDCLK Invert Demod Clock
27 GND Ground 28 INVCKOUT Invert Output Clock
29 CLKIN Input Clock to Board 30 MSTRCLK Master Clock Node
31 DRVCLK Clock Driver 32 OSCCLK Oscillator Output
NOTE: To input the clock to the board, connect pin 29 to 30; to source the clock from the on-board oscillator, connect pin 29 to 31 and pin 30 to 32.
HSP50110/210EVAL