Harris HSP50210EVAL, User Manual

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Item 17: Design Es/No
(-100dB to 100dB)
Enter the design Es/No. This is used to set the carrier phase
detector operational gain. Enter 100 for noise free.
Item 18: Minimum A/D backoff
(0 to 60)
This is the minimum total power backoff at the A/D. The
nominal backoff is halfway between the minimum and max
backoff.
Item 19: Maximum A/D backoff
(0 to 60)
This is the maximum total power backoff at the A/D.
Item 20: DCL Output Vector Length
(-60 to 3)
This is the nominal HSP50210 output level set by the AGC.
This is in dB relative to full scale on either axis. Typically, this
is set to -6dB for BPSK, -3dB for QPSK, and -1.8dB for
8PSK.
Item 21: DQT Output Vector Level
(-60 to 3)
The output level for the HSP50110 is set to minimize limiting
while maximizing effective bits. With noise only, this is typically
set to -12dBFS. Since the HSP50210 can only add gain and
cannot attenuate a signal, this should be set low enough that
the output level at the HSP50210 can be achieved (for exam-
ple, the HSP50110 output should not be set to -6dBFS when
the desired output of the HSP50210 is -6dBFS).
Item 22: DCL Output Level Detector Threshold
(-60 to 3)
This is the threshold for the output level detector on the
HSP50210 (THRESH#). The output pin is asserted when the
signal magnitude out of the HSP50210 exceeds this pro-
grammed threshold.
Item 23: Output Slicer Threshold
(0 to 1)
The output slicer thresholds are set based on the needs of
the FEC. The programmed level is the first of the three com-
parator thresholds. The thresholds are relative to the full
scale magnitude on one rail. The output format set by the
program for the soft decisions is currently signed-magnitude.
The range is 0-1. The decisions thresholds are at 1x, 2x, 3x
the programmed threshold.
Item 24: DQT AGC Slew Rate
(0 to 1,000,000)
This is the slew rate for the AGC in the HSP50110. The AGC
is updated on every output sample. Since this AGC adjusts
for changes that are out of the band of interest (FDM signals
coming and going, etc.), it is typically set to slew faster than
the AGC in the HSP50210. The value entered is in dB/s
Item 25 DCL AGC Slew Rate
(0 to 1,000,000)
This is the slew rate for the AGC in the HSP50210. This
AGC adjusts for changes in signal level due to SNR changes
or signals coming and going inside the filter band of the
HSP50110. This AGC is typically set to slew slower than the
AGC in the HSP50110. The value entered is in dB/sec
Item 26: AGC Limits
(0; 1)
0 = Computed; 1 = FULL RANGE
This value is either calculated from the bandwidths and
Es/No’s, or is entered as FULL RANGE.
Item 27: Output Multiplexer Control
(0; 1; 2; 3; 4; 5; 6; 7, 8)
0 - Isoft(2:0), Qsoft(2:0), Status(6:0), AGC(7:1)
1 - Isoft2, Qsoft2, Mag(7:0), Status6, Status0, Phase(7:0)
2 - Isoft(2:0), Qsoft(2:0), Status(6:0), FreqErr(7:1)
3 - Isoft(2:0), Qsoft(2:0), Status(6:0), GainErr(7:1)
4 - Isoft(2:0), Qsoft(2:0), Status(6:0), BitPhErr(7:1)
5 - Isoft(2:0), Qsoft(2:0), Status(6:0), CarPhErr(7:1)
6 - Isoft(2:0),Qsoft(2:0), LkAcc(6:0), LkCnt(6:0)
7 - Isoft(2:0), Qsoft(2:0), Iend(7:1), Qend(7:1))
8 -Reserved(7:0), Status5, Status6, NCOS(9:0)
The output multiplexer selects the signals that are routed to
the output bus of the HSP50210. In most cases, the soft
decisions are available at the MSBs of the AOUT bus. This
allows other nodes to be monitored without disturbing the
output data. In most cases where an error detector is
brought out, it is the bottom 7 bits of the BOUT bus. Selec-
tion 7 can be used to plot the I/Q constellation using a logic
analyzer or a pair of D/A converters.
Carrier Tracking Loop Menu
Item 1: Carrier Tracking Loop Upper Limit
(-52,000,000Hz to 52,000,000Hz)
This is the upper limit for carrier loop filter lag accumulator.
This sets the upper limit on carrier acquisition and tracking.
During acquisition, the sweep direction reverses when this
limit is reached.
Item 2: Carrier Tracking Loop Lower Limit
(-52,000,000Hz to 52,000,000Hz)
This is the lower limit for carrier loop filter lag accumulator.
This sets the lower limit on carrier acquisition and tracking.
During acquisition, the sweep direction reverses when this
limit is reached.
Item 3: Carrier Tracking Loop Order
(0; 1; 2)
0 = disabled, 1 = 1st, 2 = 2nd
When carrier tracking is disabled, the feedback path from the
HSP50210 in the HSP50110 is disabled and the complex mul-
tiplier in the HSP50210 is bypassed. In first order mode, the
phase error input to the carrier lag accumulator is zeroed. In
second order mode, the loop filter is a lead/lag type. During
acquisition, the program sets the loop to first order.
HSP50110/210EVAL