Harris HSP50210EVAL User Manual Download

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Advanced Evaluation Configurations

Terminal/PC With Terminal Emulation Control of
Evaluation Board

The user has the option of communicating directly with the
evaluation board microcontroller monitor program using a
“dumb terminal” or a PC with a communications program
such as Terminal under Microsoft Windows

™

. The COM port

settings are 4800 baud, 8 bits, 1 stop bit, and no parity. The
download (.DLD) files generated by the Control/Status soft-
ware contain monitor commands for loading the HSP regis-
ters. A terminal emulator program can be used to send these
files to the monitor program as a text file download. Faster
transfers result when using “Line at a Time” versus other
download options because the text transfers wait only for the
prompt string “>”.

1. On reset, the monitor program sends a greeting.

2. Press enter and the monitor will return a prompt.

3. To display a help screen, send “?”.

4. To initialize the 68HC11 to communicate with the HSP

parts enter the following commands:
MM 005A
00 88 08 03 04 01
This sets up the memory map and address decoding.

The memory map for the 68HC11 is provided in Appendix G.
A list of the file types on the distribution disk with a brief
description, is provided in Appendix H.

For further information on the MC68HC11K4 microproces-
sor, reference the following Motorola data books:

Motorola M68HC11 Reference Manual (M68HC11RM/AD)

Motorola MC68HC11K4 Technical Data (MC68HC11K4/D)

The source code for the monitor program (BUFK4.ASM,
.S19, and .LST) is available on the Motorola’s bulletin board
for microprocessor products. It can be accessed using either
anonymous ftp to freeware.aus.sps.mot.com or via modem
at (512) 891-3733 (8 bits, 1 stop bit, no parity).

Serial Data Output at RS232 Levels

A user can read the I symbol serial data directly from the
output bus of the HSP50210 at RS232 levels using JP8-3.
JP4 must have pin 31 jumpered to pin 32 to connect the out-
put data to RS232 driver, U8.

Using SERINADE Designed Filters

Once SERINADE has been used to synthesize a filter, it is
possible to use this filter design in the FIR filters in the
demodulator on the evaluation board. This procedure
assumes that the SERINADE .RPT files are available for
import. Version 1.1 or higher is recommended.

Root Raised Cosine Filter

Several filter coefficient files have been included on the
HSP50110/210EVAL disk because the SERINADE program
does not compute square root of raised cosine filters. These
files are provided for import into SERINADE. Select FIR
type:

Imported on the SERINADE design menu screen.

SERINADE will add the control register values for the raised
cosine filter and any half band stages that you might select.
SERINADE will generate the .RPT files as before. The root
raised cosine coefficient files have been provided for alpha =
0.2, 0.35, 0.4, and 0.5 at 2X, 4X, and 8X baud rate. The
impulse response length is 8 baud intervals for all cases.

Non Demodulator Configurations

If other configurations are needed, the software can be used
to generate computed data gain, filtering, and I/O settings.
These settings can be downloaded as a file, as before, or
modified as individual register IC parameters after an initial
download.

Detailed Circuit Description

The reader should reference the detailed schematics,
found in Appendix E, while reading the detailed circuit
description.

Signal Path

The signal path begins with digitized IF data samples input
to the P1 connector. These data samples form a complex
data bus, 10 bits of each I and Q samples, which is routed to
the input of the HSP50110 Digital Quadrature Tuner, U1. Pull
down resistors, RZ1-3, are provided for unused inputs. If the
input sampled IF data format is offset binary and it is a real
signal (either I or Q data only), the MSB of the unused input
bus (I or Q) should be pulled up to a logic “1” to set the bus
to midscale. Because all of the P1 signals pass through test
header JP1, it can also serve as an input connector. In
addition to the P1 signals, JP1 has two HSP50110 signals,
the input enable signal DQTENI# and the output signal
DQTHI/LO. JP1 also has the AGCLVL input signal for the
68HC11 internal A/D converter. The external access to the
DQTENI# signal provided on P1 allows the HSP50110 to be
evaluated in both the gated input and interpolated input
modes. The DQTHI/LO, when externally filtered, can be
used in designing an Automatic Gain Control (AGC) circuit
around the IF A/D converter. Both the threshold and logic
sense of the DQTHI/LO signal are programmable. The
AGCLVL signal is the return path for an external analog AGC
signal. The AGCLVL signal is digitized and read by the
processor.