Harris HSP50210EVAL, User Manual

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S E M I C O N D U C T O R
1
USER’s MANUAL
April 1996
HSP50110/210EVAL
DSP Demodulator Evaluation Board
Features
• Evaluation Kit for the HSP50110 Digital Quadrature
Tuner and the HSP50210 Digital Costas Loop
• PSK Demodulator Board for Rapid Prototyping
• Interfaces with HI5703 A/D Evaluation Boards for
Analog Inputs
• Interfaces to PC Serial Port
• DOS Based Control/Status Software
• HSP43124 Serial FIR Filters for Custom Filtering
• SERINADE FIR Filter Design Software
• Power and RS232 Cables Supplied
Applications
• Prototyping Tool for PSK Communication Receivers
• PSK Demodulators from 1 KBPS to 2.5 MBPS
• Bit Synchronizers
• Digital Downconversion
• Narrowband Tracking Filters
Description
Evaluation Kit
The HSP50110/210EVAL kit consists of a circuit board, a
Control/Status software program, the SERINADE™ FIR filter
development software, and interface cables. The kit provides
the necessary tools to evaluate the HSP50110 Digital
Quadrature Tuner, the HSP43124 FIR Filter and the HSP50210
Digital Costas Loop integrated circuits. The evaluation kit is
designed as a drop in prototype PSK demodulator for digitized
(A/D converted) IF communications applications. The circuit
board accepts an input signal of up to 10 bits of I and Q
samples and recovers baseband I/Q data and symbol clock.
Analog IF signals can also be processed by inserting an
HI5703 A/D evaluation board between the analog source and
the HSP50110/210EVAL circuit board.
Circuit Board
Figure 1 illustrates the major functions of the evaluation circuit
board. The circuit board is a 3U x 160mm VME/Eurocard form
factor with dual 96 pin I/O connectors. The connector pinouts
conforms to the VME P2 connector pinout (i.e. power pin
positions located on the middle row and I/O pin positions
located on the outer rows). Data enters the board on the P1 96
pin plug connector and is routed through the HSP50110 Digital
Quadrature Tuner to the HSP50210 Digital Costas Loop. Data
leaves the board through the P2 plug connector. For
applications requiring custom filtering, the HSP43124 Serial I/O
FIR Filter can be inserted in the data path prior to the Digital
Costas Loop. An on-board microcontroller, a Motorola 68HC11,
provides a control and status interface to the serial port of a
Personal Computer (PC) running the Control/Status software
program. The microcontroller EPROM contains the Motorola
monitor program which provides the serial interface to the PC.
Test connectors are provided at key signal and control locations
in the demodulator circuit.
Functional Block Diagram
JP1 JP2 JP3
P1
96 PIN
CONNECTOR
JP9
JP7
JP6
HSP43124 (U5)
SERIAL I/O FIR FILTER
HSP43124 (U4)
SERIAL I/O FIR FILTER
P2
JP8
68HC11
MICROCONTROLLER
(U12)
CLOCK
GENERATOR/BUFFER
(U2 AND U3)
8K x 8 RAM
(U13)
JP4 JP5
IF OR BASEBAND
SAMPLED DATA
MICROCONTROLLER
DOWNCONVERTED
SAMPLED DATA
RS232
CONFIGURE/CONTROL
I AND Q BASEBAND
DATA SYMBOLS
SERIAL I DATA
FIGURE 1.
HSP50210
DIGITAL
COSTAS
(U7)
LOOP
HSP50110
DIGITAL
QUADRATURE
(U1)
TUNER
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1996
SERINADE™ is a trademark of Harris Corporation.
File Number
4149