Giga-tronics 8501A, Operation & Maintenance Manual

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Trig Pulse Stretcher
The Trig Pulse Stretcher makes sure that the delay board is triggered only by the first leading edge of
each trigger pulse. It stretches the pulse to 200 ns after the last trailing edge of the pulse. In this way, all
glitches shorter than 200 ns will be removed from the pulse. Its input comes from the Trig Select circuit,
and its output goes to the Ramp Control Logic.
The Pulse Stretcher function is initiated by the monostable multivibrator, U26, which is configured
through its E+ and E- inputs by flip-flop U29B to accept only a negative sloping trigger, and by the
2-input OR gate U24C. All action takes place in the ECL format.
To better understand the operation of the Pulse Stretcher, assume that the output of U29B has been
clocked but not reset. The input would then be low. When the input goes high, the first thing that happens
is that the output of the OR gate goes high. Then, the output of U29B will be reset causing the second
input of the OR gate to go high. When the input goes low it will trigger U26 into generating a 200 ns
output pulse. U26 can be triggered so that if the input signal contains more pulses that are less than
200 ns apart, the output will stay low until 200 ns after the last negative edge. When the output of U26
goes back to the high condition (the reset input of U29A is then low). U29A is clocked and the inverted
output goes low. Since this means that both inputs of U24C are low, the output of the Pulse Stretcher will
now go low.
After the PPM is first turned on, it is necessary to give the Pulse Stretcher one trigger input pulse
(generated by the soft trigger function) to initialize it.
Clock
The Clock is a stable crystal controlled square wave generator. It operates at 39.0625 MHz to give a
25.6 ns period.
The Clock consists of U23A,B & C, and Y1. U23A is a positive feedback amplifier with the Y1 crystal.
U23C provides a dc bias to the input and U23B is an output buffer. The frequency is adjusted with C79.
The clock frequency can be measured with a high impedance probe at TP5.
Clock Gate
The Clock Gate provides the timing to the Counter when either in the count mode or in the delay data
mode. When counting, the clock is enabled with a clock enable signal from the Ramp Control Logic and,
when loading, it is enabled by a load signal from the CPU Interface.
The Clock Gate consists of AND gates U28A and U28B whose outputs are OR’d in U27C. The clock is
connected to both U28A and U28B, and can be gated by either the load signal on U28A pin 4 or by the
Ramp Control Logic Out 2 on U28B pin 7.
Counter
The Counter establishes a coarse delay time. It is controlled by the Digital Delay Bus and the load signal
from the CPU Interface. The clock gives it a resolution from 25.6 ns to a maximum delay of about
430 ms. The output is the selected clock pulse with just one gate delay with respect to the clock.
The Counter consists of high speed ECL binary counter U14, five TTL binary counters U9, U12, U11,
U10, and U9 (with the first one being S-TTL), and the clock input. ECL delay data is translated from
TTL by U13. It is clocked from the Clock circuitry. During the delay count, the multiplexer U16 selects
the Terminal Count (TC connection) of U14 as the clock input to U8, and the Carry Out (CO connection)
of U8 as the clock input to U12, U11, U10, and U9. U11, U10, and U9 operate in a look-ahead, carry
mode. U19A, U20A, and U24A are using the U8 Terminal Count and the U8 and U9 Carry Out to select
the first clock pulse after the counter has counted up to a full count.
When all of the counters are loaded, they have to be provided with one clock pulse while the Load input
is low (Parallel Enable for U14) to execute the load. In U14, this is done by the Clock Gate circuit. For
Series 8500A Peak Power Meters
4-16
Manual No. 20790, Rev C, November 1998