4.2.4
Digital Delay PC Assembly (A5)
See Figure 4-5, Figure 4-6, and schematic diagram #16686 in Chapter 8.
The Digital Delay PC board circuitry establishes time delays that may be desired when examining sample
pulses. Delays can be set in increments of 0.1 ns up to about 430 ms.
As can be seen in Figure 4-5, there is a complex interaction between each of the sub-functions of the
delay board circuitry. This section describes the sequence of events that occur in the delay board starting
with the reset of the circuits, and continuing through the generating of the pulse sample outputs. A
detailed description of individual circuitry blocks on the Digital Delay PC board follows the sequence of
events.
Figure 4-5. Digital Delay (A5) Block Diagram
Series 8500A Peak Power Meters
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Manual No. 20790, Rev C, November 1998
Summary of Contents for 8501A
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