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GE OpenVPX VPXcel6 SBC622, Hardware Reference Manual

The GE OpenVPX VPXcel6 SBC622 is a powerful single board computer designed for rugged environments. To ensure smooth operation, make sure to consult the comprehensive Hardware Reference Manual, available for free download from our website. Discover the full potential of this product by accessing the manual today.

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8  SBC622 Hardware Reference Manual

List of Tables 

Table 1 Fabric Support for SBC622. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 1-1 Jumpers, Headers, Connectors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 1-2 E5 and E506 Front Panel COM3 Port Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 1-3 E7 COM1/COM2 Mode, GbE Routing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 1-4 E500  XMC1 NV Memory Write Enable/Disable; SMBus Disable/Enable . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 1-5 E501  XMC2 NV Memory Write Enable/Disable; SMBus Disable/Enable . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 1-6 E502 RTC Reg Clr; CMOS Clr  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 1-7 E503 Expansion Plane (PCIe) Bus Configuration   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 1-8 E504 Flash Descriptor Override /PCIe NT Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 1-9 E505 SYSRESET# Control /Onboard Flash Disable   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 1-10 E32 RS422 Termination Selection for COM1/COM2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 2-1 Partial List of Display Modes Supported for Analog  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 2-2 Partial List of Display Modes Supported for Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 2-3 PCI Device/Vendor IDs and Bus Number  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 3-1 Control/Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 3-2 Board Revision Register (0x601)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 3-3 Board Configuration Register 2 (0x603)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 3-4 Board Configuration Register 3 (0x604)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 3-5 Board Status Register 1 (Alarm Status Register) (0x606) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 3-6 Watchdog Timer Control Status Register (WCSR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 3-7 Watchdog Timer Control (WDT) Status Register (WCSR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 3-8 Control Register 1 (0x620)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 3-9 Control Register 2 (0x621)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 3-10 Control Register 3 (0x622) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 3-11 TCSR1 Bit Mapping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 3-12 Timer Control Status Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 3-13 Timer Control Status Register Bit Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 3-14 Timer x Clock Select  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 3-15 GPIO Out Register (0x640) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 3-16 GPIO In Register (0x641)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 3-17 GPIO Direction Register (0x642)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 3-18 GPIO Interrupt Enable Register (0x643)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 3-19 GPIO Level/Edge Register (0x644)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 3-20 GPIO Active Low/High Register (0x645)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 3-21 GPIO Both Edges Register (0x646)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 3-22 GPIO Interrupt Status Register (0x647)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table A-1 Power Management (P0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table A-2 Power Management (J0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table A-3 10 GbE (KX4) Data Plane (P1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table A-4 10 GbE (KX4) Data Plane (J1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Summary of Contents for OpenVPX VPXcel6 SBC622

Page 1: ...ication No 500 9300527818 000 Rev B Hardware Reference VPXcel6 SBC622 6U VPX Single Board Computer THE SBC622 IS DESIGNED TO MEET THE EUROPEAN UNION EU RESTRICTIONS OF HAZARDOUS SUBSTANCE ROHS DIRECTIVE 2002 95 EC CURRENT REVISION ...

Page 2: ...Document History Hardware Reference Document Number 500 9300527818 000 Rev B March 18 2011 ...

Page 3: ... 31 1 8 Installing or Removing a PMC Card 32 1 8 1 Installing 3 3 V or 5 0 V VIO Keypin 32 1 9 Front Panel of SBC622 Convection Cooled Version 34 1 9 1 Connectors 34 1 9 2 LEDs 36 1 10 SBC622 Rear I O Support 38 2 Standard Features 39 2 1 Functional Definitions 40 2 1 1 Core i7 Dual Core Processor 40 2 1 2 Mobile Intel QM57 Express Chipset 40 2 1 3 Volatile Memory DDR3 Main Memory Array 41 2 1 4 N...

Page 4: ...gister 0x601 51 3 2 3 Board Configuration Register 1 0x602 51 3 2 4 Board Configuration Register 2 0x603 51 3 2 5 Board Configuration Register 3 0x604 52 3 2 6 VPX Geographical Address GA 0x605 53 3 2 7 Board Status Register 1 Alarm Status Register 0x606 53 3 2 8 Board Status Register 2 0x607 53 3 2 9 Board ID Word 0x608 53 3 2 10 Board Feature Set Word 0x60A 53 3 2 11 Watchdog Keepalive Register ...

Page 5: ... P3 J3 Connector 72 A 1 5 Backplane P4 J4 Connector 73 A 1 6 Backplane P5 J5 Connector 74 A 1 7 Backplane P6 J6 Connector 75 A 2 Serial Port Connector RJ45 J10 76 A 3 USB Connectors and Pinout J1 J3 76 A 4 Gigabit Ethernet Connector and Pinout J2 82580 77 A 5 PMC Site 1 Connector and Pinouts 78 A 5 1 PMC Connector and Pinouts J11 78 A 5 2 PMC Connector and Pinouts J12 79 A 5 3 PMC Connector and Pi...

Page 6: ...nual B 5 Boot Setup Menu 95 B 6 Security Setup Menu 96 B 7 Save Exit Menu 97 C Appendix C Specifications and Physical Description 98 C 1 Specifications 98 C 2 Heatsink and Conduction Plate Members 98 C 3 Reliability Requirements 98 ...

Page 7: ...Connector Locations SBC622 67 Figure A 2 VPX Connector 68 Figure A 3 Serial Connector J10 76 Figure A 4 USB Port J1 J3 76 Figure A 5 GbE Connector J2 77 Figure A 6 PMC Site 1 Connector and Pinouts J11 78 Figure A 7 PMC Site 1 Connector and Pinouts J12 79 Figure A 8 PMC Site 1 Connector and Pinouts J13 80 Figure A 9 PMC Site 1 Connector and Pinouts J14 81 Figure A 10 XMC Site 1 Connector and Pinout...

Page 8: ...vision Register 0x601 51 Table 3 3 Board Configuration Register 2 0x603 51 Table 3 4 Board Configuration Register 3 0x604 52 Table 3 5 Board Status Register 1 Alarm Status Register 0x606 53 Table 3 6 Watchdog Timer Control Status Register WCSR 54 Table 3 7 Watchdog Timer Control WDT Status Register WCSR 54 Table 3 8 Control Register 1 0x620 55 Table 3 9 Control Register 2 0x621 55 Table 3 10 Contr...

Page 9: ... Site 1 Connector Pinouts J11 78 Table A 19 PMC Site 1 Connector Pinouts J12 79 Table A 20 PMC Site 1 Connector Pinouts J13 80 Table A 21 PMC Site 1 Connector Pinouts J14 81 Table A 22 XMC1 Site 1 Connector Pinouts J15 82 Table A 23 XMC1 Site 1 Connector Pinouts J16 83 Table A 24 PMC Site 2 Connector Pinouts J21 84 Table A 25 PMC Site 2 Connector Pinouts J22 85 Table A 26 PMC Site 2 Connector Pino...

Page 10: ...o optionally host additional pre boot applications such as Built In Test BIT SBC622 is compliant to the OpenVPX profile ʺMOD6 PAY 4F1Q2U2T 12 2 1 8ʺ The following table details the fabric support for this product SBC622 Board Form Factor and Packaging The SBC622 board is a single slot board assembly meeting the mechanical and electrical requirements defined in the ANSI VITA 46 0 ANSI VITA 46 9 ANS...

Page 11: ...vection Cooled Assembly Conduction Cooled Board Level 4 and Level 5 The SBC622 conduction cooled board is a 6U single slot VPX board meeting the mechanical requirements defined in the VITA 46 0 specification The SBC622 conduction option is defined for extended temperature Level 4 and Level 5 operation in rugged environments using a conduction cooled chassis Conduction cooled assembly does not supp...

Page 12: ...gabit Ethernet port 2x USB ports 1x COM port Rear I O x16 or 4x 4 PCIe NTB capable 2x 10 Gigabit Ethernet GbE ports 4x GbE ports 1x DVI VGA 3x SATA Ports 2x COM Ports 6x USB ports 8x GPIO 2x XMC PMC I O signals Optional conduction cooled version Optional extended operating temperature range Temperature sensor for core CPU PCH monitoring Trusted Platform Module TPM Board Management Micro controller...

Page 13: ...nd a Mobile Intel QM57 Express Chipset Core i7 is the next generation of 64 bit multi core mobile processors built on 32 nanometer process technology The major feature of the Core i7 ECC is the DDR3 memory and graphics controller integration with the Dual Core CPU Features of the Core i7 Processor Intel Intelligent Power Technology allows processors to operate at optimal frequency Intelligent perf...

Page 14: ...vice on the PCH SPI bus The BIOS also provides ROM code that supports remote booting from any of the Ethernet ports Target Operating Systems SBC622 hardware supports Windows Linux and VxWorks operating systems The following notes provide information to properly install certain versions of the operating systems Windows XP SP3 NOTE There is a known issue with certain brands and models of USB CDROM d...

Page 15: ... 27 January 2003 on Waste Electrical and Electronic Equipment WEEE IEEE 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan Architecture June 1993 IEEE 1386 2001 IEEE Standard for a Common Mezzanine Card CMC Family June 2001 IEEE 1386 1 2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC June 2001 Intel Low Pin Count Interface Specification Rev 1 1 August 2002...

Page 16: ...erʹs Labs UL 94 Standard for Tests for Flammability of Plastic Materials for Parts in Devices and Appliance Edition 5 October 1996 USB Universal Serial Bus Specification Rev 2 0 April 2000 Intel Core i7 600 i5 500 i5 400 and i3 300 Mobile Processor Series Datasheet Volume 1 Intel Document Number 322812 January 2010 Intel Core i7 600 i5 500 i5 400 and i3 300 Mobile Processor Series Datasheet Volume...

Page 17: ...ual Volume 2A Instruction Set Reference A M Intel 64 and IA 32 Architectures Software Developerʹs Manual Volume 2B Instruction Set Reference N Z Intel 64 and IA 32 Architectures Software Developerʹs Manual Volume 3A System Programming Guide Part 1 Intel 64 and IA 32 Architectures Software Developerʹs Manual Volume 3B System Programming Guide Part 2 Intel 64 Architecture x2APIC Specification Intel ...

Page 18: ...2 Standard Features describes the product s standard features and functionality Chapter 3 CPLD Control and Status Registers describes the registers provided by the CPLD Maintenance provides GE s contact information relative to the care and maintenance of the unit Appendix A Connectors and Pinouts illustrates and defines the connectors included in the unit s I O ports Appendix B BIOS Setup Utility ...

Page 19: ...stitutes a definite safety hazard Keep Away from Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and disc...

Page 20: ...eath to personnel CAUTION CAUTION denotes a hazard It calls attention to an operating procedure practice or condition which if not correctly performed or adhered to could result in damage to or destruction of part or all of the system NOTE NOTE denotes important information It calls attention to a procedure practice or condition which is essential to highlight TIP Tip denotes a bit of expert infor...

Page 21: ...oard s heat damage and other visible contamination All claims arising from shipping damage should be filed with the carrier and a complete report sent to GE Customer Care 1 2 Handling Precautions CAUTION Some of the components assembled on GE s products may be sensitive to electrostatic discharge and damage may occur on boards that are subjected to a high energy electrostatic field When the board ...

Page 22: ...on page 23 The definitions of the jumpers headers and connectors are included in Table 1 1 Jumpers Headers Connectors on page 24 All jumpers marked User Configured in the following tables may be changed or modified by the user All jumpers marked Factory Configured should not be modified by the user Care must be taken when making jumper modifications to ensure against improper settings or connectio...

Page 23: ...7 Processor Mobile Intel QM57 Express Chipset PCIe Switch PEX8648 Quad GbE 82580 PMC1 Bridge Pericom PMC2 Bridge Pericom Dual 10 GbE 82599 E5 E506 E501 E500 E503 E504 E7 E505 E17 P0 P1 P2 P3 P4 P5 P6 J11 J12 J13 J14 J21 PMC XMC SITE 2 PMC XMC SITE 1 J22 J23 J24 J15 J16 J25 J26 P103 P104 S10 J2 E502 E32 Key 2 Key 3 Key 1 R1066 R1065 R215 On Back ...

Page 24: ...l J10 Serial Port Connector COM3 Front Panel J11 J12 J13 and J14 PMC Site 1 Connectors Onboard J15 J16 XMC Site 1 Connectors Onboard J21 J22 J23 J24 PMC Site 2 Connectors Onboard J25 J26 XMC Site 2 Connectors Onboard Jumpers Function E5 Front Panel COMPort Signal Configuration RS232 RS422 E7 GbE to VPX backplane or Front Panel E17 CPLD JTAG Programming Header Factory use only E32 RS422 Termination...

Page 25: ... jumper installed Out jumper not installed The following tables display the jumper positions for the SBC622 NOTE Except as indicated all jumpers are by default Not Installed The default settings are indicated in bold NOTE All jumper switch settings are User Configured Table 1 2 E5 and E506 Front Panel COM3 Port Configuration Table 1 3 E7 COM1 COM2 Mode GbE Routing Table 1 4 E500 XMC1 NV Memory Wri...

Page 26: ...ctory Set Not Installed 3 4 Normal CPU Behavior CMOS Clear Note E502 is not loaded for conduction cooled options Shorting across the pads of R1065 is equivalent to installing jumper on pins 3 4 E503 Function 3 4 1 2 1 x8 2 x4 Ports Open Open 2 x8 Ports Open Shorted 1 x16 Port Shorted Open 4 x4 Ports Shorted Shorted E504 Position Not Installed Installed 1 2 Transparent PCIe Non Transparent PCIe 3 4...

Page 27: ...ersions have screw driven wedge locks at the top and bottom of the board to provide the necessary mechanical thermal interface Correct adjustment requires a calibrated torque wrench with a hexagonal head of size 3 32ʺ 2 38 mm set to between 0 6 and 0 8 Nm In an air cooled development enclosure when taking I O connections from the backplane connectors use of GE s I O modules or some equivalent sys ...

Page 28: ...ule VPX6UX604 and an Open VPX compliant backplane A null modem 9 way D to 9 way D type cable for connecting COM1 to a control terminal or HyperTerminal For the Ethernet port a CAT5 or better straight through patch cable for 10 100 1000Base TX A VGA monitor and suitable cables USB Keyboard Similar antistatic and safety precautions apply when handling and or installing I O modules as for the board 1...

Page 29: ...de of the heatsink is to be greater than 450 LFM 3 Choose chassis slot If the SBC622 is to be the VPX system controller choose the appropriately marked VPX slot The SBC622 does not require jumpers for enabling disabling the system controller function 4 Insert the SBC622 into a VPX chassis system controller or peripheral slot a While ensuring that the board is properly aligned and oriented in the s...

Page 30: ...30 SBC622 Hardware Reference Manual Figure 1 2 SBC622 in Chassis VPX Backplane SBC622 inserted into Chassis ...

Page 31: ... except short across the pads of R1065 at step 2 1 7 2 BIOS Setup The SBC622 has an onboard BIOS Setup program that controls many configuration options These options are saved in a special non volatile battery backed memory chip and are collectively referred to as the board s CMOS Configuration The CMOS contents are preserved as long as battery power is applied to the VBAT pin on the VPX backplane...

Page 32: ...cedure is applicable for both removal and installation of PMC modules and fully populated PMC cards See Figure 1 3 PMC Installed onto 2 PMC Site Model on page 33 1 Remove the mezzanine screws 2 Separate the mezzanine connector while lifting and rotating the mezzanine board Pull away from the front panel 3 Remove the PMC modules by removing two mounting screws per module This step will be necessary...

Page 33: ...Installation and Setup 33 Figure 1 3 PMC Installed onto 2 PMC Site Model F ...

Page 34: ...the SBC622 The SBC622 Front Panel provides access to XMC PMC1 XMC PMC Site 1 slot XMC PMC2 XMC PMC Site 2 slot RST Manual reset switch BPHF Status LEDs COM3 COM3 serial port LAN 10 100 1000 Ethernet Connector USB Two USB Serial Ports NOTE If a board reset is required via the manual reset switch ensure that the switch is not repeatedly pressed during the power up reset cycle ...

Page 35: ...Installation and Setup 35 Figure 1 4 Front Panel Layout LED Status Convection Cooled SBC622 RST B P H F C O M 3 L A N X M C P M C 1 X M C P M C 2 ...

Page 36: ...ptional has detected an error condition When the Processor PCH are in the Power Management state S5 all four front panel LEDs illuminate The two LEDs integrated in the RJ45 receptacle for GbE ports provide link activity and link speed status information for the Ethernet ports on SBC622 as follows left to right on the panel Link Activity GREEN illuminates during link flashing during active data tra...

Page 37: ...Installation and Setup 37 Figure 1 5 Front Panel SBC622 Isometric View Convection cooled F F ...

Page 38: ...terface on page 44 These signals are accessed by the use of a rear transition module RTM which terminates the signals into industry standard connectors Connector pinouts and orientation for the SBC622 are defined in Appendix A Connectors and Pinouts The SBC622 processor board is designed to support RTM VPX6U604 Other RTMs may not support all available SBC622 rear I O mentioned above RTM connection...

Page 39: ... 10 Gig E Front IO ETI BMM Super IO MUX MUX MUX Quad GbE CPLD TPM PCIe to PCI X PCIe to PCI X QM57 SATA to PATA XMC PMC Site 2 Core i7 NAND Flash 2 4 GByte DDR3 2 4 GByte DDR3 XMC PMC Site 1 PCIe Switch 10 GbE COM3 COM4 GbE 2x USB x4 x4 FDI DMI LPC x16 x16 4x4 x8 x8 PMC1 I O 8x GPIO 4x USB DVI VGA XMC 2 I O 3x SATA PMC 2 I O ...

Page 40: ...ption SIMD SSE 4 1 4 2 Root complex for PMC XMC site 1 the 10 GbE Ethernet Controller and the VPX PCIe expansion plane x16 PCIe interface to onboard switch 2 1 2 Mobile Intel QM57 Express Chipset The Mobile Intel QM57 Express Chipset contains a DMI serial link interface to the Core i7 processors plus internal logic to control data transfers between the Core i7 memory controller and the various I O...

Page 41: ... SMBus of the PCH 2 1 5 SPI Bus Resources The SBC622 supports BIOS firmware code using the Mobile Intel QM57 Express Chipset SPI bus channel The BIOS firmware is contained in one 4 MByte size SPI bus Flash part The SPI flash parts can be in circuit programmed with updates after initial programming of the SPI bus parts which occurs off of the unit 2 1 6 LPC Bus Resources The LPC bus on SBC622 suppo...

Page 42: ... speed and link activity on the RJ45 receptacle Backplane selection of the GbE port provides no LED support Ports 1 and 2 provide 10 100 1000 T support and routed to P4 one channel mux d with the Front Panel Ports 3 and 4 provide 10 100 1000 BX support and routed to P4 GbE ports support remote boot from either the Front or Rear configuration 2 1 10 Dual 10 GbE The SBC622 supports Dual 10 GbE Ports...

Page 43: ...ter ETC with quarter second resolution and provides thirty four years of total time accumulation 2 1 15 Trusted Platform module TPM The SBC622 provides trusted platform support via the Atmel AT97SC3204 TPM offering Hardware asymmetric crypto engine 2048 bit RSA sign EEPROM storage for RSA keys NV storage for 1280 bytes of user data The TPM includes a cryptographic accelerator capable of computing ...

Page 44: ...ckplane VS1 and VS3 power rails are accessed by the SBC622 following the functional requirements for VPX boards in VITA 46 0 This circuit also controls the Power LED on the front panel of the assembly See Section 1 9 2 LEDs on page 36 Live insertion as defined in VITA 1 4 is not supported on the SBC622 The VS1 and VS3 rails are used for SBC622 circuits and at the PMC site The VCC_12V_AUX and VCC_ ...

Page 45: ...th the 1 07 GHz processor option video quality may degrade slightly VGA Interface The VGA interface can be accessed using an included adapter to adapt from the DVI D front panel connector to a HD15 VGA connector Supported display modes for VGA include Table 2 1 Partial List of Display Modes Supported for Analog Bits Per Pixel Frequency in Hz Resolution 16 bit 32 bit 640 x 480 800 x 600 60 72 75 85...

Page 46: ...TA 46 9 2 3 6 SATA Ports There are five SATA ports Two SATA channels are routed to the optional NAND Flash Drive s Three SATA channels are routed to P6 and can be accessed using RTMs which terminate into standard SATA connectors The SATA interface is provided by the Intel QM57 Express Chipset Platform Controller Hub The SATA interface supports up to four channels 2 3 7 COM Ports 1 and 2 COM Ports ...

Page 47: ...0 28 04 00E4 USB EHCI Controller Intel Mobile QM57 Express PCH 3B34 8086 00 29 00 00E8 DMI to PCI Bridge Intel Mobile QM57 Express PCH 2448 8086 00 30 00 00F0 PCI to LPC Bridge Intel Mobile QM57 Express PCH 3B07 8086 00 31 00 00F8 SATA Controller Intel Mobile QM57 Express PCH 3B2E 8086 00 31 02 00FA SMBus Controller Intel Mobile QM57 Express PCH 3B30 8086 00 31 03 00FB SATA Controller Intel Mobile...

Page 48: ...are a Type A host interface capable of supporting USB 1 0 1 1 and 2 0 targets Front Panel USB Ports are capable of supporting 1 5A power One GbE via RJ45 For further information on the Front Panel See Section 1 9 Front Panel of SBC622 Convection Cooled Version on page 34 2 4 Built In TEST BIT BIT functionality is provided by hardware in conjunction with installed software BIT is included for fault...

Page 49: ...C622 provides a bootable NAND Flash system and 512 KBits of non volatile SEEPROM 3 1 CPLD Description The SBC622 CPLD provides a general purpose I O port Watchdog Timer and general purpose timers The block diagram for the CPLD is shown in the figure below Figure 3 1 Block Diagram for CPLD The CPLD contains two LPC interfaces the RT suite LPC interface and the 8 bit GPIO port LPC interface RT LPC I...

Page 50: ...tchdog Timer CSR WCSR Word Read Write 610 to 615 Board ID String Registers Read Only 616 to 61F Reserved 620 Control Register 1 Read Write 621 Control Register 2 Read Write 622 Control Register 3 Read Write 623 IRQ Enable Register Read Write 624 Drive Links Low Register Read Write 625 to 62B Reserved 62C 62D Reserved for unused Timers 1 and 2 630 Timer Control Status Register TCSR3 Read Write 631 ...

Page 51: ...ed on the SBC622 3 2 4 Board Configuration Register 2 0x603 The SBC622 only implements bit 0 of this register Table 3 2 Board Revision Register 0x601 Bits Meaning D7 to D5 Number revision artwork level of the hardware build state 1 Revision 1 2 Revision 2 3 Revision 3 4 Revision 4 Letter revision of the hardware build state 0x0 Revision A 0x1 Revision B D4 to D0 0x18 Revision Y 0x19 Revision YA 0x...

Page 52: ... Reads 0 D5 Main Hub Write Protect 1 Write protected 0 Write enabled D4 Main Boot Flash Write Enable by Software Lock 1 Write protected 0 Writes enabled D3 Flash Hard Drive installed 1 Flash Hard Drive is installed 0 Flash Hard Drive is not installed D2 NVRAM Write Protect 1 Write protected 0 Writes enabled D1 Flash Hard Drive Write Protect 1 Write protected 0 Writes enabled D0 Main Boot Flash Wri...

Page 53: ...et 0x0D within the selected timeout period The data written to this location is irrelevant 3 2 12 Watchdog Timer CSR WCSR Word 0x60E The SBC622 provides a programmable Watchdog Timer WDT which can be used to reset the system if software integrity fails The WDT is controlled and monitored by the WDT Control Status Register WCSR which is located at offset 0x0E from base I O address 0x600 Table 3 5 B...

Page 54: ...bled by the application software after reset in order for the Watchdog Timer to continue to operate Once the Watchdog Timer is enabled the application software must refresh the Watchdog Timer within the selected timeout period to prevent a reset or SERR from being generated The Watchdog Timer is refreshed by performing a write to the WDT Keepalive register WKPA The data written is irrelevant 3 2 1...

Page 55: ...ffer Enable 1 Buffer Enabled default 0 Buffer Disabled D4 ISP Data buffer enable 1 Enabled 0 Disabled default D3 BMM_PS0_ISP_VPP Used to program the BMM consult the factory for use D2 BMM_PS1_ISP_CLK Used to program the BMM consult the factory for use D1 BMM_PROGRAM_EN Used to program the BMM consult the factory for use D0 ISP Data out Used to program the BMM consult the factory for use Table 3 9 ...

Page 56: ...z 500 KHz and 250 KHz Each timer may be independently enabled and each is capable of generating a system interrupt on timeout Events can be timed by either polling the timers or enabling the interrupt capability of the timer A status register allows for application software to determine which timer is the cause of any interrupt NOTE Register definitions exist for four timers two 16 bit and two 32 ...

Page 57: ...quent reads to the other timer registers do not latch new count values and may be read in any order 3 2 21 Timer Control Status Register TCSR 0x62C 0x62D 0x630 0x631 Each timer is controlled and monitored via the Timer Control Status Register TCSRx located at the following addresses The mapping of the bits in the registers is as follows Table 3 11 TCSR1 Bit Mapping Field Bits Read or Write Descrip...

Page 58: ...3 2 22 Timer 1 Value Register 0x634 Timer 1 is not implemented on SBC622 3 2 23 Timer 2 Value Register 0x636 Timer 2 is not implemented on SBC622 3 2 24 Timer 3 Value Register 0x638 Timer 3 is a 32 bit timer that is located at offset 0x38 from base I O address 0x600 When this field is read the value returned is either the current count value or the loaded value depending on the setting of TCSR3 3 ...

Page 59: ...and the signals are isolated whenever the SBC622 is powered down Figure 3 2 CPLD GPIO Interface Access The GPIO signals are sourced from the CPLD and any reset clears all output pins to inputs To prevent GPIO output pins glitching during board reset the GPIO Out Register offset 0x640 is only reset on power up Always write this register before enabling GPIO output pins Under software control each G...

Page 60: ...he edges can cause false triggering On really slow edges software may need to filter the inputs 3 2 31 GPIO Out Register 0x640 This holds the GPIO out data NOTE This register is only cleared on a power cycle 3 2 32 GPIO In Register 0x641 This reflects the current state of the GPIO pins regardless of whether they are configured as inputs or outputs Table 3 15 GPIO Out Register 0x640 Bit GPIO Pin D7...

Page 61: ...3 GPIO3 direction 1 Output 0 Input default D2 GPIO2 direction 1 Output 0 Input default D1 GPIO1 direction 1 Output 0 Input default D0 GPIO0 direction 1 Output 0 Input default Table 3 18 GPIO Interrupt Enable Register 0x643 Bit Meaning D7 GPIO7 interrupt enable 1 Enabled 0 Disabled default D6 GPIO6 interrupt enable 1 Enabled 0 Disabled default D5 GPIO5 interrupt enable 1 Enabled 0 Disabled default ...

Page 62: ...itivity 1 Edge 0 Level default Table 3 20 GPIO Active Low High Register 0x645 Bit Meaning D7 GPIO7 interrupt high or low 1 Active high or going high edge 0 Active low or going low edge default D6 GPIO6 interrupt high or low 1 Active high or going high edge 0 Active low or going low edge default D5 GPIO5 interrupt high or low 1 Active high or going high edge 0 Active low or going low edge default D...

Page 63: ...IO4 both edges 1 Both edges 0 Off default D3 GPIO3 both edges 1 Both edges 0 Off default D2 GPIO2 both edges 1 Both edges 0 Off default D1 GPIO1 both edges 1 Both edges 0 Off default D0 GPIO0 both edges 1 Both edges 0 Off default Table 3 22 GPIO Interrupt Status Register 0x647 Bit Meaning D7 GPIO7 interrupt status 1 Interrupt is active 0 No interrupt D6 GPIO6 interrupt status 1 Interrupt is active...

Page 64: ... boot the SBC622 using the PXE protocol The Ethernet must be connected through one of the front panel RJ45 connectors to boot remotely This feature allows users to create systems without the worry of disk drive reliability or the extra cost of adding NAND Flash drives BootWare Features PXE boot support Unparalleled boot sector virus protection Detailed boot configuration screens Optional disabling...

Page 65: ...erting or remov ing the board from the chassis 8 Quality of cables and I O connections If products must be returned contact GE for a Return Material Authorization RMA Number This RMA Number must be obtained prior to any return from Customer Care RMA request forms can be obtained from repairs huntsville ip ge com GE Customer Care is available at 1 800 433 2682 in North America or 1 780 401 7700 for...

Page 66: ...des the contact signal assignments for VPX connectors located on the backplane other rear I O connectors and front panel connectors In the tables listed in this appendix active low signals are identified with a trailing ʹ ʹ ʹ ʹ or ʹNʹ attached to the signal name Active high signals in a signal pair may have a trailing ʹ ʹ or ʹPʹ attached to the signal name ...

Page 67: ...etails J3 J1 J10 XDP Debug Port XDP Debug Port LEDS Intel Core i7 Processor Mobile Intel QM57 Express Chipset PCIe Switch PEX8648 Quad GbE 82580 PMC1 Bridge Pericom PMC2 Bridge Pericom Dual 10 GbE 82599 E5 E506 E501 E500 E503 E504 E7 E505 E17 P0 P1 P2 P3 P4 P5 P6 J11 J12 J13 J14 J21 PMC XMC SITE 2 PMC XMC SITE 1 J22 J23 J24 J15 J16 J25 J26 P103 P104 S10 J2 E502 E32 Key 2 Key 3 Key 1 R1066 R1065 R2...

Page 68: ...or J0 J1 J2 J3 J4 J5 and J6 of the backplane pinouts when the SBC622 is plugged in The power ground and signal assignments on the backplane connectors are defined by a combination of the following specifications OpenVPX VITA 46 0 VITA 46 4 VITA 46 6 and VITA 46 9 The following tables shows these signal assignments and pin fields for these connections The VPX Connector table pin field assignments a...

Page 69: ...3 NC Vs3 Vs3 Vs3 4 NC NC GND 12V Aux GND SYSRESET NVMRO 5 NC GA4 GND 3v3 Aux GND SMB_CLK SMB_DAT 6 GA3 GA2 GND 12V Aux GND GA1 GA0 7 TCK GND TDO TDI GND TMS TRST 8 GND NC NC GND NC NC GND J1 Pin Row I Row H Row G Row F Row E Row D Row C RowB Row A 1 Vs1 Vs1 Vs1 Vs1 NC NC NC NC NC 2 Vs1 Vs1 Vs1 Vs1 NC NC NC NC NC 3 Vs3 Vs3 Vs3 Vs3 NC Vs3 Vs3 Vs3 Vs3 4 GND NC NC GND 12V Aux GND SYSRESET NVMRO GND 5 ...

Page 70: ... NC GND NC NC GND 13 NC GND NC NC GND NC NC 14 GND NC NC GND NC NC GND 15 MSKRST GND NC NC GND NC NC 16 GND NC NC GND NC NC GND J1 Pin Row I Row H Row G Row F Row E Row D Row C RowB Row A 1 VPX_GDISC1 GND GND 10G1_T0 10G1_T0 GND GND 10G1_R0 10G1_R0 2 GND 10G1_T1 10G1_T1 GND GND 10G1_R1 10G1_R1 GND GND 3 VBAT GND GND 10G1_T2 10G1_T2 GND GND 10G1_R2 10G1_R2 4 GND 10G1_T3 10G1_T3 GND GND 10G1_R3 10G1...

Page 71: ...E_RX13 GND 15 Reserved GND PCIE_TX14 PCIE_TX14 GND PCIE_RX14 PCIE_RX14 16 GND PCIE_TX15 PCIE_TX15 GND PCIE_RX15 PCIE_RX15 GND J2 Pin Row I Row H Row G Row F Row E Row D Row C Row B Row A 1 Reserved GND GND PCIE_TX0 PCIE_TX0 GND GND PCIE_RX0 PCIE_RX0 2 GND PCIE_TX1 PCIE_TX1 GND GND PCIE_RX1 PCIE_RX1 GND GND 3 Reserved GND GND PCIE_TX2 PCIE_TX2 GND GND PCIE_RX2 PCIE_RX2 4 GND PCIE_TX3 PCIE_TX3 GND G...

Page 72: ..._DTR n a GND J14 57 J14 59 GND J14 58 J14 60 16 GND GND J14 61 J14 63 GND J14 62 J14 64 GND Table A 8 PMC I O Site 1 and COM1 J3 Pin Row I RS232 Mode Row I RS 422 Mode Row H Row G Row F Row E Row D Row C Row B Row A 1 COM1_RX COM1 RXD GND GND J14 1 J14 3 GND GND J14 2 J14 4 2 GND GND J14 5 J14 7 GND GND J14 6 J14 8 GND GND 3 COM1_TX COM1_TXD GND GND J14 9 J14 11 GND GND J14 10 J14 12 4 GND GND J14...

Page 73: ...D GND MDIB3T_N MDIB3T_P GND MDIB2T_N MDIB2T_P GND 15 COM2_DTR n a GND MDIA1T_N MDIA1T_P GND MDIA0T_N MDIA0T_P 16 GND GND MDIA3T_N MDIA3T_P GND MDIA2T_N MDIA2T_P GND Pin Row I RS232 Mode Row I RS 422 Mode Row H Row G Row F Row E Row D Row C Row B Row A 1 COM2_RX COM2_RXD GND GND J16 A5 J16 B5 GND GND J16 D5 J16 E5 2 GND GND J16 A7 J16 B7 GND GND J16 D7 J16 E7 GND GND 3 COM2_TX COM2_TXD GND GND J16 ...

Page 74: ...24 50 J24 52 14 GND J24 53 J24 55 GND J24 54 J24 56 GND 15 NC GND J24 57 J24 59 GND J24 58 J24 60 16 GND J24 61 J24 63 GND J24 62 J24 64 GND Pin Row I Row H Row G Row F Row E Row D Row C Row B Row A 1 HDA_SDO GND GND J24 1 J24 3 GND GND J24 2 J24 4 2 GND J24 5 J24 7 GND GND J24 6 J24 8 GND GND 3 HDA_RST GND GND J24 9 J24 11 GND GND J24 10 J24 12 4 GND J24 13 J24 15 GND GND J24 14 J24 16 GND GND 5 ...

Page 75: ...VI_TXCN GND GPIO3 USB_P2_PWR GND 15 VGA_BLUE GND SATA_RXN SATA2_RXP GND SATA3_RXP SATA3_RXN 16 GND NC DVI_HOT_PLUG GND SATA2_TXN SATA2_TXP GND Pin Row I Row H Row G Row F Row E Row D Row C Row B Row A 1 NC GND GND J26 A5 J26 B5 GND GND J26 D5 J26 E5 2 GND J26 A7 J26 B7 GND GND J26 D7 J26 E7 GND GND 3 VGA_DDC_CLK GND GND J26 A9 J26 B9 GND GND J26 D9 J26 E9 4 GND J26 A15 J26 B15 GND GND J26 D15 J26 ...

Page 76: ...picts a representation of the connectors and the table that follows shows the pinout same for each Figure A 4 USB Port J1 J3 Table A 15 Serial Connector Pinout J10 Pin RS232 Default Mode RS422 Mode 1 DCD RXD 2 RTS RTS 3 GND TXD 4 TX TXD 5 RX RXD 6 GND CTS 7 CTS CTS 8 DTR RTS NOTE See the appropriate table of jumper and switch settings for configuring A cable is available PN 42G7602 0003 to convert...

Page 77: ...t diagram for the Gigabit Ethernet connector is shown in the following figure and table Figure A 5 GbE Connector J2 Table A 17 Ethernet Connectors 10 100 1000 Mbit J2 Pin Signals Signals 1 MDI0 TX RX0 2 MDI0 TX RX0 3 MDI1 TX RX1 4 MDI2 TX RX2 5 MDI2 TX RX2 6 MDI1 TX RX1 7 MDI3 TX RX3 8 MDI3 TX RX3 ...

Page 78: ...r J11 Left Side Right Side Left Side Right Side Pin Name Pin Name Pin Name Pin Name 1 JTAG TCK 2 12 V 33 FRAME 34 GND 3 GND 4 INTA 35 GND 36 IRDY 5 INTB 6 INTC 37 DEVSEL 38 5 V 7 BMODE1 8 5 V 39 PCIXCAP 40 LOCK 9 INTD 10 NC 41 SDONE 42 3 3V 11 GND 12 NC 43 PAR 44 GND 13 CLK 14 GND 45 PMC VIO 46 AD 15 15 GND 16 GNT0 47 AD 12 48 AD 11 17 REQ0 18 5 V 49 AD 9 50 5 V 19 PMC VIO 20 AD 31 51 GND 52 C BE ...

Page 79: ...AG_TRST 33 GND 34 NC 3 JTAG_TMS_2 4 JTAG_TDO 35 TRDY 36 3 3V 5 JTAG_TDI 6 GND 37 GND 38 STOP 7 GND 8 NC 39 PERR 40 GND 9 NC 10 NC 41 3 3V 42 SERR 11 3 3V 12 3 3V 43 C BE 1 44 GND 13 RST 14 GND 45 AD 14 46 AD 13 15 3 3V 16 GND 47 M66EN 48 AD 10 17 PME 18 GND 49 AD 8 50 3 3V 19 AD 30 20 AD 29 51 AD 7 52 NC 21 GND 22 AD 26 53 3 3V 54 NC 23 AD 24 24 3 3V 55 NC 56 GND 25 IDSEL 26 AD 23 57 NC 58 NC 27 3...

Page 80: ... AD 46 5 CBE 6 6 CBE 5 37 AD 45 38 GND 7 CBE 4 8 GND 39 PMC VIO 40 AD 44 9 PMC VIO 10 PAR64 41 AD 43 42 AD 42 11 AD 63 12 AD 62 43 AD 41 44 GND 13 AD 61 14 GND 45 GND 46 AD 40 15 GND 16 AD 60 47 AD 39 48 AD 38 17 AD 59 18 AD 58 49 AD 37 50 GND 19 AD 57 20 GND 51 GND 52 AD 36 21 PMC VIO 22 AD 56 53 AD 35 54 AD 34 23 AD 55 24 AD 54 55 AD 33 56 GND 25 AD 53 26 GND 57 PMC VIO 58 AD 32 27 GND 28 AD 52 ...

Page 81: ... 11 P3 D3 12 P3 A3 13 P3 F4 14 P3 C4 15 P3 E4 16 P3 B4 17 P3 E5 18 P3 B5 19 P3 D5 20 P3 A5 21 P3 F6 22 P3 C6 23 P3 E6 24 P3 B6 25 P3 E7 26 P3 B7 27 P3 D7 28 P3 A7 29 P3 F8 30 P3 C8 31 P3 E8 32 P3 B8 33 P3 E9 34 P3 B9 35 P3 D9 36 P3 A9 37 P3 F10 38 P3 C10 39 P3 E10 40 P3 B10 41 P3 E11 42 P3 B11 43 P3 D11 44 P3 A11 45 P3 F12 46 P3 C12 47 P3 E12 48 P3 B12 49 P3 E13 50 P3 B13 51 P3 D13 52 P3 A13 53 P3...

Page 82: ... 4 MRSTO 5 NC 5 NC 5 3 3V 5 NC 5 NC 5 5V 6 GND 6 GND 6 TMS 6 GND 6 GND 6 12V 7 NC 7 NC 7 3 3V 7 NC 7 NC 7 5V 8 GND 8 GND 8 TDI 8 GND 8 GND 8 12V 9 NC 9 NC 9 NC 9 NC 9 NC 9 5V 10 GND 10 GND 10 TDO 10 GND 10 GND 10 GA0 11 TX0 11 TX0 11 MBIST 11 TX1 11 TX1 11 5V 12 GND 12 GND 12 GA1 12 GND 12 GND 12 PRS 13 TX2 13 TX2 13 3 3V 13 TX3 13 TX3 13 5V 14 GND 14 GND 14 GA2 14 GND 14 GND 14 MSDA 15 NC 15 NC 1...

Page 83: ... NC 3 NC NC NC NC NC NC 4 NC NC NC NC NC NC 5 NC P4 A1 P4 B1 NC P4 D1 P4 E1 6 NC NC NC NC NC NC 7 NC P4 B2 P4 C2 NC P4 E2 P4 F2 8 NC NC NC NC NC NC 9 NC P4 A3 P4 B3 NC P4 D3 P4 E3 10 NC NC NC NC NC NC 11 NC NC NC NC NC NC 12 NC NC NC NC NC NC 13 NC NC NC NC NC NC 14 NC NC NC NC NC NC 15 NC P4 B4 P4 C4 NC P4 E4 P4 F4 16 NC NC NC NC NC NC 17 NC P4 A5 P4 B5 NC P4 D5 P4 E5 18 NC NC NC NC NC NC 19 NC P...

Page 84: ...tor J21 Left Side Right Side Left Side Right Side Pin Name Pin Name Pin Name Pin Name 1 JTAG TCK 2 12 33 FRAME 34 GND 3 GND 4 INTA 35 GND 36 IRDY 5 INTB 6 INTC 37 DEVSEL 38 5 V 7 BMODE1 8 5 V 39 PCIXCAP 40 LOCK 9 INTD 10 NC 41 SDONE 42 3 3V 11 GND 12 NC 43 PAR 44 GND 13 CLK 14 GND 45 PMC VIO 46 AD 15 15 GND 16 GNT0 47 AD 12 48 AD 11 17 REQ0 18 5 V 49 AD 9 50 5 V 19 PMC VIO 20 AD 31 51 GND 52 C BE ...

Page 85: ...TAG_TRST 33 GND 34 NC 3 JTAG_TMS_2 4 JTAG_TDO 35 TRDY 36 3 3V 5 JTAG_TDI 6 GND 37 GND 38 STOP 7 GND 8 NC 39 PERR 40 GND 9 NC 10 NC 41 3 3V 42 SERR 11 3 3V 12 3 3V 43 C BE 1 44 GND 13 RST 14 GND 45 AD 14 46 AD 13 15 3 3V 16 GND 47 M66EN 48 AD 10 17 PME 18 GND 49 AD 8 50 3 3V 19 AD 30 20 AD 29 51 AD 7 52 NC 21 GND 22 AD 26 53 3 3V 54 NC 23 AD 24 24 3 3V 55 NC 56 GND 25 IDSEL 26 AD 23 57 NC 58 NC 27 ...

Page 86: ...6 AD 46 5 CBE 6 6 CBE 5 37 AD 45 38 GND 7 CBE 4 8 GND 39 PMC VIO 40 AD 44 9 PMC VIO 10 PAR64 41 AD 43 42 AD 42 11 AD 63 12 AD 62 43 AD 41 44 GND 13 AD 61 14 GND 45 GND 46 AD 40 15 GND 16 AD 60 47 AD 39 48 AD 38 17 AD 59 18 AD 58 49 AD 37 50 GND 19 AD 57 20 GND 51 GND 52 AD 36 21 PMC VIO 22 AD 56 53 AD 35 54 AD 34 23 AD 55 24 AD 54 55 AD 33 56 GND 25 AD 53 26 GND 57 PMC VIO 58 AD 32 27 GND 28 AD 52...

Page 87: ...11 P5 D3 12 P5 A3 13 P5 F4 14 P5 C4 15 P5 E4 16 P5 B4 17 P5 E5 18 P5 B5 19 P5 D5 20 P5 A5 21 P5 F6 22 P5 C6 23 P5 E6 24 P5 B6 25 P5 E7 26 P5 B7 27 P5 D7 28 P5 A7 29 P5 F8 30 P5 C8 31 P5 E8 32 P5 B8 33 P5 E9 34 P5 B9 35 P5 D9 36 P5 A9 37 P5 F10 38 P5 C10 39 P5 E10 40 P5 B10 41 P5 E11 42 P5 B11 43 P5 D11 44 P5 A11 45 P5 F12 46 P5 C12 47 P5 E12 48 P5 B12 49 P5 E13 50 P5 B13 51 P5 D13 52 P5 A13 53 P5 ...

Page 88: ... 5 NC 5 3 3V 5 NC 5 NC 5 5V 6 GND 6 GND 6 TMS 6 GND 6 GND 6 12V 7 NC 7 NC 7 3 3V 7 NC 7 NC 7 5V 8 GND 8 GND 8 TDI 8 GND 8 GND 8 12V 9 NC 9 NC 9 NC 9 NC 9 NC 9 5V 10 GND 10 GND 10 TDO 10 GND 10 GND 10 GA0 11 TX0 11 TX0 11 MBIST 11 TX1 11 TX1 11 5V 12 GND 12 GND 12 GA1 12 GND 12 GND 12 PRS 13 TX2 13 TX2 13 3 3V 13 TX3 13 TX3 13 5V 14 GND 14 GND 14 GA2 14 GND 14 GND 14 MSDA 15 NC 15 NC 15 NC 15 NC 15...

Page 89: ...C NC NC NC 3 NC NC NC NC NC NC 4 NC NC NC NC NC NC 5 NC P6 A1 P6 B1 NC P6 D1 P6 E1 6 NC NC NC NC NC NC 7 NC P6 B2 P6 C2 NC P6 E2 P6 F2 8 NC NC NC NC NC NC 9 NC P6 A3 P6 B3 NC P6 D3 P6 E3 10 NC NC NC NC NC NC 11 NC NC NC NC NC NC 12 NC NC NC NC NC NC 13 NC NC NC NC NC NC 14 NC NC NC NC NC NC 15 NC P6 B4 P6 C4 NC P6 E4 P6 F4 16 NC NC NC NC NC NC 17 NC P6 A5 P6 B5 NC P6 D5 P6 E5 18 NC NC NC NC NC NC ...

Page 90: ...installing from a bootable disk For example when installing an operating system from a CD enter the First Boot menu and use the arrows keys to highlight ATAPI CD ROM Drive Press ENTER to continue with system boot This feature is accessed by pressing the F7 key at the very beginning of the boot cycle The selection made from this screen applies to the current boot only and will not be used during th...

Page 91: ...ain screen The information displayed on your screen will reflect your actual system Table B 2 BIOS Main Menu Aptio Setup Utility Copyright C 2009 American Megatrends Inc Main Advanced Chipset Boot Security Save Exit BIOS Information BIOS Vendor American Megatrends Core Version 4 6 3 5 Project Version xvb6_413 x64 Build Date 02 08 2010 13 21 00 UnCore Information IGD VBIOS Version 1973 GMCH Version...

Page 92: ...xit menu select Load Failsafe Defaults and reboot the system If the system failure prevents access to the BIOS firmware screens refer to Section 1 7 1 Clear CMOS RTC Password on page 31 for instructions on clearing the CMOS Table B 3 BIOS Advanced Menu Options shown may not be available on your system Aptio Setup Utility Copyright C 2009 American Megatrends Inc Main Advanced Chipset Boot Security ...

Page 93: ...e reboot the system and access the BIOS firmware From the Exit menu select Load Failsafe Defaults and reboot the system If the system failure prevents access to the BIOS firmware screens refer to Section 1 7 1 Clear CMOS RTC Password on page 31 for instructions on clearing the CMOS Table B 4 BIOS Chipset Menu Aptio Setup Utility Copyright C 2009 American Megatrends Inc Main Advanced Chipset Boot S...

Page 94: ...e Control Panel The Gigabit Ethernet boot from LAN BIOS firmware defaults to Disabled in the BIOS firmware Setup Utility The Chipset menu of the BIOS firmware Setup Utility allows the boot from LAN BIOS firmware to be Enabled or Disabled Table B 4 on page 93 shows the Chipset Menu Use the arrow keys to highlight the Onboard Device Configuration Select ʹGigE Option ROMʹ in the submenu s list and en...

Page 95: ...ether to use Quick Boot or not Table B 5 BIOS Boot Menu Aptio Setup Utility Copyright C 2009 American Megatrends Inc Main Advanced Chipset Boot Security Save Exit Boot Configuration UEFI Boot Disabled Setup Prompt Timeout 2 Bootup NumLock State On CSM16 Module Version 07 60 GateA20 Active Upon Request Option ROM Messages Force BIOS Interrupt 19 Capture Disabled Boot Option Priorities Delete Boot O...

Page 96: ... 31 for instructions on clearing the CMOS Aptio Setup Utility Copyright C 2009 American Megatrends Inc Main Advanced Chipset Boot Security Save Exit Password Description If ONLY the Administrator s password is set then this only limits access to Setup and is only asked for when entering Setup If ONLY the User s password is set then this is a power on password and must be entered to boot or enter S...

Page 97: ...Select Load Failsafe Defaults and continue the reboot Aptio Setup Utility Copyright C 2009 American Megatrends Inc Main Advanced Chipset Boot Security Save Exit Save Changes and Exit Discard Changes and Exit Save Changes and Reset Discard Changes and Reset Save Options Save Changes Discard Changes Restore Defaults Save as User Defaults Restore User Defaults Boot Override Launch EFI Shell from file...

Page 98: ... thermal relief solution is required to support the operating temperature ranges listed in Table C 1 above over silicon with Tjmax ratings of 100 C C 3 Reliability Requirements The SBC622 assembly has obtained CE mark The SBC622 is fully compliant with the European Union RoHS and WEEE directives Level 1 Level 2 Level 4 Level 5 Cooling Method Convection Convection Conduction Conduction Conformal Co...

Page 99: ...ARE PROVIDED AS IS WITH NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ALL OTHER LIABILITY ARISING FROM RELIANCE UPON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED GE Intelligent Platforms Information Centers Americas 1 800 322 3616 or 1 256 880 0444 Asia Pacifi...

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