CPLD Control and Status Registers 51
The
control
and
status
registers
exist
for
controlling
or
reading
the
status
of
the
hardware.
The
addresses
are
as
seen
by
the
processor.
In
the
following
register
descriptions,
the
bit
significance
is
shown
in
little
‐
endian
mode
(i.e.
from
the
viewpoint
of
the
processor).
MSB
=
D7,
LSB
=
D0
3.2.1 Board ID Register (0x600)
This
reads
back
0x56,
the
number
assigned
to
the
SBC622.
3.2.2 Board Revision Register (0x601)
This
provides
information
on
the
build
state
of
the
SBC622.
3.2.3 Board Configuration Register 1 (0x602)
This
register
is
not
implemented
on
the
SBC622.
3.2.4 Board Configuration Register 2 (0x603)
The
SBC622
only
implements
bit
0
of
this
register.
Table 3-2 Board Revision Register (0x601)
Bits Meaning
D7 to D5
Number revision (artwork level) of the hardware build state:
1 = Revision 1
2 = Revision 2
3 = Revision 3
4 = Revision 4
Letter revision of the hardware build state:
0x0 = Revision A
0x1 = Revision B
D4 to D0
0x18 = Revision Y
0x19 = Revision YA
0x1F = Revision YG
Table 3-3 Board Configuration Register 2 (0x603)
Bit Meaning
D7
PMC READY
1 = Not ready
0 = Ready
D6
RESERVED. Reads '0'
D5
RESERVED. Reads '0'
D4 Reserved.
Reads
'0'
D3
RESERVED. Reads '0'
D2
DBA~ (unused signal that comes from the Test connector)
1 = Not active
0 = Active
D1
RESERVED. Reads '0'
D0
VPX System Controller
1 = SBC622 is System Controller
0 = SBC622 is not System Controller
Summary of Contents for OpenVPX VPXcel6 SBC622
Page 2: ...Document History Hardware Reference Document Number 500 9300527818 000 Rev B March 18 2011 ...
Page 33: ...Installation and Setup 33 Figure 1 3 PMC Installed onto 2 PMC Site Model F ...
Page 37: ...Installation and Setup 37 Figure 1 5 Front Panel SBC622 Isometric View Convection cooled F F ...
