GE OpenVPX VPXcel6 SBC622, Hardware Reference Manual

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CPLD Control and Status Registers 53
3.2.6 VPX Geographical Address (GA) (0x605)
This register is not implemented on the SBC622.
3.2.7 Board Status Register 1 (Alarm Status Register) (0x606)
The SBC622 only implements bit D7 of this register.
3.2.8 Board Status Register 2 (0x607)
This register is not implemented on the SBC622.
3.2.9 Board ID (Word, 0x608)
This word reads back 0x7818.
3.2.10 Board Feature Set (Word, 0x60A)
This word reads back 0x0444.
3.2.11 Watchdog Keepalive Register (0x60D)
When enabled, the Watchdog Timer is prevented from resetting the system by
writing to the WDT Keepalive Register (WKPA) located at offset 0x0D within the
selected timeout period. The data written to this location is irrelevant.
3.2.12 Watchdog Timer CSR (WCSR, Word, 0x60E)
The SBC622 provides a programmable Watchdog Timer (WDT) which can be
used to reset the system if software integrity fails.
The WDT is controlled and monitored by the WDT Control Status Register
(WCSR) which is located at offset 0x0E from base I/O address 0x600.
Table 3-5 Board Status Register 1 (Alarm Status Register) (0x606)
Bit Meaning
D7 PEX8624 Fatal Error, GPI5 input
1 = Fatal error
0 = No error
D6 CPU too Hot (direct from CPU), GPI5 input
1 = Alarm
0 = No alarm
D5 Temperature Alarm (ADT7481 THERM output), GPI5 input
1 = Alarm
0 = No alarm
D4 Thermal Alarm (ADT7481 ALERT/THERM2 output), GPI5 input
1 = Alarm
0 = No alarm
D3 Reserved. Reads '0'
D2 RESERVED. Reads '0'
D1 RESERVED. Reads '0'
D0 RESERVED. Reads '0'