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5.3.2.2 Memory Circuit Control
Figure 5.3.7 is a memory circuit control block diagram.
MB90706
Figure 5.3.7 Memory control block diagram
The MB90706 has the DRAM control and chip select address decoder circuits for memory control as shown in
Figure 5.3.7
[DRAM control]
The DRAM control outputs DRAM control signals RAS and CAS to control DRAM data reading and writing and
refresh DRAM.
[Chip select address decoder]
The chip select address decoder decodes addresses and outputs a chip enable signal to ROM.
The memory circuit consists of four types of elements, DRAM, PROGRAM ROM, and EEPROM as shown in
Figure 5.3.7.
[DRAM]
The MB90706 has a “256K x 16 bits” DRAM for control program work areas, line buffers, and external character
storage areas.
External bus
DRAM control
Chip select address
decoder
I/O port
RAS,CAS,
CS0
DRAM
256k×16 Bit
Max. 1M Bytes
PROGRAMROM
1M×16 Bit
Max. 4M Bytes
Defined space capacity
EEPROM
16K Bits
Summary of Contents for Impact 3650
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