Section 4 High-speed Counter
4-4
To express a negative numeric value by two’s complement, individual bit of the numeric part is reversed and then 1 (one)
is added.
The following types of counting are available:
(1) Two-phase double multiplication
This mode counts at the leading and trailing edges of B-phase (PB pin) pulses. Two is counted per cycle.
The timing of incremental or decremental counting is as follows:
<Timing of incremental counting>
At the leading edge of B-phase pulse while A-phase is “H”
At the trailing edge of B-phase pulse while A-phase is “L”
<Timing of decremental counting>
At the leading edge of B-phase pulse while A-phase is “L”
At the trailing edge of B-phase pulse while A-phase is “H”
4-1-4 Operation modes of high-speed counter
The pulses that are input through the encoder input (PA and PB) are counted up or down.
Signed 32-bit data (expressed by two’s complement) is used in the high-speed counter, and the current counter value is
stored in %MD10.276.
4-1 High-speed Counter Specifications
%MD10.276
2,147,483,647
2,147,483,646
1
0
–1
–2
–2,147,483,647
–2,147,483,648
Current counter value
(%MD10.276)
A-phase
(PA)
B-phase
(PB)
4
3
2
1
0
0
1
2
3
