Section 4 High-speed Counter
4-2
4-1 High-speed Counter Specifications
4-1-2 Pin layout of encoder input
1
2
3
4
5
6
Pin No.
Signal name Specification
1
PO
Power input (+12V DC or +15V DC)
2
PA
A-phase input
3
PB
B-phase input
4
CM
Common for PA and PB
5
PZ
Not used
6
NC
Not connected
4-1-3 List of system memory for high-speed counter
(1) High-speed counter control %MW10.272
Note: The high-speed counter function has the function to latch the match interrupt signal that occurs while match interrupt is
disabled.
(2) High-speed counter status %MW10.274
Address
Name
Description
%MX10.272.0
Count control
Sets the counting operation of high-speed counter.
ON: Stop counting, OFF: Enable counting
%MX10.272.1
Current value reset
Resets the current value of high-speed counter.
%MX10.272.2
Match interrupt enable
Sets Enable / Disable of match interrupt for high-speed counter.
ON: Enable, OFF: Disable
%MX10.272.3
Match occurrence clear
Clears the match occurrence status of high-speed counter. When this flag is set
ON, a request to clear is issued. When the clearing is completed, this flag is set
OFF by the system.
%MX10.272.4
Match interrupt latch reset
Resets the match interrupt latched while interrupt was disabled for high-speed
counter. (Note)
%MX10.272.5
Not used
%MX10.272.6
Comparison value set
Sets the comparison value of high-speed counter. When this flag is set ON, a
request to set is issued. When the setting is competed, this flag is set OFF by
the system.
%MX10.272.7
Current value preset
Presets the current value of high-speed counter. When this flag is set ON, a
request to preset is issued. When the presetting is competed, this flag is set OFF
by the system.
%MX10.272.8
|
%MX10.272.15
Not used
Address
Name
Description
%MX10.274.0
Match occurrence
This flag is set ON when the set value of high-speed counter coincides with its
current value. This flag is cleared when the match occurrence clear flag
(%MW10.272.3) is set ON.
%MX10.274.1
|
%MX10.274.15
Not used
