Fluke 9100 Series Service Manual Download Page 17

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2/Theory of Operation

2-5

INPUT SECTION THEORY OF OPERATION

NOTE

All of the input section circuitry is located on the

Main PCA unless otherwise indicated.

Mainframe to Bus Interface Functional Block

The bus interface block connects the 9100A/9105A mainframe

microprocessor bus to the Vector Output I/O Module. The module is a

memory-mapped device, with all control performed by writing to the

module memory space. The control bus enters the module on connector J1

and consists of the following lines:

o Seven address lines, A1 through A7.

o Eight data lines, D0 through D7.

o Two differential strobe lines, and STROBE-.

o One control line, R/W-.

The two mainframe strobe signals, and STROBE-, are translated by

U9 into the module STROBE- signal. STROBE- is the key signal that

qualifies all of the bus activities and is used by U7 to latch the

addresses and R/W-, and to enable the data bus buffer. The STROBE-

signal, in conjunction with the latched version of the R/W-, generates

the read strobe (RD-) and the write strobe (WR-). The STROBE- signal and

the decoder U6 provide address decoding by generating signals AD8-

through ADE- and ALLCHIP-. Signals AD8- through ADC- and ALLCHIP- are

input to AND Gates U3 and U5 to provide the custom chip selects CS0-

through CS4-. Signals ADD- and ADE- are used as register select lines.

(The mainframe STROBE- signal has already had some amount of address

decoding. STROBE- for any particular module is only active on accesses

to addresses $DXXXX, with address bit 0 = 1, and with the proper “hot

bit” identifying the module. See the heading, “Mainframe Addressing of

the Module”, further on in this section for more information on hot-bit

decoding).

MAINFRAME ADDRESSING OF THE MODULE

Memory reserved for module control occupies the mainframe addresses

$D0000 through $DFFFF. Out of this 64K-byte block, four modules can be

addressed. Lower Data Strobe (LDS-) on the mainframe qualifies all

module addresses; thus address bit 0 is effectively a 1. Addresses

within this space using Upper Data Strobe (UDS-) are unused. Figure 2-3

shows a summary of module input section address decoding. Figure 2-4

provides an addressing example.

Each of the four modules is controlled via “hot-bit decoding” of the

mainframe address lines A8 through A11. This method of decoding allows

any combination of modules to be addressed simultaneously. Figure 2-5

Summary of Contents for 9100 Series

Page 2: ...btain warranty service contact a Fluke Service Center or send the product with the description of the difficulty postage prepaid to the nearest Fluke Service Center Fluke assumes no risk for damage in transit Fluke will at our option repair or replace the defective product free of charge However if we determine that the failure was caused by misuse alteration or abnormal condition of operation or ...

Page 3: ...RRUPTS 2 13 DATA COMPARE EQUAL OUTPUT PIN 2 13 OPERATION OF GENERAL CONTROL LATCH BLOCK 2 13 Connector Code Functional Block 2 16 Input Protection Functional Block 2 16 OUTPUT SECTION THEORY OF OPERATION 2 16 Main PCA to Top PCA Interface Functional Block 2 17 ADDRESSING 2 18 Internal Oscillator Control Functional Block 2 20 Output Control Functional Block 2 20 RAM Select Functional Block 2 21 CHI...

Page 4: ... VECTOR OUTPUT I O MODULE FUSE 3 1 CLEANING 3 2 VECTOR OUTPUT I O MODULE SELF TEST 3 2 DISASSEMBLY 3 2 TROUBLESHOOTING 3 3 General Information 3 3 4 List of Replaceable Parts 4 1 INTRODUCTION 4 3 HOW TO OBTAIN PARTS 4 3 ADDITIONAL INFORMATION 4 4 5 Schematic Diagrams 5 1 ...

Page 5: ... 2 15 2 4 Dip Clip and Calibration Module Configuration Codes 2 17 2 5 Connector Code Examples 2 18 2 6 Vector I O Module Output Section Address Map 2 19 2 7 U25 Drive Register 2 Bit Description Write D0X21 2 20 2 8 U5 Register Bit Description Write D0X01 2 21 2 9 U6 Register Bit Description Write D0X11 2 23 2 10 U25 ID Status Register Bit Description Read D0X01 2 29 4 1 9100A 017 Vector I O Final...

Page 6: ... iv ...

Page 7: ...2 Output Section Functional Block Diagram 2 4 2 3 Input Section Address Decoding Summary 2 7 2 4 Address Decoding Example 2 8 2 5 Hot Bit Decoding Examples 2 9 2 6 Bus Interface Timing Diagram 2 10 2 7 I O Module Control and Interrupt Registers 2 14 2 8 Custom Chip Voltage Level Detection 2 15 4 1 9100A 017 Final Assembly 4 6 4 2 A1 Main PCA 4 9 4 3 A2 Top PCA 4 11 ...

Page 8: ... vi ...

Page 9: ... Vector Output I O Module Specifications ______________________________________________________________________________ VECTOR OUTPUT I O MODULE OUTPUT into 10 LSTTL loads with card edge connector attached Module Vector Size 8192 vectors 40 channels wide Maximum Vector Pattern 4 Modules 8192 vectors 160 channels wide Vector Looping Up to 65536 repetitions of one vector set Output Logic Levels High...

Page 10: ...fter the programmed edge of DR CLK for the vector to be output by that clock otherwise that vector is only driven internally and the output is held tri stated effectively skipping that vector Output Series Termination 33 Ohms Capture Clock INT CLK Capture Clock clocks 42 5 ns 5 ns after the falling edge of INT CLK DR CLK Capture Clock clocks 55 ns 10 ns after non clocking edge of DR CLK approximat...

Page 11: ...Output Protection 10V 5V for one minute maximum one line only all lines Input Thresholds ________________________________________________ TTL CMOS _________ __________ ___________________________ 5 0V 5 0V Guaranteed HIGH 2 6V 3 4V HIGH or INVALID 2 1V 2 9V Guaranteed INVALID 1 0V 1 2V LOW or INVALID 0 6V 0 8V Guaranteed LOW 0 0V 0 0V _________ __________ ___________________________ CLOCK START ST...

Page 12: ...Enable Clock 50 ns Start Edge Setup Time before clock edge for clock to be recognized 0 ns minimum Stop Edge Setup Time before clock edge for clock edge to not be recognized 5 ns minimum Enable Setup Time before clock edge for clock edge to be recognized 0 ns minimum Enable Hold Time after clock edge for clock edge to be recognized 10 ns minimum Data Timing for Asynchronous Measurements Maximum Fr...

Page 13: ...ock generated during vector driving The module also has a programmable breakpoint capability The input thresholds may be set to either TTL and CMOS levels The Vector Output I O Module can drive vector patterns synchronized to a user supplied external clock at up to 25 MHz to a user selectable internal clock at 1 5 10 or 20 MHz to a software strobe or to the Pod The output can be latched to a level...

Page 14: ...al Block o Custom Chip Functional Block o Clock and Enable Mux Functional Block o General Control Latch Functional Block o Connector Code Functional Block o Input Protection Functional Block The output section consists of the following twelve functional blocks See Figure 2 2 o Main PCA to Top PCA Interface Functional Block o Internal Oscillator Control Functional Block o Output Control Functional ...

Page 15: ...2 Theory of Operation 2 3 Figure 2 1 Input Section Functional Block Diagram ...

Page 16: ...2 Theory of Operation 2 4 Figure 2 2 Output Section Functional Block Diagram ...

Page 17: ...address decoding by generating signals AD8 through ADE and ALLCHIP Signals AD8 through ADC and ALLCHIP are input to AND Gates U3 and U5 to provide the custom chip selects CS0 through CS4 Signals ADD and ADE are used as register select lines The mainframe STROBE signal has already had some amount of address decoding STROBE for any particular module is only active on accesses to addresses DXXXX with...

Page 18: ...CSX to go active Data bus transceiver U8 turns on receiving data from the mainframe to the module Addresses and R W are guaranteed valid H STROBE WR and CSX return high Write data is latched into the module registers I End of the write cycle CUSTOM CHIP SELECTION The Bus Interface also decodes address lines A1 through A7 from the mainframe to determine which custom chips are enabled As the address...

Page 19: ...2 Theory of Operation 2 7 Figure 2 3 Input Section Address Decoding Summary ...

Page 20: ... A7 determine the custom chip selection To address all chips an address in the form DXXFX must be used X means don t care This address causes the ALLCHIP signal U6 7 to go active which when gated through U5 and U3 makes all five chip selects CS0 through CS4 active Custom Chip Functional Block The custom chips each contain eight channels of data acquisition Each channel performs 16 bit Cyclic Redun...

Page 21: ...ources for the XEN signal CLOCK AND ENABLE MUX OPERATION Inputs The Clock and Enable Mux block clock sources include BUFCLOCK CAPTURE and CALCLK2 BUFCLOCK originates from the CLOCK external synchronization line CAPTURE is a user programmable clock generated on the Top PCA by the output section during vector driving CAPTURE is routed to the Main PCA through J4 29 where it is inverted by U19 and sen...

Page 22: ...signal enters the Main PCA through the Connector Code block Channels 1 through 39 are tied together and to CALCLK2 when the Calibration Module is plugged in CALCLK2 is an input to U18 13 The ENMUX and CLKMUX signals are generated by the Control Register U14 15 and U14 16 respectively and are control inputs to U18 U18 generates outputs XEN and XCK Table 2 2 shows which signals appear on the outputs...

Page 23: ...hold Reference Voltage for Inputs CD0 CD7 VHI Input Logic High Threshold Reference Voltage for Inputs CD0 CD7 CD0 CD7 Input Channel Inputs TLI Input Test Channel Comparator Input TLO Output Test Channel Comparator Output ______________________________________________________________________________ CDn inputs have an internal resistor network to control the voltage at which they will float the inv...

Page 24: ...l Register U14 is cleared by a PWRUP Power Up signal held low by C44 to ensure a proper reset See Figure 2 7 for the Control Register bit position The J2 and J3 connectors provide the input to the General Control Latch block for detection of Clip and Calibration Modules J2 25 and J3 25 are the input pins to a detection circuit that provides SWLDET the left hand or A Switch Detect and SWRDET the ri...

Page 25: ... to form a DCE signal The DCE signal triggers a J K flip flop to produce the DCEDET and DCEINT signals The I O General Interrupt IOGENINT is an interrupt generated by the module when either pushbutton on a clip module is pressed The interrupt register on the module must be read to determine the cause In the case of a button push two J K flip flops output the SWLDET A side and SWRDET B side signals...

Page 26: ...odule Control and Interrupt Registers The threshold THRSH signal output of U14 19 controls the circuitry that produces a low voltage level VLO and a high voltage level VHI These voltage levels are used by the custom chip pins 39 and 45 to define the logic low invalid and logic high voltage ranges A logic high out U14 19 designates a TTL logic level and a logic low a CMOS logic level The THRSH sign...

Page 27: ... the custom chip uses data inputs VHI and VLO voltage levels to detect a high voltage input a low voltage input or a tri state condition See Figure 2 8 for an illustration of the detection circuitry contained in the custom chip NOTE The actual input thresholds for the high and low comparators are computed from the formulas shown in Figure 2 8 Figure 2 8 Custom Chip Voltage Level Detection Multi De...

Page 28: ... encoded in each Clip Module To read the code the mainframe performs a read at DXXE1 This operation generates the ADE signal which in turn enables U16 placing the code on the data bus Of the eight bits read the lower four bits refer to the A side and the upper four bits refer to the B side Thus differentiation is possible for 16 different conditions on each side of the module Clips that use up an ...

Page 29: ...________ 8 BIT CODE MEANING 7654 3210 ______________________________________________________________________________ 1110 0000 28 Pin Clip 1110 0001 40 Pin Clip 1110 0010 Calibration Header 0110 0010 Calibration Header 1110 0011 reserved 1110 0100 reserved 1110 0101 reserved 1110 0110 reserved 1110 0111 reserved 1110 1000 reserved 1110 1001 reserved 1110 1010 reserved 1110 1011 reserved 1110 1100 ...

Page 30: ...low the data passes in the other direction for a write Some register control signals such as COMMAND0 and COMMAND1 for U5 and U6 of the Top PCA use the rising edge of WR to latch data Since the WR signal also controls the direction of the TOPDATA bus through U24 U29 provides a nominal 46 5 ns delay to the direction control signal WR DLY on U24 This insures that during accesses to the output sectio...

Page 31: ...2 7 for more information Performing a write to DOX31 toggles either LCLO or LCHI of U25 Main PCA depending on the state of bit 3 of Drive Register 2 on U25 thereby loading the least significant byte LSB or most significant byte MSB of the loop count into U26 or U27 Performing a read at this address has no effect See the heading Loop Control Functional Block and Table 2 7 for more information Perfo...

Page 32: ...SLOGIC Functional Block as one vector driving clock source The Y output from U22 pin 6 is inverted by U19 This inversion gives OSC CLK the same phase as the INT OSC output and delays it slightly to reduce the clock to vector out skew before being routed to the P1 pin 5 INT OSC output Table 2 7 U25 Drive Register 2 Bit Description Write D0X21 ________________________________________________________...

Page 33: ...s the START ENA so that both input and output sections can be started simultaneously To clear START ENA the CO START line must be set low and a WRITE D0X11 must be performed with bit 0 set to 0 Table 2 8 U5 Register Bit Description Write D0X01 ___________________________________________________________________________ BIT SIGNAL 1 0 _________________________________________________________________...

Page 34: ...elects static RAM chip U100 A write to RAM PORT causes the selected RAM to load the data on the bus and advances the chip counter U9 output to 6 causing U11 output BYTE1 to select U102 This operation is repeated until the counter reaches 15 at which point the U10 PAL output BYTE10 selects the Control RAM U600 Upon performing a write to RAM PORT the Control RAM is loaded with the data and the RC0 o...

Page 35: ...___________________ BIT SIGNAL 1 0 ___________________________________________________________________________ 7 CLK POL Falling Edge Rising Edge 6 ENA POL Enable High Enabie Low 5 STOP POL Falling Edge Rising Edge 4 START POL Falling Edge Rising Edge 3 ENA ALWAYS Enable Always No Enable Always 2 FOR START No Forcestart Forcestart 1 STOP ENA No Stop Enabled Stop Enabled 0 Unused __________________...

Page 36: ...A The handshake synchronization circuit consists of a 74ACT74 Dual D Type Flip Flop U8 a 74AC20 Quad Input NAND Gate U12 and a 74ACT86 Exclusive OR Gate U17 all on the Top PCA Prior to vector driving the START ENA line is set low This signal is gated by U12 and U17 and is routed to U8 10 which initializes the HS ENABLE line from U8 9 high HS ENABLE permits SSGATE to be low upon receipt of a start ...

Page 37: ...ors being driven a STOP statement may be placed after an ENDLOOP statement in the vector file The LOOP DONE signal is normally low This signal remains low until the final pass through the loop has begun As long as LOOP DONE is low the output of U16 9 is also low preventing the BOTH signal from passing through U19 The LOOP signal is active one vector before the end of the loop to permit address loa...

Page 38: ...OAD RAM OUT signal This signal commands U1 and U2 to reload the LOOP BACK ADDRESS from which the vector driving resumes Vector Pattern RAM Functional Block There are ten identical Vector Pattern RAM Functional Blocks that provide the forty output channels on the Vector Output I O Module Each RAM block consists of an 8K x 8 SRAM a 74AC273 Octal D Type Flip Flop a resistor pack and one 74HC126 Tri S...

Page 39: ... the WAIT input o LOOP decrements the loop counter and checks the results after reaching one vector prior to the ENDLOOP statement o BOTH loops until the loop count is exhausted and then terminates vector driving o CAP CLK clocks the input section in the center of the current vector period When the TP5 TST test point is pulled low for testing purposes the output of U601 is disabled forced low This...

Page 40: ...p PCA SSLOGIC Functional Block for terminating vector driving if the BOTH bit of the Vector Control RAM is set Capture Clock Functional Block When a vector file is driven with the Capture clock programmed to occur the CAP CLK output at U601 2 goes high for the entire vector period CAP CLK is inverted by U20 and is then ANDed with the RAMCLK signal and output from U20 3 The ANDing of the two signal...

Page 41: ...1 0 ID CODE 01 ___________________________________________________________________________ Output Protection Functional Block The vector data on the OUT BUS of the Top PCA is connected to diode packs BAV99 that are connected to 5 volts and ground to clamp overvoltage and undervoltage on the outputs The output connectors J1 and J2 have 33 ohm resistors in series with the output that provide high sp...

Page 42: ...2 Theory of Operation 2 30 ...

Page 43: ...m 3 Using the procedures and packaging and bench techniques that are recommended The Static Sensitive S S devices are identified in the Fluke technical manual parts list with the symbol The following practices should be followed to minimize damage to S S devices 1 MINIMIZE HANDLING 2 KEEP PARTS IN ORIGINAL CONTAINERS UNTIL READY FOR USE 3 DISCHARGE PERSONAL STATIC BEFORE HANDLING DEVICES USE A HIG...

Page 44: ...PEN EDGE CONNECTOR EXCEPT AT STATIC FREE WORK STATION PLACING SHORTING STRIPS ON EDGE CONNECTOR HELPS TO PROTECT INSTALLED SS DEVICES 9 HANDLE S S DEVICES ONLY AT A STATIC FREE WORK STATION 10 ONLY ANTI STATIC TYPE SOLDER SUCKERS SHOULD BE USED 11 ONLY GROUNDED TIP SOLDERING IRONS SHOULD BE USED A complete line of static shielding bags and acces sories is available from Fluke Parts Department Tele...

Page 45: ...t the Vector Output I O Module fuse has opened This problem can occur when the I O Module COMMON lead is incorrectly connected to the UUT Prior to replacing the fuse determine the incorrect COMMON lead connection Then disconnect all I O Module leads and replace the fuse as follows 1 Locate the fuse holder on the back of the I O Module near the cable 2 Press the fuse holder cap in then rotate it co...

Page 46: ... left most field using the left arrow key 2 Press the SELFTEST softkey F1 3 Move the cursor one field to the right and press the I O MOD softkey F3 4 Move the cursor one more field to the right and press the number of the I O Module to be tested Check that the display reads MAIN SELFTEST I O MOD n where n signifies the number of the I O Module 5 Press ENTER to initiate the self test If the self te...

Page 47: ...ving out vectors check the following few key signals on the Top PCA 9100A 4022 on the affected channel s while the self test is being performed o Verify the non assertion of the external TRISTATE signal on pin 1 of the 74AC273 D Type Flip Flops U101 U103 of the Pattern RAM Functional Block o Verify the activity of the LAT CLK signal on pin 11 of the 74AC273 D Type Flip Flops U101 U103 of the Patte...

Page 48: ...3 Maintenance 3 4 U502 on the Top PCA has four channels of output By observing the failure mask and using the single point probe for verification the faulty PCA Top or Main can be isolated ...

Page 49: ...__________________________________________________________ TABLE OF CONTENTS TABLE FIGURE ASSEMBLY NAME DRAWING NO NO PAGE NO PAGE 9100A 017 Final Assembly 9100A 017 4 1 4 5 4 1 4 6 A1 Main PCA 9100A 4021 4 2 4 8 4 2 4 9 A2 Top PCA 9100A 4022 4 3 4 10 4 3 4 11 ...

Page 50: ...4 List of Replaceable Parts 4 2 ...

Page 51: ...John Fluke Manufacturing Co Inc or an authorized representative by using the Fluke Stock Number In the event the part ordered has been replaced by an new or improved part the replacement will be accompanied by an explanatory note and installation instructions if necessary To ensure prompt and efficient handling of your order please include the following information o Quantity o Fluke Stock Number ...

Page 52: ...he PCAs documented in this manual To identify the configuration of the PCAs used in your instrument refer to the revision letter on the component side of each PCA This section also contains a list of Manufacturer s Federal Supply Codes and a list of U S and international Technical Service Centers ...

Page 53: ...1310 89536 111310 2 MP 1 FOOT NON SKID 774000 89536 774000 4 MP 2 CASE TOP I O MODULE 773291 89536 773291 1 MP 3 CASE BOTTOM I O MODULE 773283 89536 773283 1 MP 4 DECAL VECTOR OUTPUT I O TOP 855387 89536 855387 1 MP 5 DECAL VECTOR OUTPUT I O BOTTOM 855390 89536 855390 1 MP 6 DECAL VECTOR OUTPUT I O SIDE 855395 89536 855395 1 MP 7 NAMEPLATE SERIAL REAR PANEL 472795 89536 472795 1 TM 1 VECTOR OUTPUT...

Page 54: ...4 List of Replaceable Parts 4 6 Figure 4 1 9100A 017 Final Assembly ...

Page 55: ...4 List of Replaceable Parts 4 7 Figure 4 1 9100A 017 Final Assembly cont ...

Page 56: ...M 200PPM 1206 745992 59124 RM73B 2BJ102KB 7 R 33 34 39 745992 R 40 745992 R 35 RES CERM 33 5 125W 200PPM 1206 746248 09969 CRCW 1206 330 J BOZ 1 TP 6 8 TERM UNINSUL WIRE FORM TEST POINT 781237 27918 TP102 01 3 U 1 OSCILLATOR 1MHZ TTL CLOCK 634113 91637 XO 43B 1 1 U 2 IC OP AMP QUAD LOW POWER SOIC 742569 18324 LM324D 1 U 3 5 IC CMOS QUAD 2 INPUT AND GATE SOIC 853317 18324 74HC08D 2 U 4 IC CMOS HEX ...

Page 57: ...4 List of Replaceable Parts 4 9 Figure 4 2 A1 Main PCA ...

Page 58: ...02 01 5 U 1 2 IC FTTL 8 BIT CNTR SOIC 852095 18324 74F269D 2 U 3 6 IC CMOS OCTAL D F F EDG TRG SOIC 838029 18324 74HC273DT 4 U 7 19 IC CMOS QUAD 2 INPUT AND GATE SOIC 838227 54590 CD74AC08M 2 U 8 13 16 IC CMOS DUAL D F F EDG TRG SOIC 837930 54590 CD74ACT74M 3 U 9 IC CMOS SYNC DIV BY 16 BIN CNTR SOIC 852066 18324 74HC163D 1 U 10 PROGRAMMED 22V10 TOP U10 855429 89536 855429 1 U 11 PROGRAMMED 22V10 T...

Page 59: ...4 List of Replaceable Parts 4 11 Figure 4 3 A2 Top PCA ...

Page 60: ...____________________________________________________ Ref Assembly Fluke Revision Name Part No Level ______________________________________________________________________________ A1 Main PCA 873948 C A2 Top PCA 873950 C ______________________________________________________________________________ ...

Page 61: ...Amatom El Mont California 04713 Motorola Inc semiconductor Group Phoenix Arizona 34114 Oak Industries Rancho Bernardo CA 61752 IR ONICS Inc Warwick Rhode Island 91637 Dale Electronics Inc Columbus Nebraska 09969 Dale Electronics Inc Yankton South Dakota 50541 Hypertronics Corp Hudson Massachusetts 61935 Schurter Inc Petalum California 12040 National Semiconductor Corp Danbury Connecticut 51406 Mur...

Page 62: ...S Technical Service I E Strandlodsveij 1A PO Box 1919 DK 2300 Copenhagen S Tel 45 1 572222 Ecuador Proteco Coasin Cia Ltda P O Box 228 A Ave 12 de Octubre 2285 y Orellana Quito Tel 593 2 529684 Egypt Philips Egypt 10 Abdel Rahman el Rafei st el Mohandessin P O Box 242 Dokki Cairo Tel 20 2 490922 England Philips Scientific Test Measuring Division Colonial Way Watford Hertforshire WD2 4TT Tel 44 923...

Page 63: ...Main Rd Martindale Johannesburg 2092 Tel 27 11 470 5255 Spain Philips Iberica Sae Depto Tecnico Instrumentacion c Martinez Villergas 2 28027 Madrid Tel 34 1 4042200 Sweden Philips Kistaindustrier Ab I E Technical Customer Support Borgarfjordsgatan 16 S 164 93 Kista Tel 46 8 703 1000 Switzerland Philips A G Technischer Kundendienst Postfach 670 Allmendstrasse 140 CH 8027 Zurich Tel 41 1 482211 Taiw...

Page 64: ...4 List of Replaceable Parts 4 16 ...

Page 65: ...5 1 Section 5 Schematic Diagrams ______________________________________________________________________________ CONTENTS FIGURE TITLE PAGE 5 1 A1 Main PCA 5 3 5 2 A2 Top PCA 5 5 ...

Page 66: ...5 Schematic Diagrams 5 2 ...

Page 67: ...5 Schematic Diagrams 5 3 Figure 5 1 A1 Main PCA ...

Page 68: ...5 Schematic Diagrams 5 4 Figure 5 1 A1 Main PCA cont ...

Page 69: ...5 Schematic Diagrams 5 5 Figure 5 2 A2 Top PCA ...

Page 70: ...5 Schematic Diagrams 5 6 Figure 5 2 A2 Top PCA cont ...

Page 71: ...tom Chip Functional Block 2 8 Cyclic Redundancy Checking 2 8 2 27 Data Compare Equal Output Pin 2 13 Data Compare Interrupt 2 13 Data Comparison Interrupts 2 13 Data Comparison Inputs 2 12 DCE 2 13 Dip Clip Module 2 17 Disassembling the Module 3 2 Drive Clock Selection 2 23 Drive Status Functional Block 2 28 ENDLOOP Statement 2 27 Functional Blocks Capture Clock 2 28 Clock and Enable Mux 2 8 Conne...

Page 72: ...eral 2 13 Loading Vector RAM 2 27 LOOP 2 25 2 27 Loop and Stop Performing 2 25 Loop Control Functional Block 2 27 Main PCA to Top PCA Interface Functional Block 2 17 Mainframe Addressing of the Module 2 5 Mainframe to Bus Interface Functional Block 2 5 Multi Detection and Interrupt 2 15 Operation of General Control Latch Block 2 13 Output Control Functional Block 2 20 Output Protection Functional ...

Page 73: ...ting the Module 3 3 Vector Address Functional Block 2 26 Vector Control RAM 2 22 2 26 Vector Drive Complete Logic 2 25 Vector Drive Status Nybble 2 18 2 24 Vector Drive Termination 2 27 Vector Output I O Module Overview 2 1 Vector Pattern RAM 2 22 2 26 Vector RAM Address Register 2 23 VHI and VLO 2 14 WAIT 2 24 2 27 ...

Page 74: ...Index Index 4 ...

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