TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
12
4.0 HARDWARE DESIGN CONSIDERATIONS
Figures 4 and 6 each presents a schematic design of the XRT71D00 device being
interfaced to the XRT73L00 device. In these schematics, both the XRT73L00 and the
XRT71D00 devices have been configured to operate in the “Host” Mode. In the case of
Figure 4, the XRT71D00 device has been designed to operate in the Receive Path.
Additionally, in the case of Figure 6, the XRT71D00 device has been designed to operate
in the Transmit Path.
There are numerous other things to note about Figures 4 and 6.
1. The XRT71D00 and the XRT73L00 devices are each connected to the following
signals.
a. HW_RESET*
This signal is tied to the “RST*” input pin of the XRT71D00 device and the
“REG_RESET*” input pin of the XRT73L00 device. Therefore, pulsing the
“HW_RESET*” input signal “low” will command a “Hardware RESET” to both the
Jitter Attenuator and the LIU IC.
b. JA_LIU_CS*
This signal is tied to the CS* (Chip-Select) input pins of both the XRT71D00 and the
XRT73L00 devices. Therefore, pulsing the “JA_LIU_CS*” input signal “low”
asserts Chip Select for both of these devices, simultaneously.
c. JA_LIU_SCLK_IN
This input signal is tied to the “SCLK” input pins of both the XRT71D00 and the
XRT73L00 devices. Hence, applying a clock signal to this input signal permits the
clock signal to be applied to the “SCLK” input pins of both devices, simultaneously.
d. JA_LIU_SDI_IN
This input signal is tied to the “SDI” input pins of both the XRT71D00 and the
XRT73L00 devices. Hence, applying data (via this signal) permits this signal to be
applied to the “SDI” input pins of both devices, simultaneously.
e. JA_LIU_SDO_OUT
This output signal is tied to the “SDO” output pins of both the XRT71D00 and the
XRT73L00 device. Therefore, either the “SDO” output pin of the XRT73L00 device,
or that of the XRT71D00 device can drive this output signal.
