TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
46
apply Address and Data values to this input (in a serial manner) during READ and
WRITE operations.
Data that is applied to this input pin will be latched (into the Microprocessor Serial
Interface circuitry) upon the rising edge of the SCLK signal. A more definitive
description on how to use this particular input pin is presented below.
SDO – Serial Data Output pin
This output pin serial outputs the contents of a specified Command Register, during
READ operations. Data, which is output via this pin, is updated upon the falling edge of
the SCLK input signal.
This output pin is tri-stated during all other times.
REG_RESET or RST* - Hardware Reset Input pins
This input pin permits the user to command a “Hardware RESET” to either the
XRT73L00 or the XRT71D00 devices. In the case of the XRT73L00 and XRT71D00
device, each of the Command Registers will be reset to their default values. Each of
these devices will also begin operating in a manner that corresponds with the “default”
values of these Command Registers. Further, in the case of the XRT71D00 device, the
contents of the FIFO (within the chip) will be flushed. Additionally, the FIFO_READ
and FIFO_WRITE pointers, will be reset to their “default” positions.
