5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Install Close to the
DC-DC Converter or
Switching Regulator
NOTE: BNC Connector on
Transmit Side is sometimes
AC coupled to Chassis
GND
NOTE: External Input
Control pins should be
pulled to GND, when the
LIU is configured in
HOST Mode.
NOTE: In this Configuration,
the XRT71D00 device should
be assigned a "Channel
Address" of 00.
(3.6V)
XRT71D00_XRT73L00_HOST.sch
1.01
Schematic Design for TAN_042
B
1
1
Thursday, June 07, 2001
Title
Size
Document Number
Rev
Date:
Sheet
of
JITTERY RECOVERED CLOCK SIGNAL
SMOOTHED RECOVERED CLOCK SIGNAL
3.3V
JP2
JUMPER
1
2
R1
100
C10
0.1uF
R11
4.7K
U3
XRT71D00
31
2
3
4
5
6
7
8
10
11
14
15
18
19
20
21
22
23
26
27
28
29
30
RPOS
RNEG
RCLK
GNDD
MCLK
GNDA
VDDA
STS-1
SDI
SCLK
HOST/HW
FL
Ch_Addr_1
SDO
RST
ICT
GNDD
RRCLK
RRNEG
RRPOS
VDDD
Ch_Addr_0
CS
VDDD
C8
0.1uF
C9
0.1uF
J1
BNC
1
2
J2
BNC
1
2
R4
37.4
R5
37.4
JP1
JUMPER
1
2
T1
T3001
1
6
3
4
L1
15uH
T2
T3001
1
6
3
4
C11
1000pF
L2
6.8uH
L3
6.8uH
D1
D1N5914
U10
XRT73L00
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
41
42
43
44
20
11
39
TxLEV
TAOS
TxAVDD
DMO
TxAGND
AGND
RxAGND
RRTIP
RRING
RxAVDD
REQDIS
LOSTHR
LLB
RLB
STS-1/DS3
E3
HOST/HW
SDI
SCLK
CS
RLOL
RLOS
DGND
DVDD
EXCLK
RxDGND
RxDVDD
LCV
RCLK1
RNEG
RPOS
ICT
TxOFF
TCLK
TPDATA
TNDATA
TRING
TTIP
TxAVDD
MRING
MTIP
SDO
REG_RESET
TxAGND
C15
1000pF
R6
31.6
C14
0.1uF
C3
2.2uF
R3
475
R7
31.6
C4
2.2uF
C1
0.01uF
R8
274
C5
33uF
R9
274
R10
4.7K
R2
100
C13
0.1uF
C6
0.1uF
C7
0.1uF
C12
0.1uF
HW_RESET*
JA_LIU_CS*
JA_LIU_SCLK_IN
RxLOS
RxLOL
XMIT_FAIL
LINE_CODE_VIOL
RxPOS_De_Jittered
RxNEG_De_Jittered
RCLK_De_Jittered
44.736MHz
44.736MHz
TxPOS
TxNEG
JA_LIU_SDO_OUT
JA_LIU_SDI_IN
JA_FIFO_ALARM
TxAVDD
RxAVDD
DVDD
DVDD
RxAVDD
DVDD
DVDD
TxAVDD
RxAVDD
