TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
20
Register
Bit-Format
Addr. Command
Register
Type D6
D5 D4
D3 D2
D1
D0
0x00 CR0 R/O
Res.
Res.
RLOL RLOS ALOS DLOS
DMO
0x01 CR1 R/W
Res.
Res.
TXOFF
TAOS TXCLK
INV
0
TXLEV TXBIN
0x02 CR2 R/W
Res.
Res.
Res.
ENDECDIS
ALOSDIS
DLOSDIS
REQDIS
0x03 CR3 R/W
Res.
Res.
RNRZ
LOSMUT
RCLK2/
LCV*
RCLK2
INV
RCLK1
INV
0x04 CR4 R/W
Res.
Res.
Res. STS-1/
DS3*
E3 LLB
RLB
0x05
CR5
R/W
Res.
Res.
Res. Res. Res. Res.
Res.
0x06 CR6 R/W
STS-1
0
E3/DS3* DJA
BWS CLKES
0
FSS
0x07
CR7
R/O
Res.
Res.
Res. Res. Res. Res. FL
Figure 7, The Recommended Bit-Format of the “Composite Set” of Command
Registers (from the XRT73L00 and the XRT71D00 Device), when the XRT71D00
device is configured to operate in the “Transmit Path”.
If the above-mentioned configuration is implemented, then the XRT71D00 device will be
provided with the following set-up and hold times, for each of the three (3) data rates.
Table 3, The “TPDATA/TNDATA” to “TCLK” Set-up and Hold Times provided to
the XRT71D00 Device, when configured as presented in Figure 6.
Data Rate
TPDATA/TNDATA to TCLK
Set-up Time Provided
TCLK to TPDATA/TNDATA
Hold Time Provided
E3 9.5ns
19.5ns
DS3 6ns
16ns
STS-1 4.5ns
14.5ns
NOTES:
1. Minimum “TPDATA/TNDATA to TCLK Set-up Time” Requirements of XRT73L00
Device = 3ns.
2. Minimum “TCLK to TPDATA/TNDATA Hold-Time Requirements of the
XRT73L00 Device = 3ns.
