TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
10
Table 1, The Relationship between the Logic States of the “Ch_Addr_0” and
“Ch_Addr_1” input pins, and the “Assigned Channel”
Ch_Addr_1 Ch_Addr_0
Assigned
Channel
0 0
Channel
0
0 1
Channel
1
1 0
Channel
2
1 1
Not
Valid
If a given XRT71D00 device is assigned to “Channel 0” then it will only respond to
READ/WRITE operations to Address locations 0x06 and 0x07 (within the device). If the
Microprocessor attempts to perform write operations to address locations “0x0E” and
“0x16”, then the XRT71D00 device will ignore this particular operation. Further, if the
Microprocessor attempts to perform read operations to address locations “0x0E”, “0x0F”,
“0x16” and “0x17”, then the XRT71D00 device will simply ignore these particular
operations and will continue to tri-state its “SDO” output pin.
Similarly, if a given XRT71D00 device is assigned to “Channel 1” then it will only
respond to READ/WRITE operations to Address locations 0x0E and 0x0F (within the
device). If the Microprocessor attempts to perform write operations to address locations
“0x06” and “0x16”, then the XRT71D00 device will ignore this particular operation.
Further, if the Microprocessor attempts to perform read operations to address locations
“0x06”, “0x07”, “0x16” and “0x17”, then the XRT71D00 device will simply ignore these
particular operations and will continue to tri-state its “SDO” output pin.
This Applications Note discusses how to interface a single XRT71D00 device to the
XRT73L00 device. Therefore, the Jitter Attenuator IC (within this Applications Note)
will be assigned to “Channel 0”.
When the XRT71D00 device has been assigned to “Channel 0” and has been interfaced
with the XRT73L00 device (as shown in Figure 3); then the resulting composite
Command Register Address Map is as presented below.
