6
FUNCTIONS
54
EPSON
S1C33 FAMILY C33 PE CORE MANUAL
6
.
3
.
3
Exception Handling
When an interrupt or exception occurs, the processor starts exception handling. (This exception handling does not
apply for reset and debug exceptions.)
The exception handling performed by the processor is outlined below.
(
1
) Suspends the instruction currently being executed.
An interrupt or exception is generated synchronously with the rising edge of the system clock at the end of the
cycle of the currently executed instruction.
(
2
) Saves the contents of the PC and PSR to the stack (SP), in that order.
(
3
) Clears the IE (interrupt enable) bit in the PSR to disable maskable interrupts that would occur thereafter. If
the generated exception is a maskable interrupt, the IL (interrupt level) in the PSR is rewritten to that of the
generated interrupt.
(
4
) Reads the vector for the generated exception from the vector table, and sets it in the PC. The processor thereby
branches to the user
’
s exception handler routine.
After branching to the user
’
s exception handler routine, when the
reti
instruction is executed at the end of
exception handling, the saved data is restored from the stack in order of the PC and PSR, and the processing returns
to the suspended instruction.
6
.
3
.
4
Reset
The processor is reset by applying a low-level pulse to its #RESET pin. All bits of the PSR are thereby cleared to
0
,
and the contents of other registers become indeterminate.
The processor starts operating at the rising edge of the #RESET pulse to perform a reset sequence. In this reset
sequence, the reset vector is read out from the top of the vector table and set in the PC. The processor thereby
branches to the user
’
s initialization routine, in which it starts executing the program. The reset sequence has priority
over all other processing.
6
.
3
.
5
Address Misaligned Exception
The load instructions that access memory or I/O areas are characteristic in that the data size to be transferred is
predetermined for each instruction used, and that the accessed addresses must be aligned with the respective data-
size boundaries.
Instruction Transfer data size Address
ld.b
/
ld.ub
Byte (
8
bits)
Byte boundary (applies to all addresses)
ld.h
/
ld.uh
Halfword (
16
bits) Halfword boundary (least significant address bit =
0
)
ld.w
Word (
32
bits)
Word boundary (two least significant address bits =
00
)
If the specified address in a load instruction does not satisfy this condition, the processor assumes an address
misaligned exception and performs exception handling. In this case, the load instruction is not executed. The PC
value saved to the stack in exception handling is the address of the load instruction that caused the exception.
In the load instructions that use the SP as the base address, no address misaligned exceptions will occur, as the
addresses are aligned properly according to the data size.
Nor does this exception occur in the instructions that involve branching of the program flow (e.g.,
call
%rb
or
jp
%rb
), as the least significant bit of the PC is always fixed to
0
. The same applies to the vector for exception
handling.
