Epson S1C33 Series Core Manual Download Page 132

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DETAILS OF INSTRUCTIONS

124

EPSON

S1C33 FAMILY C33 PE CORE MANUAL

ld.w

%sd

%rs

Function

Word data transfer

Standard)

←

Extension

) Unusable

Extension

) Unusable

Code

r s

s d

0xA0__

Flag

IE C V Z N

– – – – –

is the PSR, the content of

is copied.

Mode

Src: Register direct

%rs

%r0

%r15

Dst: Register direct

%sd

%psr

%sp

%alr

%ahr

%ttbr

%pc

CLK

One cycle (three cycles when

%sd

%psr

)

Description

The content of the

Example

ld.w %sp,%r0

; sp

←

Caution

When a special register other than the destination registers listed above is specified as

%sd

, the

ld.w

instruction will be executed as a

nop

instruction.

Summary of Contents for S1C33 Series

Page 1: ...CMOS 32 BIT SINGLE CHIP MICROCOMPUTER Core Manual S1C33 Family C33 PE ...

Page 2: ...ir ing high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this mate rial will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating t...

Page 3: ... 99 Specs not fixed Specification Package D die form F QFP B BGA Model number Model name C microcomputer digital products Product classification S1 semiconductor Development tools S5U1 C 33000 H2 1 Packing specifications 00 standard packing Version 1 Version 1 Tool type Hx ICE Dx Evaluation board Ex ROM emulation board Mx Emulation memory for external ROM Tx A socket for mounting Cx Compiler packa...

Page 4: ......

Page 5: ...Register IDIR 10 2 8 Debug Base Register DBBR 10 2 9 Register Notation and Register Numbers 11 2 9 1 General Purpose Registers 11 2 9 2 Special Registers 12 3 Data Formats 13 3 1 Unsigned 8 Bit Transfer Register Register 13 3 2 Signed 8 Bit Transfer Register Register 13 3 3 Unsigned 8 Bit Transfer Memory Register 14 3 4 Signed 8 Bit Transfer Memory Register 14 3 5 8 Bit Transfer Register Memory 14...

Page 6: ...ctions 36 5 13 Push and Pop Instructions 37 5 14 Branch and Delayed Branch Instructions 39 5 14 1 Types of Branch Instructions 39 5 14 2 Delayed Branch Instructions 42 5 15 System Control Instructions 44 5 16 Swap Instructions 45 5 17 Other Instructions 46 6 Functions 47 6 1 Transition of the Processor Status 47 6 1 1 Reset State 47 6 1 2 Program Execution State 47 6 1 3 Exception Handling 47 6 1 ...

Page 7: ... sign8 jrge d sign8 84 jrgt sign8 jrgt d sign8 85 jrle sign8 jrle d sign8 86 jrlt sign8 jrlt d sign8 87 jrne sign8 jrne d sign8 88 jruge sign8 jruge d sign8 89 jrugt sign8 jrugt d sign8 90 jrule sign8 jrule d sign8 91 jrult sign8 jrult d sign8 92 ld b rd rs 93 ld b rd rb 94 ld b rd rb 95 ld b rd sp imm6 96 ld b rb rs 97 ld b rb rs 98 ld b sp imm6 rs 99 ld c rd imm4 100 ld c imm4 rs 101 ld cf 102 l...

Page 8: ...rd rs 135 or rd sign6 136 pop rd 137 popn rd 138 pops sd 139 psrclr imm5 140 psrset imm5 141 push rs 142 pushn rs 143 pushs ss 144 ret ret d 145 retd 146 reti 147 rl rd rs 148 rl rd imm5 149 rr rd rs 150 rr rd imm5 151 sbc rd rs 152 sla rd rs 153 sla rd imm5 154 sll rd rs 155 sll rd imm5 156 slp 157 sra rd rs 158 sra rd imm5 159 srl rd rs 160 srl rd imm5 161 sub rd rs 162 sub rd imm6 163 sub sp im...

Page 9: ... can be effectively utilized 1 1 Features Processor type Seiko Epson original 32 bit RISC processor 32 bit internal data processing Contains a 32 bit 16 bit multiplier Operating clock frequency DC to 66 MHz or higher depending on the processor model and process technology Instruction set Code length 16 bit fixed length Number of instructions 125 Execution cycle Main instructions executed in one cy...

Page 10: ... w sd rs Special register specifiable in sd added ld w rd ss Special register specifiable in ss added Added instructions The instructions added to the C33 PE Core are listed below For details see the description of each instruction in subsequent sections of this manual 1 Instructions specifically designed to save and restore single or special registers have been added push rs Pushes single registe...

Page 11: ... register A debug base register DBBR has been added This register indicates the start address of the debug area It normally is fixed to 0x60000 Processor status register The following flags in PSR have been removed as have the related instructions MO flag bit 7 Mac overflow flag DS flag bit 6 Divide sign 1 2 3 Address Space and Other Address space The C33 PE Core supports a 4G byte space based on ...

Page 12: ...During initialization at power on the contents of the general purpose registers are indeterminate 2 2 Program Counter PC Symbol PC Size 32 bits Initial value Indeterminate Register name Program Counter R W R The Program Counter hereinafter referred to as the PC is a 32 bit counter for holding the address of an instruction to be executed More specifically the PC value indicates the address of the n...

Page 13: ...els are masked unless the IL bit field is set to a different level or the interrupt handler routine is terminated by the reti instruction IE bit 4 Interrupt Enable This bit controls maskable external interrupts by accepting or disabling them When IE bit 1 the processor enables maskable external interrupts When IE bit 0 the processor disables maskable external interrupts When an interrupt or except...

Page 14: ...4 When a positive integer is subtracted from a negative integer the operation resulted in producing a 0 positive in the sign bit most significant bit of the result Z bit 1 Zero This bit indicates that an operation resulted in 0 More specifically this bit is set to 1 when the execution of a logical operation arithmetic operation or shift instruction resulted in 0 or is otherwise reset to 0 N bit 0 ...

Page 15: ...tack and data area from overlapping Furthermore as the SP becomes indeterminate when it is initialized upon reset last stack address 4 with 2 low order bits 0 must be written to the SP in the beginning part of the initialization routine A load instruction may be used to write this address If an interrupt or exception occurs before the stack is set up it is possible that the PC or PSR will be saved...

Page 16: ...ution of a Call Instruction A subroutine call instruction call uses one word 32 bits of the stack The call instruction pushes the content of the PC return address onto the stack before branching to a subroutine The pushed address is restored into the PC by the ret instruction and the program is returned to the address next to that of the call instruction SP operation by the call instruction 1 SP S...

Page 17: ... is pushed onto the stack as shown in the diagram below For returning from the handler routine the reti instruction is used to pop the contents of the PC and PSR off the stack In the reti instruction unlike in ordinary pop operation the PC and PSR are read out of the stack in that order and the SP address is altered as shown in the diagram below SP operation when an interrupt occurred 1 SP SP 4 2 ...

Page 18: ...Low Register hereinafter referred to as the ALR and the Arithmetic Operation High Register hereinafter referred to as the AHR Each is a 32 bit data register that allows data to be transferred to and from the general purpose registers using load instructions Multiply instructions use the ALR and the AHR to store the 32 low order bits and 32 high order bits of the result of operation respectively Wh...

Page 19: ...registers serve as an index register The register is actually written as r0 r1 or r15 with each register name enclosed in brackets to denote register indirect addressing In register indirect addressing the post increment function provided for continuous memory addresses can be used In such a case the register name is suffixed by as in r0 When post increment is specified each time memory is accesse...

Page 20: ...general purpose register The instruction that operates on a special register as the destination is as follows ld w sd rs The bit field that specifies a register in the instruction code contains the code corresponding to a given register number The relationship between the special registers and the register numbers is listed in the table below Table 2 9 2 1 Special Registers Special register PSR SP...

Page 21: ...ry is accessed in little endian format one byte halfword or word at a time If memory is to be accessed in halfword or word units the specified base address must be on a halfword boundary least significant address bit 0 or word boundary 2 low order address bits 00 respectively Unless this condition is satisfied an address misaligned exception is generated Byte 3 8 bit data 31 24 Byte 2 23 16 Byte 1...

Page 22: ... S S S S S 31 24 23 16 15 8 Byte 7 0 rd S S S S S S S S S S S S S S S S S S Byte Figure 3 4 1 Signed 8 Bit Transfer Memory Register Bits 31 8 in the destination register are sign extended 3 5 8 Bit Transfer Register Memory Example ld b rb rs X rs 31 24 X 23 16 X 15 8 Byte 7 0 Byte 7 0 rb Figure 3 5 1 8 Bit Transfer Register Memory 3 6 Unsigned 16 Bit Transfer Register Register Example ld uh rd rs ...

Page 23: ...0 0 0 31 16 15 Byte 0 Byte 1 0 0 0x 1 Byte 1 rd 0 0 0 0 0 0 0 0 Figure 3 8 1 Unsigned 16 Bit Transfer Memory Register Bits 31 16 in the destination register are zero extended 3 9 Signed 16 Bit Transfer Memory Register Example ld h rd rb S rb 0x 0 Byte 0 7 7 8 0 31 16 15 Byte 0 Byte 1 0 0x 1 Byte 1 rd S S S S S S S S S S S S S S S S S Figure 3 9 1 Signed 16 Bit Transfer Memory Register Bits 31 16 i...

Page 24: ...er Memory Register Example ld w rd rb rb 0x 00 Byte 0 7 7 8 0 31 16 15 Byte 0 Byte 1 23 24 Byte 2 Byte 3 0 0x 01 Byte 1 0x 10 Byte 2 0x 11 Byte 3 rd Figure 3 12 1 32 Bit Transfer Memory Register 3 13 32 Bit Transfer Register Memory Example ld w rb rs rb 0x 00 Byte 0 7 7 8 0 31 16 15 Byte 0 Byte 1 23 24 Byte 2 Byte 3 0 0x 01 Byte 1 0x 10 Byte 2 0x 11 Byte 3 rs Figure 3 13 1 32 Bit Transfer Register...

Page 25: ...BBR TTBR Figure 4 1 C33 PE Address Map Memories or I O devices can be mapped anywhere in the address space Note however that the addresses shown below cannot be used for user applications as they are reserved 0xC00000 This is the default reset vector address TTBR initial value The C33 PE Core starts executing the program from the boot address written to this address 0x402E0 0x402FF 0x4812D byte 0x...

Page 26: ...ion 16 bits 16 bits 32 bits Unsigned integer multiplication 16 bits 16 bits 32 bits Signed integer multiplication 32 bits 32 bits 64 bits Unsigned integer multiplication 32 bits 32 bits 64 bits PC relative conditional jump Branch condition Z N V Delayed branching possible PC relative conditional jump Branch condition N V Delayed branching possible PC relative conditional jump Branch condition N V ...

Page 27: ...Stack word general purpose register General purpose register word memory Postincrement possible General purpose register word stack No operation HALT SLEEP Extend operand in the following instruction Test a specified bit in memory data Clear a specified bit in memory data Set a specified bit in memory data Invert a specified bit in memory data Bytewise swap on byte boundary in word Push general pu...

Page 28: ... specified by immediate Arithmetic shift to the right Bits 0 31 shifted as specified by the register Arithmetic shift to the right Bits 0 31 shifted as specified by immediate Arithmetic shift to the left Bits 0 31 shifted as specified by the register Arithmetic shift to the left Bits 0 31 shifted as specified by immediate Rotate to the right Bits 0 31 rotated as specified by the register Rotate to...

Page 29: ...R onto the stack Pop data for special registers sd ALR off the stack jpr jpr d psrset psrclr ld c ld c do c ld cf swaph push pop pushs pops rb imm5 imm5 rd imm4 imm4 rs imm6 rd rs rs rd ss sd Mnemonic 5 4 Instructions Removed Table 5 4 1 Instructions Removed Classification Arithmetic operation Other Function First step in signed integer division First step in unsigned integer division Execution of...

Page 30: ...32 0b011111 to 0b100000 Except in the case of shift related and bit manipulating instructions immediate data can be extended to a maximum of 32 bits by a combined use of the operand value and the ext instruction Example ext imm13 1 ext imm13 2 ld w r0 sign6 r0 after execution imm13 1 r0 31 19 18 imm13 2 6 sign6 5 0 5 5 2 Register Direct Addressing The content of a specified register is used direct...

Page 31: ...r1 Register Memory ld b r1 r0 ld h r1 r0 ld w r1 r0 In this example the address indicated by r1 is the memory address from or to which data is to be transferred In halfword and word transfers the base address that is set in a register must be on a halfword boundary least significant address bit 0 or word boundary 2 low order address bits 0 respectively Otherwise an address misaligned exception wil...

Page 32: ...e least significant bit always 0 is the displacement ld w r0 sp 0x10 The word data at the address derived by adding 0x40 to the content of the current SP is loaded into the R0 register For word data transfers because word boundary addresses are accessed four times the 6 bit immediate 2 low order bits always 0 is the displacement If ext instructions described in Section 5 6 are used ordinary regist...

Page 33: ...n the ext instruction follows an ext the ext instruction will be executed as a nop instruction 5 6 1 Extension of Immediate Addressing Extension of imm6 The imm6 immediate is extended to a 19 bit or 32 bit immediate Extending to a 19 bit immediate To extend the immediate to 19 bit quantity enter one ext instruction directly before the target instruction Example ext imm13 add rd imm6 Extended immed...

Page 34: ...nstruction to the address that is indirectly referenced by rb Adding a 13 bit immediate Memory is accessed at the address derived by adding the 13 bit immediate specified by imm13 to the address specified by the rb register During address calculation imm13 is zero extended to 32 bit quantity Example ext imm13 ld b rd rb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 13 12 imm13 0 Immediate 31 Memory add...

Page 35: ...g to the transferred data size This applies to other than byte transfers Examples ext imm13 ld b rd sp imm6 ext imm13 ld h sp imm6 rs Extended immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 31 19 18 imm13 6 imm6 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 imm13 imm6 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 imm13 imm6 5 2 Byte transfer Halfword transfer Word transfer The extended data and the sp are added to comprise the source...

Page 36: ...etic operation performed An example of how to extend for an add operation is shown below Extending to rs imm13 To extend to rs imm13 enter one ext instruction directly before the target instruction Example ext imm13 add rd rs If not extended rd rd rs When extended by one ext instruction rd rs imm13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 13 12 imm13 0 Immediate 31 Data 0 rs 31 Data imm13 0 rd Ext...

Page 37: ... Example ext imm13 jrgt sign8 S S S S 0 0 0 S S S S S S S 31 22 21 9 8 imm13 sign8 0 Immediate 31 Current address 0 pc 31 New address 0 1 pc The most significant bit S in the immediate that has been extended by the ext instruction is the sign with which bits 31 22 are extended to become signed 22 bit data The most significant bit in sign8 is handled as the MSB data of 8 bit data and not as the sig...

Page 38: ...r other exceptions until after the target instruction to be extended is executed This is intended to simplify operation for the compression of ext instructions in prefetch Furthermore as the address to which the program is returned by reti or retd at the end of exception handling is the ext instruction in no case will the ext instructions operate erratically due to exception handling For two ext i...

Page 39: ...gned byte or halfword transfers the source data is zero extended to 32 bits In transfers in which data is transferred from registers data of a specified size on the lower side of the register is the data to be transferred If the destination of transfer is a general purpose register the register content after a transfer is as follows Signed byte data transfer S S S S S S S S 31 24 Extended with the...

Page 40: ...nd Logical AND or Logical OR xor Exclusive OR not Logical NOT All logical operations are performed in a specified general purpose register R0 R15 The source is one of two either 32 bit data in a specified general purpose register or signed immediate data 6 19 or 32 bits Differences from the C33 STD Core CPU When a logical operation is performed the V flag bit 2 in the PSR is cleared ...

Page 41: ...formed between one general purpose register and another R0 R15 or between a general purpose register and an immediate Furthermore the add and sub instructions can perform operations between the SP and immediate Immediates in sizes smaller than word except for the cmp instruction are zero extended when operation is performed The cmp instruction compares two operands and may alter a flag depending o...

Page 42: ...d for the multiplier and the multiplicand respectively For 16 bit multiplications the 16 low order bits in the specified register are used The signed multiplication instructions use the MSB in the multiplier and multiplicand as the sign bit The result of a 16 bit 16 bit operation is loaded into the ALR The result of a 32 bit 32 bit operation is loaded into the AHR and ALR with the 32 high order bi...

Page 43: ... 0 31 logically shifted to the right srl rd rs Bits 0 31 logically shifted to the right 31 0 C rd srl Logical shift right 0 0 31 C rd 0 sll Logical shift left 31 0 C MSB Sign bit rd sra Arithmetic shift right 0 31 C rd 0 sla Arithmetic shift left 31 0 C rd rr Rotate right 31 C rd 0 rl Rotate left The table below lists the number of bits shifted as specified by the rs register or the operand imm5 T...

Page 44: ...3 Set a specified bit to 1 bnot rb imm3 Invert a specified bit 1 0 Bit manipulation is performed on the memory address specified by the rb general purpose register imm3 specifies a bit number bits 0 7 in the byte data stored in that address location Although the content of memory data altered by these instructions except btst is only the specified bit the specified address is rewritten because mem...

Page 45: ...are saved and restored Because in addition to the push pop instructions load instructions are available for register indirect addressing with displacement sp imm6 where the SP is the base address individual store load operations on each register can be performed with respect to the SP In this case however the SP is not altered A specific register number is assigned to each register refer to Chapte...

Page 46: ... of pushs low address 31 0 After execution of pushs ahr alr low address SP SP Figure 5 13 3 Successive Push of Special Registers 31 0 Before execution of pops low address 31 0 After execution of pops ahr alr ahr alr low address SP SP Figure 5 13 4 Successive Pop of Special Registers Example 3 push rs Push any general purpose register onto the stack pop rd Pop any general purpose register off the s...

Page 47: ...placement actually added to the PC is a signed 9 bit quantity derived by doubling sign8 least significant bit always 0 The specifiable displacement can be extended by the ext instruction as shown below For branch instructions used singly jp sign8 Functions as jp sign9 sign9 sign8 0 For branch instructions that are used singly a signed 8 bit displacement sign8 can be specified S 0 9 8 sign8 0 sign9...

Page 48: ...nge of memory areas used Branch conditions The jp and jpr instructions are unconditional jump instructions that always cause the program to branch Instructions with names beginning with jr are conditional jump instructions for which the respective branch conditions are set by a combination of flags so that only when the conditions are satisfied do they cause the program to branch to a specified ad...

Page 49: ...ts least significant bit is always made 0 Refer to the 2 Absolute jump instructions 5 Software exceptions The software exception int imm2 is an instruction that causes the software to generate an exception by which a specified exception handler routine can be executed Four distinct exception handler routines can be created with the respective vector numbers specified by imm2 When a software except...

Page 50: ...nch instruction name Delayed branch instructions jrgt d jrge d jrlt d jrle d jrugt d jruge d jrult d jrule d jreq d jrne d call d jp d ret d jpr d Delayed slot instructions It is necessary that the delayed slot instructions satisfy all of the following conditions 1 cycle instruction Do not access memory Not extended by an ext instruction The instructions listed below can be used as delayed slot in...

Page 51: ...ing the delayed slot instruction so that the delayed slot instruction is not executed when the program returns from the subroutine No interrupts or exceptions occur in between a delayed branch instruction and a delayed slot instruction as they are masked out by hardware Application for leaf subroutines The following shows an example application of delayed branch instructions for achieving a fast l...

Page 52: ... used to control the system They do not affect the registers or memory nop Only increments the PC with no other operations performed halt Places the processor in HALT mode slp Places the processor in SLEEP mode For details on HALT and SLEEP modes refer to Section 6 4 Power Down Mode and the Technical Manual for each S1C33 model ...

Page 53: ...on a word boundary 8 7 16 15 24 23 Byte 0 Byte 1 Byte 2 Byte 3 0 rs 31 8 7 16 15 24 23 Byte 3 Byte 2 Byte 1 Byte 0 0 rd 31 swaph rd rs The 32 bit data in general purpose registers has its big and little endians converted on a halfword boundary 8 7 16 15 24 23 Byte 0 Byte 1 Byte 2 Byte 3 0 rs 31 8 7 16 15 24 23 Byte 1 Byte 0 Byte 3 Byte 2 0 rd 31 Differences from the C33 STD Core CPU The swaph inst...

Page 54: ...e PSR flags to be manipulated directly As these flag control instructions can set and clear flags bitwise it is possible to control interrupts by enabling or disabling in one instruction psrset imm5 Sets the PSR bit specified by imm5 2 0 0 4 to 1 psrclr imm5 Clears the PSR bit specified by imm5 2 0 0 4 to 0 The contents of PSR are not altered when the imm5 is 5 or more ...

Page 55: ...when an exception occurs or the slp or halt instruction is executed 6 1 3 Exception Handling When a software or other exception occurs the processor enters an exception handling state The following are the possible causes of the need for exception handling 1 External interrupt 2 Software exception 3 Address misaligned exception 4 Zero division 5 NMI 6 Undefined instruction exception ext exception ...

Page 56: ...can be set for the exception vector table address in the software In this case the addresses set in the TTBR must be aligned with the 1K byte boundary TTBR 9 0 fixed to 00 0000 0000 6 2 1 Instruction Fetch and Execution Internally in the C33 PE Core instructions are processed in two pipelined stages so that data transfer between registers and general arithmetic logic instructions can be executed i...

Page 57: ...clock cycle The number of clock cycles required for accesses to the internal RAM and caches as well as flag changes that occur pursuant to memory accesses are given below C33 STD Core CPU compatible instructions Table 6 2 2 1 Number of Instruction Execution Cycles and Flag Status C33 STD Compatible Instructions Classification Arithmetic operation Branch Remark PSR change IE 0 IE no change Cycle 1 ...

Page 58: ...m3 rd rs rs rd Mnemonic Remark Cycle 1 1 2 4 2 2 1 2 4 2 2 1 1 2 4 2 2 1 1 2 4 2 2 1 2 4 2 2 1 1 2 4 2 2 1 1 1 2 4 2 2 1 2 4 2 2 1 5 5 0 1 2 2 3 4 3 4 4 3 4 4 3 4 4 1 N 1 N 1 C V Z N Flag Function extended instructions Table 6 2 2 2 Number of Instruction Execution Cycles and Flag Status Function Extended Instructions Classification Logical operation Shift and rotate Data transfer and or xor not sr...

Page 59: ...2 3 6 2 3 6 C V Z N Flag 1 Three cycles when the branch conditions are satisfied and the instruction is not a delayed branch instruction 2 Zero cycles when lookahead decoding is possible 3 When a branch instruction does not involve a delayed branch not accompanied by the extension d a 1 instruction equivalent blank time occurs as no instructions are executed during a branch therefore apparently 1 ...

Page 60: ...0x00060000 TTBR 0x1C TTBR 0x30 to TTBR 0x3C TTBR 0x40 to TTBR 0x3FC Priority High Low When two or more exceptions occur simultaneously they are processed in order of priority beginning with the one that has the highest priority When an exception occurs the processor disables interrupts that would occur thereafter and performs exception handling To support multiple interrupts or another interrupt f...

Page 61: ...ith the program execution are classified as exceptions and those that occur asynchronously are classified as interrupts In this manual the internal processing performed by the processor for interrupts and exceptions that occurred is referred to collectively as exception handling The vector address is one that contains a vector or the jump address for the user s exception handler routine that is pr...

Page 62: ...essor starts operating at the rising edge of the RESET pulse to perform a reset sequence In this reset sequence the reset vector is read out from the top of the vector table and set in the PC The processor thereby branches to the user s initialization routine in which it starts executing the program The reset sequence has priority over all other processing 6 3 5 Address Misaligned Exception The lo...

Page 63: ... IE interrupt enable flag in the PSR is set that the processor accepts a maskable external interrupt Furthermore their acceptable interrupt levels are limited by the IL interrupt level field in the PSR The interrupt levels 0 15 in the IL field dictate the interrupt levels that can be accepted by the processor and only interrupts with priority levels higher than that are accepted The IE flag and th...

Page 64: ...the instruction address that follows the undefined instruction executed Address TTBR 12 is used to store the undefined instruction exception vector 6 3 10 ext Exception If three or more ext instructions are described sequentially an ext exception occurs when the third ext instruction is detected In this case the PC value that is saved into the stack by the exception processing is the first ext ins...

Page 65: ...T or SLEEP mode Initial reset is one cause that can be bring the processor out of HALT or SLEEP mode Other causes depend on the implementation of the clock control circuit outside the C33 PE Core Initial reset maskable external interrupts NMI and debug exceptions are commonly used for canceling HALT and SLEEP modes The interrupt enable disable status set in the processor does not affect the cancel...

Page 66: ...he status of instruction execution by the processor is traced When a debug exception occurs the processor performs the following processing 1 Suspends the instruction currently being executed A debug exception is generated at the end of the E stage of the currently executed instruction and is accepted at the next rise of the system clock 2 Saves the contents of the PC and R0 in that order to the a...

Page 67: ...s configured as a simple interface consisting of only a 16 bit instruction bus and 32 bit input and output data buses Dedicated coprocessor instructions ld c rd imm4 Transfer data from the coprocessor ld c imm4 rs Transfer data to the coprocessor do c imm6 Execute the coprocessor ld cf Transfer C V Z and N flags from the coprocessor The concrete commands and status of the coprocessor vary with eac...

Page 68: ...content The register field rd rs sd or ss in the code contains a register number General purpose registers rd rs R0 0b0000 R1 0b0001 R15 0b1111 Special registers sd ss PSR 0b0000 SP 0b0001 ALR 0b0010 AHR 0b0011 TTBR 0b1000 IDIR 0b1010 DBBR 0b1011 PC 0b1111 immX Unsigned immediate X bits in length The X contains a number representing the bit length of the immediate signX Signed immediate X bits in ...

Page 69: ...gister direct rd r0 to r15 CLK One cycle Description 1 Standard adc rd rs rd rd rs C The content of the rs register and C carry flag are added to the rd register 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the d bit Example 1 adc r0 r1 r0 r0 r1 C 2 Addition of 64 bit data data 1 r2 r1 data2 r4 r3 result r2 r...

Page 70: ...ntent of the rs register after being zero extended and the result is loaded into the rd register The content of the rs register is not altered 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 add rd rs rd rs imm26 The 26 bit immediate imm26 is added to the content of the rs register after being zero extended and the result is loaded into the rd register The content of the rs register is no...

Page 71: ...o extended 2 Extension 1 ext imm13 imm19 18 6 add rd imm6 rd rd imm19 imm6 imm19 5 0 The 19 bit immediate imm19 is added to the rd register after being zero extended 3 Extension 2 ext imm13 imm32 31 19 ext imm13 imm32 18 6 add rd imm6 rd rd imm32 imm6 imm32 5 0 The 32 bit immediate imm32 is added to the rd register 4 Delayed instruction This instruction may be executed as a delayed instruction by ...

Page 72: ...E C V Z N Mode Src Immediate data unsigned Dst Register direct SP CLK One cycle Description 1 Standard Quadruples the 10 bit immediate imm10 and adds it to the stack pointer SP The imm10 is zero extended into 32 bits prior to the operation 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the d bit Example add sp ...

Page 73: ...of the rs register and the zero extended 13 bit immediate imm13 are logically AND ed and the result is loaded into the rd register The content of the rs register is not altered 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 and rd rs rd rs imm26 The content of the rs register and the zero extended 26 bit immediate imm26 are logically AND ed and the result is loaded into the rd register T...

Page 74: ...sign19 18 6 and rd sign6 rd rd sign19 sign6 sign19 5 0 The content of the rd register and the sign extended 19 bit immediate sign19 are logically AND ed and the result is loaded into the rd register 3 Extension 2 ext imm13 sign32 31 19 ext imm13 sign32 18 6 and rd sign6 rd rd sign32 sign6 sign32 5 0 The content of the rd register and the 32 bit immediate sign32 are logically AND ed and the result ...

Page 75: ...egister indirect addressing with displacement The extended instruction clears the data bit specified with the imm3 in the address specified by adding the 13 bit immediate imm13 to the contents of the rb register It does not change the contents of the rb register 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 bclr rb imm3 B rb imm26 imm3 0 The ext instructions change the addressing mode t...

Page 76: ... addressing mode to register indirect addressing with displacement The extended instruction reverses the data bit specified with the imm3 in the address specified by adding the 13 bit immediate imm13 to the contents of the rb register It does not change the contents of the rb register 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 bnot rb imm3 B rb imm26 imm3 B rb imm26 imm3 The ext inst...

Page 77: ...instruction stores the address that follows this instruction and the contents of the R0 register into the stack for debugging then reads the vector for the debug handler routine from the debug vector address 0x0060000 and sets it to the PC Thus the program branches to the debug handler routine Furthermore the processor enters the debug mode The retd instruction must be used for return from the deb...

Page 78: ... register indirect addressing with displacement The extended instruction sets the data bit specified with the imm3 in the address specified by adding the 13 bit immediate imm13 to the contents of the rb register It does not change the contents of the rb register 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 bset rb imm3 B rb imm26 imm3 1 The ext instructions change the addressing mode t...

Page 79: ...1 if B rb imm13 imm3 0 else Z flag 0 The ext instruction changes the addressing mode to register indirect addressing with displacement The extended instruction tests the data bit specified with the imm3 in the address specified by adding the 13 bit immediate imm13 to the contents of the rb register It does not change the contents of the rb register 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm...

Page 80: ...e instruction following the call instruction 2 Delayed branch d bit 1 call d rb When call d is specified the d bit in the instruction code is set and the following instruction becomes a delayed instruction The delayed instruction is executed before branching to the subroutine Therefore the address PC 4 of the instruction that follows the delayed instruction is stored into the stack as the return a...

Page 81: ...e 22 bit displacement is sign extended and added to the PC The sign22 allows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 call sign8 call sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement into 32 bits using their two 13 bit immediates imm13 2 The displacement covers the entire address spa...

Page 82: ...3 from the contents of the rs register and sets or resets the flags C V Z and N according to the results It does not change the contents of the rd and rs registers 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 cmp rd rs rs imm26 Subtracts the 26 bit immediate imm26 from the contents of the rs register and sets or resets the flags C V Z and N according to the results It does not change t...

Page 83: ...he contents of the rd register and sets or resets the flags C V Z and N according to the results The sign19 is sign extended into 32 bits prior to the operation It does not change the contents of the rd register 3 Extension 2 ext imm13 sign32 31 19 ext imm13 sign32 18 6 cmp rd sign6 rd sign32 sign6 sign32 5 0 Subtracts the signed 32 bit immediate sign32 extended with the ext instruction from the c...

Page 84: ... Extension 1 Unusable Extension 2 Unusable Code 15 12 11 8 7 6 5 0 1 0 1 1 1 1 1 1 0 0 imm6 0xBF0_ Flag IE C V Z N Mode Immediate unsigned CLK One cycle Description The command specified by imm6 is issued to the coprocessor imm6 is output to the dedicated coprocessor address bus Example do c 0x1a coprocessor execute command 1A ...

Page 85: ... will occur See descriptions of each instruction for the extension contents and the usage Exceptions for the ext instruction not including reset and debug break are masked in the hardware and exception handling is determined when the target instruction to be extended is executed In this case the return address from exception handling is the beginning of the ext instruction Example ext 0x1000 ext 0...

Page 86: ...ernal interrupts NMI and debug exceptions are commonly used for canceling HALT mode The interrupt enable disable status set in the processor does not affect the cancellation of HALT mode even if an interrupt signal is used as the cancellation In other words interrupt signals are able to cancel HALT mode even if the IE flag in PSR or the interrupt enable bits in the interrupt controller depending o...

Page 87: ...he stack then reads the software exception vector from the trap table and sets it to the PC By this processing the program flow branches to the specified software exception handler routine The C33 PE supports four types of software exceptions and the software exception number 0 to 3 is specified by the 2 bit immediate imm2 imm2 Vector address Software exception 0 0 Base 48 Software exception 1 1 B...

Page 88: ...r is ignored and is always handled as 0 2 Delayed branch d bit 1 jp d rb For the jp d instruction the next instruction becomes a delayed instruction A delayed instruction is executed before the program branches Exceptions are masked in intervals between the jp d instruction and the next instruction so no interrupts or exceptions occur Example jp r0 Jumps to the address specified by the R0 register...

Page 89: ...ows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 jp sign8 jp sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement to be added to the PC into signed 32 bits using their 13 bit immediates imm13 2 The displacement covers the entire address space Note that the low order 3 bits of the first imm13...

Page 90: ...he program branches to that address 2 Delayed branch d bit 1 jpr d rb For the jpr d instruction the next instruction becomes a delayed instruction A delayed instruction is executed before the program branches Exceptions are masked in intervals between the jpr d instruction and the next instruction so no interrupts or exceptions occur Example jpr r0 PC PC R0 Caution When the jpr d instruction delay...

Page 91: ...truction extends the displacement to be added to the PC into signed 22 bits using its 13 bit immediate data imm13 The sign22 allows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 jreq sign8 jreq sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement to be added to the PC into signed 32 bits usin...

Page 92: ...The ext instruction extends the displacement to be added to the PC into signed 22 bits using its 13 bit immediate data imm13 The sign22 allows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 jrge sign8 jrge sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement to be added to the PC into signed 3...

Page 93: ...gn22 0 0 The ext instruction extends the displacement to be added to the PC into signed 22 bits using its 13 bit immediate data imm13 The sign22 allows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 jrgt sign8 jrgt sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement to be added to the PC into...

Page 94: ...gn22 0 0 The ext instruction extends the displacement to be added to the PC into signed 22 bits using its 13 bit immediate data imm13 The sign22 allows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 jrle sign8 jrle sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement to be added to the PC into...

Page 95: ...The ext instruction extends the displacement to be added to the PC into signed 22 bits using its 13 bit immediate data imm13 The sign22 allows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 jrlt sign8 jrlt sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement to be added to the PC into signed 3...

Page 96: ...truction extends the displacement to be added to the PC into signed 22 bits using its 13 bit immediate data imm13 The sign22 allows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 jrne sign8 jrne sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement to be added to the PC into signed 32 bits usin...

Page 97: ...ext instruction extends the displacement to be added to the PC into signed 22 bits using its 13 bit immediate data imm13 The sign22 allows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 jruge sign8 jruge sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement to be added to the PC into signed 32 ...

Page 98: ... 0 0 The ext instruction extends the displacement to be added to the PC into signed 22 bits using its 13 bit immediate data imm13 The sign22 allows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 jrugt sign8 jrugt sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement to be added to the PC into s...

Page 99: ... 0 0 The ext instruction extends the displacement to be added to the PC into signed 22 bits using its 13 bit immediate data imm13 The sign22 allows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 jrule sign8 jrule sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement to be added to the PC into s...

Page 100: ...ext instruction extends the displacement to be added to the PC into signed 22 bits using its 13 bit immediate data imm13 The sign22 allows branches within the range of PC 0x200000 to PC 0x1FFFFE 3 Extension 2 ext imm13 imm13 12 3 sign32 31 22 ext imm13 sign32 21 9 jrult sign8 jrult sign32 sign8 sign32 8 1 sign32 0 0 The ext instructions extend the displacement to be added to the PC into signed 32 ...

Page 101: ... r d 0xA1__ Flag IE C V Z N Mode Src Register direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The 8 low order bits of the rs register are transferred to the rd register after being sign extended to 32 bits 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the d bit Example...

Page 102: ...ts The rb register contains the memory address to be accessed 2 Extension 1 ext imm13 ld b rd rb memory address rb imm13 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the content of the rb register with the 13 bit immediate imm13 added comprises the memory address the byte data in which is transferred to the rd register The content of...

Page 103: ... 0 0 0 1 0 0 0 0 1 r b r d 0x21__ Flag IE C V Z N Mode Src Register indirect with post increment rb r0 to r15 Dst Register direct rd r0 to r15 CLK Two cycles Description The byte data in the specified memory location is transferred to the rd register after being sign extended to 32 bits The rb register contains the memory address to be accessed Following data transfer the address in the rb registe...

Page 104: ...f the current SP with the 6 bit immediate imm6 added as displacement comprises the memory address to be accessed 2 Extension 1 ext imm13 imm19 18 6 ld b rd sp imm6 memory address sp imm19 imm6 imm19 5 0 The ext instruction extends the displacement to a 19 bit quantity As a result the content of the SP with the 19 bit immediate imm19 added comprises the memory address the byte data in which is tran...

Page 105: ...dress to be accessed 2 Extension 1 ext imm13 ld b rb rs memory address rb imm13 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the 8 low order bits of the rs register are transferred to the address indicated by the content of the rb register with the 13 bit immediate imm13 added The content of the rb register is not altered 3 Extension...

Page 106: ...8 7 4 3 0 0 0 1 1 0 1 0 1 r b r s 0x35__ Flag IE C V Z N Mode Src Register direct rs r0 to r15 Dst Register indirect with post increment rb r0 to r15 CLK Two cycles Description The 8 low order bits of the rs register are transferred to the specified memory location The rb register contains the memory address to be accessed Following data transfer the address in the rb register is incremented by 1 ...

Page 107: ...dded as displacement comprises the memory address to be accessed 2 Extension 1 ext imm13 imm19 18 6 ld b sp imm6 rs memory address sp imm19 imm6 imm19 5 0 The ext instruction extends the displacement to a 19 bit quantity As a result The 8 low order bits of the rs register are transferred to the address indicated by the content of the SP with the 19 bit immediate imm19 added 3 Extension 2 ext imm13...

Page 108: ...E C V Z N Mode Src Immediate unsigned Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The contents of the coprocessor register specified by imm4 is transferred to the general purpose register rd imm4 is output to the dedicated coprocessor address bus 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instructi...

Page 109: ... C V Z N Mode Src Register direct rs r0 to r15 Dst Immediate unsigned CLK One cycle Description 1 Standard The contents of the general purpose register rs is transferred to the coprocessor register specified by imm4 imm4 is output to the dedicated coprocessor address bus 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instructio...

Page 110: ... the coprocessor Standard PSR 3 0 coprocessor flag Extension 1 Unusable Extension 2 Unusable Code 15 12 11 8 7 4 3 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0x01D0 Flag IE C V Z N Mode CLK Three cycles Description The C V Z and N flags are transferred from the coprocessor to the PSR 3 0 Example ld cf copy coprocessor flag ...

Page 111: ... r s r d 0xA9__ Flag IE C V Z N Mode Src Register direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The 16 low order bits of the rs register are transferred to the rd register after being sign extended to 32 bits 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the d bit Ex...

Page 112: ...m13 ld h rd rb memory address rb imm13 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the content of the rb register with the 13 bit immediate imm13 added comprises the memory address the halfword data in which is transferred to the rd register The content of the rb register is not altered 3 Extension 2 ext imm13 imm26 25 13 ext imm13 ...

Page 113: ...r15 CLK Two cycles Description The halfword data in the specified memory location is transferred to the rd register after being sign extended to 32 bits The rb register contains the memory address to be accessed Following data transfer the address in the rb register is incremented by 2 Caution 1 The rb register must specify a halfword boundary address least significant bit 0 Specifying an odd addr...

Page 114: ...essed The least significant bit of the displacement is always 0 2 Extension 1 ext imm13 imm19 18 6 ld h rd sp imm6 memory address sp imm19 imm6 imm19 5 0 The ext instruction extends the displacement to a 19 bit quantity As a result the content of the SP with the 19 bit immediate imm19 added comprises the memory address the halfword data in which is transferred to the rd register Make sure the imm6...

Page 115: ...ext instruction changes the addressing mode to register indirect addressing with displacement As a result the 16 low order bits of the rs register are transferred to the address indicated by the content of the rb register with the 13 bit immediate imm13 added The content of the rb register is not altered 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 ld h rb rs memory address rb imm26 Th...

Page 116: ...r0 to r15 Dst Register indirect with post increment rb r0 to r15 CLK Two cycles Description The 16 low order bits of the rs register are transferred to the specified memory location The rb register contains the memory address to be accessed Following data transfer the address in the rb register is incremented by 2 Caution The rb register and the displacement must specify a halfword boundary addres...

Page 117: ...t is always 0 2 Extension 1 ext imm13 imm19 18 6 ld h sp imm6 rs memory address sp imm19 imm6 imm19 5 0 The ext instruction extends the displacement to a 19 bit quantity As a result the 16 low order bits of the rs register are transferred to the address indicated by the content of the SP with the 19 bit immediate imm19 added Make sure the imm6 specified here resides on a halfword boundary least si...

Page 118: ... r d 0xA5__ Flag IE C V Z N Mode Src Register direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The 8 low order bits of the rs register are transferred to the rd register after being zero extended to 32 bits 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the d bit Example...

Page 119: ...gister contains the memory address to be accessed 2 Extension 1 ext imm13 ld ub rd rb memory address rb imm13 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the content of the rb register with the 13 bit immediate imm13 added comprises the memory address the byte data in which is transferred to the rd register The content of the rb reg...

Page 120: ... 0 0 0 1 0 0 1 0 1 r b r d 0x25__ Flag IE C V Z N Mode Src Register indirect with post increment rb r0 to r15 Dst Register direct rd r0 to r15 CLK Two cycles Description The byte data in the specified memory location is transferred to the rd register after being zero extended to 32 bits The rb register contains the memory address to be accessed Following data transfer the address in the rb registe...

Page 121: ...P with the 6 bit immediate imm6 added as displacement comprises the memory address to be accessed 2 Extension 1 ext imm13 imm19 18 6 ld ub rd sp imm6 memory address sp imm19 imm6 imm19 5 0 The ext instruction extends the displacement to a 19 bit quantity As a result the content of the SP with the 19 bit immediate imm19 added comprises the memory address the byte data in which is transferred to the...

Page 122: ...r s r d 0xAD__ Flag IE C V Z N Mode Src Register direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The 16 low order bits of the rs register are transferred to the rd register after being zero extended to 32 bits 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the d bit Exa...

Page 123: ...b memory address rb imm13 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the content of the rb register with the 13 bit immediate imm13 added comprises the memory address the halfword data in which is transferred to the rd register The content of the rb register is not altered 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 ld...

Page 124: ...5 CLK Two cycles Description The halfword data in the specified memory location is transferred to the rd register after being zero extended to 32 bits The rb register contains the memory address to be accessed Following data transfer the address in the rb register is incremented by 2 Caution 1 The rb register must specify a halfword boundary address least significant bit 0 Specifying an odd addres...

Page 125: ...gnificant bit of the displacement is always 0 2 Extension 1 ext imm13 imm19 18 6 ld uh rd sp imm6 memory address sp imm19 imm6 imm19 5 0 The ext instruction extends the displacement to a 19 bit quantity As a result the content of the SP with the 19 bit immediate imm19 added comprises the memory address the halfword data in which is transferred to the rd register Make sure the imm6 specified here r...

Page 126: ... 0 1 1 1 0 r s r d 0x2E__ Flag IE C V Z N Mode Src Register direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The content of the rs register word data is transferred to the rd register 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the d bit Example ld w r0 r1 r0 r1 ...

Page 127: ...ter word data is transferred to the rd register Example ld w r0 psr r0 psr Caution 1 When a ld w rd pc instruction is executed a value equal to the PC of this ld w instruction plus 2 is loaded into the register This instruction must be executed as a delayed slot instruction If it does not follow a delayed branch instruction the PC value that is loaded into the rd register may not be the next instr...

Page 128: ...nges the addressing mode to register indirect addressing with displacement As a result the content of the rb register with the 13 bit immediate imm13 added comprises the memory address the word data in which is transferred to the rd register The content of the rb register is not altered 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 ld w rd rb memory address rb imm26 The addressing mode ...

Page 129: ...Two cycles Description The word data in the specified memory location is transferred to the rd register The rb register contains the memory address to be accessed Following data transfer the address in the rb register is incremented by 4 Caution 1 The rb register and the displacement must specify a word boundary address two least significant bits 0 Specifying other addresses causes an address misa...

Page 130: ... the displacement are always 0 2 Extension 1 ext imm13 imm19 18 6 ld w rd sp imm6 memory address sp imm19 imm6 imm19 5 0 The ext instruction extends the displacement to a 19 bit quantity As a result the content of the SP with the 19 bit immediate imm19 added comprises the memory address the word data in which is transferred to the rd register Make sure the imm6 specified here resides on a word bou...

Page 131: ...nded 2 Extension 1 ext imm13 sign19 18 6 ld w rd sign6 rd sign19 sign extended sign6 sign19 5 0 The immediate data is extended into a 19 bit quantity by the ext instruction and it is loaded to the rd register after being sign extended 3 Extension 2 ext imm13 sign32 31 19 ext imm13 sign32 18 6 ld w rd sign6 rd sign32 sign6 sign32 5 0 The immediate data is extended into a 32 bit quantity by the ext ...

Page 132: ...sd is the PSR the content of rs is copied Mode Src Register direct rs r0 to r15 Dst Register direct sd psr sp alr ahr ttbr pc CLK One cycle three cycles when sd psr Description The content of the rs register word data is transferred to a special register Example ld w sp r0 sp r0 Caution When a special register other than the destination registers listed above is specified as sd the ld w instructio...

Page 133: ... instruction changes the addressing mode to register indirect addressing with displacement As a result the content of the rs register is transferred to the address indicated by the content of the rb register with the 13 bit immediate imm13 added The content of the rb register is not altered 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 ld w rb rs memory address rb imm26 The addressing m...

Page 134: ...5 Dst Register indirect with post increment rb r0 to r15 CLK Two cycles Description The content of the rs register word data is transferred to the specified memory location The rb register contains the memory address to be accessed Following data transfer the address in the rb register is incremented by 4 Caution The rb register and the displacement must specify a word boundary address two least s...

Page 135: ...cant bits of the displacement are always 0 2 Extension 1 ext imm13 imm19 18 6 ld w sp imm6 rs memory address sp imm19 imm6 imm19 5 0 The ext instruction extends the displacement to a 19 bit quantity As a result the content of the rs register is transferred to the address indicated by the content of the SP with the 19 bit immediate imm19 added Make sure the imm6 specified here resides on a word bou...

Page 136: ... 0 1 0 1 0 0 0 1 0 r s r d 0xA2__ Flag IE C V Z N Mode Src Register direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK Five cycles Description The 16 low order bits of the rd register and the 16 low order bits of the rs register are multiplied together with the signs and the 32 bit product resulting from the operation is loaded into the ALR register Example mlt h r0 r1 alr r0 15 0 r1 15 0 si...

Page 137: ...4 3 0 1 0 1 0 1 0 1 0 r s r d 0xAA__ Flag IE C V Z N Mode Src Register direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK Seven cycles Description The content of the rd register and the content of the rs register are multiplied together with the signs and the 64 bit product resulting from the operation is loaded into the AHR and ALR register pair Example mlt w r0 r1 ahr alr r0 r1 signed mult...

Page 138: ... 0 1 0 1 0 0 1 1 0 r s r d 0xA6__ Flag IE C V Z N Mode Src Register direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK Five cycles Description The 16 low order bits of the rd register and the 16 low order bits of the rs register are multiplied together without signs and the 32 bit product resulting from the operation is loaded into the ALR register Example mltu h r0 r1 alr r0 15 0 r1 15 0 un...

Page 139: ...4 3 0 1 0 1 0 1 1 1 0 r s r d 0xAE__ Flag IE C V Z N Mode Src Register direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK Seven cycles Description The content of the rd register and the content of the rs register are multiplied together without signs and the 64 bit product resulting from the operation is loaded into the AHR and ALR register pair Example mltu w r0 r1 ahr alr r0 r1 unsigned mu...

Page 140: ...n Standard No operation Extension 1 Unusable Extension 2 Unusable Code 15 12 11 8 7 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Flag IE C V Z N Mode CLK One cycle Description The nop instruction just takes 1 cycle and no operation results The PC is incremented 2 Example nop nop Waits 2 cycles ...

Page 141: ...__ Flag IE C V Z N 0 Mode Src Register direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard All the bits of the rs register are reversed and the result is loaded into the rd register 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the d bit Example When r1 0x55555555 not r0 r...

Page 142: ...xt imm13 sign19 18 6 not rd sign6 rd sign19 sign6 sign19 5 0 All the bits of the sign extended 19 bit immediate sign19 are reversed and the result is loaded into the rd register 3 Extension 2 ext imm13 sign32 31 19 ext imm13 sign32 18 6 not rd sign6 rd sign32 sign6 sign32 5 0 All the bits of the sign extended 32 bit immediate sign32 are reversed and the result is loaded into the rd register 4 Dela...

Page 143: ... of the rs register and the zero extended 13 bit immediate imm13 are logically OR ed and the result is loaded into the rd register The content of the rs register is not altered 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 or rd rs rd rs imm26 The content of the rs register and the zero extended 26 bit immediate imm26 are logically OR ed and the result is loaded into the rd register The...

Page 144: ... 18 6 or rd sign6 rd rd sign19 sign6 sign19 5 0 The content of the rd register and the sign extended 19 bit immediate sign19 are logically OR ed and the result is loaded into the rd register 3 Extension 2 ext imm13 sign32 31 19 ext imm13 sign32 18 6 or rd sign6 rd rd sign32 sign6 sign32 5 0 The content of the rd register and the sign extended 32 bit immediate sign32 are logically OR ed and the res...

Page 145: ...ect rd r0 to r15 CLK One cycle Description The data of a general purpose register that has been saved to the stack by a push instruction is restored from the stack The pop instruction restores word data from the stack with an address indicated by the current SP to the rd register and increments the SP by an amount equivalent to 1 word 4 bytes Stack operation when pop rd is executed SP 31 0 rd Data...

Page 146: ...aved to the stack by a pushn instruction is restored from the stack The popn instruction restores word data from the stack with its address indicated by the current SP to the r0 register and increments the SP by an amount equivalent to 1 word 4 bytes This operation is repeated until a register that matches rd is reached The rd must be the same register as specified in the corresponding pushn instr...

Page 147: ...the SP is incremented by an amount equivalent to 1 word 4 bytes 2 When the sd register is the AHR register The word data at the address indicated by the current SP is restored to the ALR register and the SP is incremented by an amount equivalent to 1 word 4 bytes Next the word data at the address indicated by the current SP is restored to the AHR register and the SP is incremented by an amount equ...

Page 148: ...1 0 1 1 1 1 1 1 1 0 0 imm5 0xBF8_ Flag IE C V Z N Mode Immediate CLK Three cycles Description Clear the bit in the PSR specified by the immediate imm5 to 0 The value of imm5 indicates a bit number with values 0 1 2 3 and 4 representing bits 0 N 1 Z 2 V 3 C and 4 IE respectively An imm5 of more than 4 is not effective and does not alter the contents of PSR Example psrclr 2 V 0 V flag cleared ...

Page 149: ...0 1 0 1 1 1 1 1 1 0 1 0 imm5 0xBF4_ Flag IE C V Z N Mode Immediate CLK Three cycles Description Set the bit in the PSR specified by the immediate imm5 to 1 The value of imm5 indicates a bit number with values 0 1 2 3 and 4 representing bits 0 N 1 Z 2 V 3 C and 4 IE respectively An imm5 of more than 4 is not effective and does not alter the contents of PSR Example psrset 2 V 1 V flag set ...

Page 150: ... 0 0 1 r s 0x001_ Flag IE C V Z N Mode Register direct rs r0 to r15 CLK Two cycles Description Save the data of a general purpose register to the stack The push instruction first decrements the current SP by an amount equivalent to 1 word 4 bytes and saves the content of the rs register to that address Stack operation when push rs is executed SP 31 0 SP 31 0 rs data Example push r3 sp sp 4 W sp r3...

Page 151: ...CLK N 1 cycles where N number of registers to be saved Description Save the data of general purpose registers to the stack The pushn instruction first decrements the current SP by an amount equivalent to 1 word 4 bytes and saves the content of the rs register to that address This operation is repeated successively until the r0 register is reached Stack operation when pushn rs where rs r3 is execut...

Page 152: ... word 4 bytes and the content of the ALR register is saved to that address 2 When the ss register is the AHR register The current SP is decremented by an amount equivalent to 1 word 4 bytes and the content of the AHR register is saved to that address Next SP is decremented by an amount equivalent to 1 word 4 bytes and the content of the ALR register is saved to that address Stack operation when pu...

Page 153: ...he SP has been modified in the subroutine it is necessary to return the SP value before executing the ret instruction 2 Delayed branch d bit 1 ret d For the ret d instruction the next instruction becomes a delayed instruction A delayed instruction is executed before the program returns from the subroutine Exceptions are masked in intervals between the ret d instruction and the next instruction so ...

Page 154: ...nsion 2 Unusable Code 15 12 11 8 7 4 3 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0x0440 Flag IE C V Z N Mode CLK Five cycles Description Restore the contents of the R0 and PC that were saved to the debug exception memory space when an debug exception occurred to the respective registers and return from the debug exception handler routine Example retd Return from a debug exception handler routine ...

Page 155: ... Code 15 12 11 8 7 4 3 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0x04C0 Flag IE C V Z N Mode CLK Five cycles Description Restore the contents of the PC and PSR that were saved to the stack when an exception or interrupt occurred to the respective registers and return from the trap handler routine The SP is incremented by an amount equivalent to 2 words Example reti Return from a trap handler routine ...

Page 156: ...rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is rotated as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 low order bits of the rs register The value in the most significant bit of the rd register is placed in the least significant bit 31 rd register after execution 0 2 Delayed inst...

Page 157: ...5 12 11 8 7 4 3 0 0 0 1 1 0 1 1 1 imm5 3 0 r d 0x37__ Flag IE C V Z N Mode Src Immediate unsigned Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is rotated as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 bit immediate imm5 The value in the most significant bit of the rd register is placed in the...

Page 158: ... rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is rotated as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 low order bits of the rs register The value in the least significant bit of the rd register is placed in the most significant bit 31 rd register after execution 0 2 Delayed ins...

Page 159: ... 15 12 11 8 7 4 3 0 0 0 1 1 0 0 1 1 imm5 3 0 r d 0x33__ Flag IE C V Z N Mode Src Immediate unsigned Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is rotated as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 bit immediate imm5 The value in the least significant bit of the rd register is placed in ...

Page 160: ...r direct rd r0 to r15 CLK One cycle Description 1 Standard sbc rd rs rd rd rs C The content of the rs register and C carry flag are subtracted from the rd register 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the d bit Example 1 sbc r0 r1 r0 r0 r1 C 2 Subtraction of 64 bit data data 1 r2 r1 data2 r4 r3 result...

Page 161: ...egister direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 low order bits of the rs register Data 0 is placed in the least significant bit of the rd register 31 rd register after execution 0 0 0 2 Delayed instruction This...

Page 162: ... left by 16 to 31 bits 15 12 11 8 7 4 3 0 0 0 1 0 1 1 1 1 imm5 3 0 r d 0x2F__ Flag IE C V Z N Mode Src Immediate unsigned Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 bit immediate imm5 Data 0 is placed in the least significant bit of ...

Page 163: ...gister direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 low order bits of the rs register Data 0 is placed in the least significant bit of the rd register 31 rd register after execution 0 0 0 2 Delayed instruction This ...

Page 164: ...t by 16 to 31 bits 15 12 11 8 7 4 3 0 0 0 1 0 0 1 1 1 imm5 3 0 r d 0x27__ Flag IE C V Z N Mode Src Immediate unsigned Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 bit immediate imm5 Data 0 is placed in the least significant bit of the ...

Page 165: ...nal interrupts NMI and debug exceptions are commonly used for canceling SLEEP mode The interrupt enable disable status set in the processor does not affect the cancellation of SLEEP mode even if an interrupt signal is used as the cancellation In other words interrupt signals are able to cancel SLEEP mode even if the IE flag in PSR or the interrupt enable bits in the interrupt controller depending ...

Page 166: ...r direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 low order bits of the rs register The sign bit is copied to the most significant bit of the rd register 31 rd register after execution 0 Sign bit S S S 2 Delayed instru...

Page 167: ... by 16 to 31 bits 15 12 11 8 7 4 3 0 0 0 1 0 1 0 1 1 imm5 3 0 r d 0x2B__ Flag IE C V Z N Mode Src Immediate unsigned Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 bit immediate imm5 The sign bit is copied to the most significant bit of ...

Page 168: ...egister direct rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 low order bits of the rs register Data 0 is placed in the most significant bit of the rd register 31 rd register after execution 0 0 0 2 Delayed instruction This ...

Page 169: ...ght by 16 to 31 bits 15 12 11 8 7 4 3 0 0 0 1 0 0 0 1 1 imm5 3 0 r d 0x23__ Flag IE C V Z N Mode Src Immediate unsigned Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted can be specified in the range of 0 to 31 by the 5 bit immediate imm5 Data 0 is placed in the most significant bit of the...

Page 170: ...the content of the rs register after being zero extended and the result is loaded into the rd register The content of the rs register is not altered 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 sub rd rs rd rs imm26 The 26 bit immediate imm26 is subtracted from the content of the rs register after being zero extended and the result is loaded into the rd register The content of the rs r...

Page 171: ...extended 2 Extension 1 ext imm13 imm19 18 6 sub rd imm6 rd rd imm19 imm6 imm19 5 0 The 19 bit immediate imm19 is subtracted from the rd register after being zero extended 3 Extension 2 ext imm13 imm32 31 19 ext imm13 imm32 18 6 sub rd imm6 rd rd imm32 imm6 imm32 5 0 The 32 bit immediate imm32 is subtracted from the rd register 4 Delayed instruction This instruction may be executed as a delayed ins...

Page 172: ...C V Z N Mode Src Immediate data unsigned Dst Register direct SP CLK One cycle Description 1 Standard Quadruples the 10 bit immediate imm10 and subtracts it from the stack pointer SP The imm10 is zero extended into 32 bits prior to the operation 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it directly after a branch instruction with the d bit Example su...

Page 173: ...irect rs r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard Swaps the byte order of the rs register high and low and loads the results to the rd register 8 7 16 15 24 23 Byte 0 Byte 1 Byte 2 Byte 3 0 rs register 31 8 7 16 15 24 23 Byte 3 Byte 2 Byte 1 Byte 0 0 rd register 31 2 Delayed instruction This instruction may be executed as a delayed instruction by writing it d...

Page 174: ...s r0 to r15 Dst Register direct rd r0 to r15 CLK One cycle Description 1 Standard Converts the 32 bit data in a general purpose register between big and little endians at halfword boundaries 8 7 16 15 24 23 Byte 0 Byte 1 Byte 2 Byte 3 0 rs register 31 8 7 16 15 24 23 Byte 1 Byte 0 Byte 3 Byte 2 0 rd register 31 2 Delayed instruction This instruction may be executed as a delayed instruction by writ...

Page 175: ... of the rs register and the zero extended 13 bit immediate imm13 are exclusively OR ed and the result is loaded into the rd register The content of the rs register is not altered 3 Extension 2 ext imm13 imm26 25 13 ext imm13 imm26 12 0 xor rd rs rd rs imm26 The content of the rs register and the zero extended 26 bit immediate imm26 are exclusively OR ed and the result is loaded into the rd registe...

Page 176: ...18 6 xor rd sign6 rd rd sign19 sign6 sign19 5 0 The content of the rd register and the sign extended 19 bit immediate sign19 are exclusively OR ed and the result is loaded into the rd register 3 Extension 2 ext imm13 sign32 31 19 ext imm13 sign32 18 6 xor rd sign6 rd rd sign32 sign6 sign32 5 0 The content of the rd register and the sign extended 32 bit immediate sign32 are exclusively OR ed and th...

Page 177: ...1 0 0 1 1 1 0 1 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 push rs pop rd pushs ss pops sd ld cf 15 Class op1 rs rd ss sd op2 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mnemonic Extension Delayed S 0 1 rs rd ss sd 2 1 2 alr 3 ahr 2 alr 3 ahr 3 Cycle Class 0 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0...

Page 178: ...5 4 3 2 1 0 Mnemonic Extension Delayed S rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rs rs rd rd rs rs rd rs rs rd rb rb rs imm5 3 0 rb rb rs imm5 3 0 rb rb rs imm5 3 0 rb rb rs imm5 3 0 rb rb rs imm5 3 0 rb rb rs imm5 3 0 rb rb rs rb rb rs 1 2 ext 2 1 1 1 2 ext 2 1 1 1 2 ext 2 1 1 1 2 ext 2 1 1 1 2 ext 2 1 1 1 2 ext 2 1 1 1 2 ext 2 1 1 2 ext 2 1 Cycle Class 2 0 0 0 0 1 1 1 1 0 0 1...

Page 179: ... 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 imm3 0 imm3 0 imm3 0 imm3 ld w sd rs ld b rd rs mlt h rd rs ld w rd ss 1 ld ub rd rs mltu h rd rs btst rb imm3 ld h rd rs mlt w rd rs bclr rb imm3 ld uh rd rs mltu w rd rs bset rb imm3 ld c rd imm4 bnot rb imm3 ld c imm4 rs adc rd rs sbc rd rs 15 Class op1 imm4 r s imm3 r s op2 14 13 12...

Page 180: ...rth RD DongSanHuan ChaoYang District Beijing CHINA Phone 86 10 6410 6655 Fax 86 10 6410 7320 SHANGHAI BRANCH 7F High Tech Bldg 900 Yishan Road Shanghai 200233 CHINA Phone 86 21 5423 5522 Fax 86 21 5423 5512 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Phone 852 2585 4600 Fax 852 2827 4346 Telex 65542 EPSCO HX EPSON Electronic Technology Development Shenzhen LTD 12 F Da...

Page 181: ...http www epsondevice com EPSON Electronic Devices Website SEMICONDUCTOR OPERATIONS DIVISION Issue July 2006 Printed in Japan A L Core Manual S1C33 Family C33 PE Document code 410755500 ...

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