6
FUNCTIONS
48
EPSON
S1C33 FAMILY C33 PE CORE MANUAL
6
.
2
Program Execution
Following initial reset, the processor loads the reset vector address into the PC and starts executing instructions
beginning with the address that was stored in the reset vector. As the instructions in the C
33
PE Core are fixed to
16
bits in length, the PC is incremented by
2
each time an instruction is fetched from the address indicated by the PC.
In this way, instructions are executed successively.
When a branch instruction is executed, the processor checks the PSR flags and whether the branch conditions have
been satisfied, and loads the jump address into the PC.
When an interrupt or exception occurs, the processor loads the address for the interrupt or exception handler routine
from the vector table into the PC.
The vector table is a table of vectors that begin with the reset vector. Following initial reset, the vector table is
located at the address
“
0
xC
00000
.
”
The exception vector table address can be determined by referencing the special
register TTBR. Alternatively, any desired address can be set for the exception vector table address in the software.
In this case, the addresses set in the TTBR must be aligned with the
1
K-byte boundary (TTBR[
9
:
0
] = fixed to
00
0000
0000
).
6
.
2
.
1
Instruction Fetch and Execution
Internally in the C
33
PE Core, instructions are processed in two pipelined stages, so that data transfer between
registers and general arithmetic/logic instructions can be executed in one clock cycle.
Pipelining speeds up instruction processing by executing one instruction while fetching another. In the
2
-stage
pipeline, each instruction is processed in two stages, with processing of instructions occurring in parallel, for faster
instruction execution.
Basic instruction stages
Instruction fetch / Instruction decode
Instruction execution / Memory access / Register write
Hereinafter, each stage is represented by the following symbols:
F (for Fetch): Instruction fetch, instruction decode
E (for Execute): Instruction execution, memory access, register write
Pipelined operation
F
E
F
E
F
E
Clock
PC
PC + 2
PC + 4
Figure
6
.
2
.
1
.
1
Pipelined Operation
Note
: The pipelined operation shown above uses the internal memory. If external memory or low-speed
external devices are used, one or more wait cycles may be inserted depending on the devices
used, with the E stage kept waiting.
