7
DETAILS OF INSTRUCTIONS
S1C33 FAMILY C33 PE CORE MANUAL
EPSON
115
ld.uh
%rd
, [
%rb
]
Function
Unsigned halfword data transfer
Standard)
rd
(
15
:
0
)
←
H[
rb
],
rd
(
31
:
16
)
←
0
Extension
1
)
rd
(
15
:
0
)
←
H[
rb
+
imm13
],
rd
(
31
:
16
)
←
0
Extension
2
)
rd
(
15
:
0
)
←
H[
rb
+
imm26
],
rd
(
31
:
16
)
←
0
Code
15
12
11
8
7
4
3
0
0
0
1
0
1
1
0
0
r b
r d
0x2C__
|
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Flag
IE C V Z N
– – – – –
|
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Mode
Src: Register indirect
%rb
=
%r0
to
%r15
Dst: Register direct
%rd
=
%r0
to
%r15
CLK
One cycle (two cycles when
ext
is used)
Description
(
1
) Standard
ld.uh
%rd
,[
%rb
]
; memory address =
rb
The halfword data in the specified memory location is transferred to the
rd
register after being
zero-extended to
32
bits. The
rb
register contains the memory address to be accessed.
(
2
) Extension
1
ext
imm13
ld.uh
%rd
,[
%rb
]
; memory address =
rb
+
imm13
The
e x t
instruction changes the addressing mode to register indirect addressing with
displacement. As a result, the content of the
rb
register with the
13
-bit immediate
imm13
added
comprises the memory address, the halfword data in which is transferred to the
rd
register. The
content of the
rb
register is not altered.
(
3
) Extension
2
ext
imm13
; =
imm26
(25:13)
ext
imm13
; =
imm26
(12:0)
ld.uh
%rd
,[
%rb
]
; memory address =
rb
+
imm26
The addressing mode changes to register indirect addressing with displacement, so the content
of the
rb
register with the
26
-bit immediate
imm26
added comprises the memory address, the
halfword data in which is transferred to the
rd
register. The content of the
rb
register is not
altered.
Caution
The
rb
register and the displacement must specify a halfword boundary address (least significant bit
=
0
). Specifying an odd address causes an address misaligned exception.
