Epson S1C17704, Technical Manual

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12 8-BIT TIMER (T8F)
12-14
EPSON
S1C17704 TECHNICAL MANUAL
0x4206: 8-bit Timer Control Register (T8F_CTL)
Register name Address Bit Name Function Setting Init. R/W Remarks
8-bit Timer
Control Register
(T8F_CTL) 0x4206
(16 bits)
D15–12 – reserved – – – 0 when being read.
D11–8 TFMD[3:0] Fine mode setup 0x0 to 0xf 0x0 R/W Set a number of times
to insert delay into a
16-underflow period.
D7–5 – reserved – – – 0 when being read.
D4 TRMD Count mode select 1 One shot 0 Repeat 0 R/W
D3–2 – reserved – – – 0 when being read.
D1 PRESER Timer reset 1 Reset 0 Ignored 0 W
D0 PRUN Timer run/stop control 1 Run 0 Stop 0 R/W
D[15:12] Reserved
D[11:8] TFMD[3:0]: Fine Mode Setup Bits
Corrects transfer rate error. (Default: 0x0)
The TFMD[3:0] bits specify a pattern of delays to be inserted in a 16-underflow period. The output
clock period will be prolonged for one count clock period per one delay inserted.
Table 12.10.3 Delay Patterns Specified with TFMD[3:0]
TFMD[3:0]
Underflow number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0x0 – – – – – – – – – – – – – – – –
0x1 – – – – – – – – – – – – – – – D
0x2 – – – – – – – D – – – – – – – D
0x3 – – – – – – – D – – – D – – – D
0x4 – – – D – – – D – – – D – – – D
0x5 – – – D – – – D – – – D – D – D
0x6 – – – D – D – D – – – D – D – D
0x7 – – – D – D – D – D – D – D – D
0x8 – D – D – D – D – D – D – D – D
0x9 – D – D – D – D – D – D – D D D
0xa – D – D – D D D – D – D – D D D
0xb – D – D – D D D – D D D – D D D
0xc – D D D – D D D – D D D – D D D
0xd – D D D – D D D – D D D D D D D
0xe – D D D D D D D – D D D D D D D
0xf – D D D D D D D D D D D D D D D
D: Indicates that a delay is inserted.
Count clock
Underflow signal (not corrected)
Underflow signal (corrected)
Output clock (not corrected)
Output clock (corrected)
Delayed
15 16
15 16
1
1
Figure 12.10.1 Delay Cycle Inserted in Fine Mode
D[7:5] Reserved