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16 STOPWATCH TIMER (SWT)

16-12

EPSON

S1C17704 TECHNICAL MANUAL

0x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG)

Register name Address

Bit

Name

Function

Setting

Init. R/W

Remarks

Stopwatch
Timer Interrupt
Flag Register
(SWT_IFLG)

0x5023

(8 bits)

D7–3

–

reserved

–

–

–

0 when being read.

D2

SIF1

1 Hz interrupt flag

1 Cause of

interrupt
occurred

0 Cause of

interrupt not
occurred

0

R/W Reset by writing 1.

D1

SIF10

10 Hz interrupt flag

0

R/W

D0

SIF100

100 Hz interrupt flag

0

R/W

This register indicates the interrupt cause occurrence status by the stopwatch timer 100 Hz, 10 Hz, and 1 Hz
signals. When a stopwatch timer interrupt occurs, read the interrupt flag in this register to determine the cause of
interrupt that has occurred (or frequency).
The SIF

∗

bits are the interrupt flags that correspond to 100 Hz, 10 Hz, and 1 Hz interrupts respectively, and are

set to 1 at the falling edge of the signals if the corresponding SIE

∗

bit (SWT_IMSK register) has been set to 1.

At this time, the stopwatch timer interrupt request signal is output to the ITC. The interrupt request signal sets the
stopwatch timer interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the ITC and
S1C17 Core settings.
The settings shown below are required to manage the cause-of-interrupt occurrence status using this register.
1. Set the stopwatch timer interrupt trigger mode in the ITC to level trigger.
2. After an interrupt occurs, reset the interrupt flag of the SWT module in the interrupt handler routine (this also

resets the interrupt flag in the ITC).

The SIF

∗

flags are reset by writing 1.

Note

: To avoid occurrence of unnecessary interrupts, be sure to reset the SIF

∗

flags before the

stopwatch timer interrupt is enabled using SIE

∗

.

D[7:3] Reserved

D2

SIF1: 1 Hz Interrupt Flag

This is the interrupt flag to indicate the 1 Hz interrupt cause occurrence status.

1 (R):

Cause of interrupt has occurred

0 (R):

No cause of interrupt has occurred (default)

1 (W):

Flag is reset

0 (W):

Has no effect

SIF1 is set to 1 at the falling edge of the 1 Hz signal only when SIE1 (D2/SWT_IMSK register) has
been set to 1.

D1

SIF10: 10 Hz Interrupt Flag

This is the interrupt flag to indicate the 10 Hz interrupt cause occurrence status.

1 (R):

Cause of interrupt has occurred

0 (R):

No cause of interrupt has occurred (default)

1 (W):

Flag is reset

0 (W):

Has no effect

SIF10 is set to 1 at the falling edge of the 10 Hz signal only when SIE10 (D1/SWT_IMSK register) has
been set to 1.

D0

SIF100: 100 Hz Interrupt Flag

This is the interrupt flag to indicate the 100 Hz interrupt cause occurrence status.

1 (R):

Cause of interrupt has occurred

0 (R):

No cause of interrupt has occurred (default)

1 (W):

Flag is reset

0 (W):

Has no effect

SIF100 is set to 1 at the falling edge of the 100 Hz signal only when SIE100 (D0/SWT_IMSK register)
has been set to 1.

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Summary of Contents for S1C17704

Page 1: ...TECHNICAL MANUAL S1C17704 CMOS 16 BIT SINGLE CHIP MICROCOMPUTER ...

Page 2: ...Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Ex...

Page 3: ...ble bit is set to disable interrupt 11 9 11 7 16 bit Timer Output Signal Numerical value modified Expression for I2C 22 3 22 3 2 Frame Signal Description deleted see Table 22 3 1 22 9 22 6 1 Turning Display On and Off Table 22 6 1 1 modified Description modified 22 15 22 8 Details of Control Registers Table 22 8 2 modified Description modified 26 7 26 6 3 External Clock Input AC Characteristics Ta...

Page 4: ... 99 Specs not fixed Specification Package D die form F QFP B BGA Model number Model name C microcomputer digital products Product classification S1 semiconductor Development tools S5U1 C 17000 H2 1 Packing specifications 00 standard packing Version 1 Version 1 Tool type Hx ICE Dx Evaluation board Ex ROM emulation board Mx Emulation memory for external ROM Tx A socket for mounting Cx Compiler packa...

Page 5: ... for the Flash Controller 3 4 0x5320 FLASHC Control Register MISC_FL 3 4 3 3 Internal RAM Area 3 5 3 3 1 Internal RAM 3 5 3 4 Display RAM Area 3 6 3 4 1 Display RAM 3 6 3 4 2 Access Control for the SRAM Controller 3 6 0x5321 SRAMC Control Register MISC_SR 3 6 3 5 Internal Peripheral Area 3 7 3 5 1 Internal Peripheral Area 1 0x4000 3 7 3 5 2 Internal Peripheral Area 2 0x5000 3 7 3 5 3 I O Map 3 8 3...

Page 6: ...el Setup Register 0 ITC_ELV0 6 17 0x4308 External Interrupt Level Setup Register 1 ITC_ELV1 6 18 0x430a External Interrupt Level Setup Register 2 ITC_ELV2 6 19 0x430c External Interrupt Level Setup Register 3 ITC_ELV3 6 20 0x430e Internal Interrupt Level Setup Register 0 ITC_ILV0 6 21 0x4310 Internal Interrupt Level Setup Register 1 ITC_ILV1 6 22 0x4312 Internal Interrupt Level Setup Register 2 IT...

Page 7: ... Direction Control Registers Px_IO 10 13 0x5203 0x5213 0x5223 0x5233 Px Port Pull up Control Registers Px_PU 10 14 0x5204 0x5214 0x5224 0x5234 Px Port Schmitt Trigger Control Registers Px_SM 10 15 0x5205 5215 Px Port Interrupt Mask Registers Px_IMSK 10 16 0x5206 5216 Px Port Interrupt Edge Select Registers Px_EDGE 10 17 0x5207 5217 Px Port Interrupt Flag Registers Px_IFLG 10 18 0x5208 P0 Port Chat...

Page 8: ...cautions 12 16 13 PWM Capture Timer T16E 13 1 13 1 Outline of the PWM Capture Timer 13 1 13 2 PWM Capture Timer Operating Mode 13 2 13 3 Setting Resetting the Counter Value 13 3 13 4 Setting Compare Data 13 4 13 5 PWM Capture Timer Run Stop Control 13 5 13 6 Controlling Clock Output 13 6 13 7 PWM Capture Timer Interrupt 13 9 13 8 Details of Control Registers 13 11 0x5300 PWM Timer Compare Data A R...

Page 9: ...atch Timer 16 4 16 5 Stopwatch Timer Run Stop Control 16 5 16 6 Stopwatch Timer Interrupt 16 6 16 7 Details of Control Registers 16 8 0x5020 Stopwatch Timer Control Register SWT_CTL 16 9 0x5021 Stopwatch Timer BCD Counter Register SWT_BCNT 16 10 0x5022 Stopwatch Timer Interrupt Mask Register SWT_IMSK 16 11 0x5023 Stopwatch Timer Interrupt Flag Register SWT_IFLG 16 12 16 8 Precautions 16 13 17 Watc...

Page 10: ... 20 2 I2C I O Pins 20 2 20 3 I2C Clock 20 3 20 4 Setting before Starting Data Transfer 20 4 20 5 Data Transmit Receive Control 20 5 20 6 I2C Interrupt 20 11 20 7 Details of Control Registers 20 13 0x4340 I2C Enable Register I2C_EN 20 14 0x4342 I2C Control Register I2C_CTL 20 15 0x4344 I2C Data Register I2C_DAT 20 17 0x4346 I2C Interrupt Control Register I2C_ICTL 20 19 21 Remote Controller REMC 21 ...

Page 11: ...t Flag Register LCD_IFLG 22 21 22 9 Precautions 22 22 23 Supply Voltage Detector SVD 23 1 23 1 Outline of the SVD module 23 1 23 2 Setting a Compare Voltage 23 2 23 3 Controlling the SVD Operation 23 3 23 4 SVD Interrupt 23 4 23 5 Details of Control Registers 23 6 0x5100 SVD Enable Register SVD_EN 23 7 0x5101 SVD Compare Voltage Register SVD_CMP 23 8 0x5102 SVD Detection Result Register SVD_RSLT 2...

Page 12: ...326 SPI AP 11 0x4340 0x4346 I2C AP 12 0x5000 0x5003 Clock Timer AP 13 0x5020 0x5023 Stopwatch Timer AP 14 0x5040 0x5041 Watchdog Timer AP 15 0x5060 0x5065 Oscillator AP 16 0x5080 0x5081 Clock Generator AP 17 0x50a0 0x50a6 LCD Driver AP 18 0x50c0 0x50c4 8 bit OSC1 Timer AP 19 0x5100 0x5104 SVD Circuit AP 20 0x5120 Power Generator AP 21 0x5200 0x52a3 P Port Port MUX AP 22 0x5300 0x530c PWM Capture T...

Page 13: ...lator for generating the 1 8 V internal voltage The S1C17704 is capable of high speed operation 8 2 MHz with low operating voltage 1 8 V Its 16 bit RISC processor executes one instruction in 1 clock cycles The S1C17704 also provides an on chip ICE function that allows on board erasing programming of the embedded Flash memory on board debugging and evaluating the program by connecting the S1C17704 ...

Page 14: ... CT 1 ch Stopwatch timer SWT 1 ch Watchdog timer WDT 1 ch 8 bit OSC1 timer T8OSC1 1 ch LCD driver 56 SEG 32 COM or 72 SEG 16 COM 1 5 bias Built in voltage booster Supply voltage detector SVD 13 programmable detection levels 1 8 V to 2 7 V Interrupts Reset NMI 16 programmable interrupts 8 levels Power supply voltage 1 8 V to 3 6 V for normal low power operation with the 1 8 V internal voltage 2 7 V...

Page 15: ... 32 bits RD 1 cycle WR 1 cycle 16 bits 1 5 cycles Interrupt system 8 16 bits 3 cycles DCLK DST2 DSIO P31 33 VDD VSS VD1 VD2 VC1 VC5 CA CG SEG0 55 71 COM0 31 15 OSC1 2 OSC3 4 FOUT1 P13 FOUT3 P30 EXCL3 P27 TOUT P26 REMI P04 REMO P05 P00 07 P10 17 P20 27 P30 33 TEST1 3 RESET EXCL0 2 P16 P07 P06 SIN SOUT SCLK P23 25 SDI SDO SPICLK P20 22 SDA SCL P14 15 Display RAM 576 bytes Reset circuit 8 bits 2 5 cy...

Page 16: ...UT P25 SCLK P26 TOUT P27 EXCL3 P30 FOUT3 DCLK P31 DST2 P32 DSIO P33 RESET TEST OSC2 OSC1 V D1 V SS OSC4 OSC3 V DD 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VC1 VC2 VC3 VC4 VC5 CA CB CC CD CE...

Page 17: ...8 N C N C COM31 SEG56 N C COM24 SEG63 COM23 SEG64 COM22 SEG65 DSIO P33 RESET TEST COM17 SEG70 COM18 SEG69 N C P24 SOUT P27 EXCL3 DST2 P32 N C N C N C P21 SDO P22 SPICLK P23 SIN TEST3 VD2 N C P00 P16 EXCL0 P17 SPISS CF CD CE P02 P01 P15 SCL VC1 VC3 CA P12 P05 REMO N C OSC4 VC2 P03 P11 P04 REMI VD1 OSC3 VDD VSS VDD VSS VSS P10 P13 FOUT1 P14 SDA P07 EXCL1 P06 EXCL2 N C N C P20 SDI P26 TOUT P25 SCLK N...

Page 18: ...EG39 SEG43 SEG48 SEG50 SEG54 SEG55 SEG20 SEG23 SEG27 SEG30 SEG33 SEG37 SEG40 SEG44 SEG47 SEG52 VC5 VC4 TEST2 CG CC COM16 SEG71 TEST1 COM21 SEG66 COM20 SEG67 COM19 SEG68 COM27 SEG60 COM25 SEG62 COM30 SEG57 COM28 SEG59 COM26 SEG61 COM29 SEG58 N C N C N C COM31 SEG56 COM24 SEG63 COM23 SEG64 COM22 SEG65 DSIO P33 RESET TEST COM17 SEG70 COM18 SEG69 P24 SOUT P27 EXCL3 DST2 P32 P21 SDO P22 SPICLK P23 SIN ...

Page 19: ... P01 P00 P02 SEG24 SEG31 SEG36 SEG40 SEG46 COM31 SEG56 SEG54 SEG55 SEG20 SEG23 SEG27 SEG30 SEG34 SEG38 SEG43 SEG47 SEG50 SEG52 VC5 COM18 SEG69 CB CC VC3 VD2 CF COM16 SEG71 COM17 SEG70 COM19 SEG68 COM26 SEG61 COM29 SEG58 COM27 SEG60 COM25 SEG62 COM30 SEG57 COM22 SEG65 COM24 SEG63 COM21 SEG66 COM23 SEG64 COM20 SEG67 OSC1 RESET OSC4 CG DCLK P31 P24 SOUT VDD TEST DST2 P32 OSC2 P22 SPICLK P23 SIN CE P0...

Page 20: ...supply pin GND 77 J11 L12 K12 VD1 Internal logic and oscillator circuit constant voltage circuit output pin 78 H11 K13 J12 OSC1 I I OSC1 oscillator input pin 79 H10 K12 J11 OSC2 O O OSC1 oscillator output pin 80 C4 K11 H8 TEST PFBGA VFBGA7 VDD TEST VFBGA10 I I Pull UP Test pin fixed at High in normal operation 81 B4 J12 H11 RESET I I Pull UP Initial set input pin 82 A4 J13 H12 DSIO P33 I O I Pull ...

Page 21: ... GND 109 A8 B12 A11 P02 I O I Pull UP Input output port pin with interrupt 110 B8 A12 B10 P01 I O I Pull UP Input output port pin with interrupt 111 A7 B11 A10 P00 I O I Pull UP Input output port pin with interrupt 112 to 127 10 11 COM0 to 15 O O L LCD common output pin 128 to 144 12 13 SEG0 to 16 O O L LCD segment output pin 1 SEG17 to SEG55 VFBGA7 B1 C2 D4 C1 D3 D2 D1 E4 E3 E2 E1 F3 F2 F1 F4 G2 ...

Page 22: ...1 OVERVIEW 1 10 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 23: ...set Code length 16 bit fixed length Number of instructions 111 basic instructions 184 including variations Execution cycle Main instructions executed in one cycles Extended immediate instructions Immediate extended up to 24 bits Compact and fast instruction set optimized for development in C language Register set Eight 24 bit general purpose registers Two 24 bit special registers One 8 bit special...

Page 24: ... The S1C17 Core contains eight general purpose registers and three special registers R4 R5 R6 R7 R3 R2 R1 R0 bit 23 bit 0 General purpose registers PC bit 23 7 6 5 4 3 2 1 0 bit 0 PSR SP Special registers IL 2 0 7 6 5 IE 4 C 3 V 2 Z 1 N 0 Figure 2 2 1 Registers ...

Page 25: ...r zero extended ld rd rs General purpose register 16 bits general purpose register rd sign7 Immediate general purpose register sign extended rd rb Memory 16 bits general purpose register Memory address post increment post decrement and pre decrement functions can be used rd rb rd rb rd rb rd sp imm7 Stack 16 bits general purpose register rd imm7 Memory 16 bits general purpose register rb rs Genera...

Page 26: ...4 bit subtraction of SP and immediate sbc rd rs 16 bit subtraction with carry between general purpose registers Supports conditional execution c executed if C 1 nc executed if C 0 sbc c sbc nc sbc rd imm7 16 bit subtraction of general purpose register and immediate with carry cmp rd rs 16 bit comparison between general purpose registers Supports conditional execution c executed if C 1 nc executed ...

Page 27: ...nching possible jrle jrle d sign7 PC relative conditional jump Branch condition Z N V Delayed branching possible jrugt jrugt d sign7 PC relative conditional jump Branch condition Z C Delayed branching possible jruge jruge d sign7 PC relative conditional jump Branch condition C Delayed branching possible jrult jrult d sign7 PC relative conditional jump Branch condition C Delayed branching possible ...

Page 28: ...ssed by general purpose register with address post incremented rb Memory addressed by general purpose register with address post decremented rb Memory addressed by general purpose register with address pre decremented sp Stack pointer sp sp imm7 Stack sp Stack with address post incremented sp Stack with address post decremented sp Stack with address pre decremented imm3 imm5 imm7 imm13 Unsigned im...

Page 29: ...nal 1 Hz timer signal 7 0x07 0x801c Clock timer interrupt 32 Hz timer signal 8 Hz timer signal 2 Hz timer signal 1 Hz timer signal 8 0x08 0x8020 8 bit OSC1 timer interrupt Compare match 9 0x09 0x8024 SVD interrupt Low supply voltage detected 10 0x0a 0x8028 LCD interrupt Frame signal 11 0x0b 0x802c PWM capture timer interrupt Compare match A Compare match B 12 0x0c 0x8030 8 bit timer interrupt Time...

Page 30: ...ion software to identify CPU core type 0xffff84 Processor ID Register IDIR Register name Address Bit Name Function Setting Init R W Remarks Processor ID Register IDIR 0xffff84 8 bits D7 0 IDIR 7 0 Processor ID 0x10 S1C17 Core 0x10 0x10 R This is a read only register that contains the ID code to represent a processor model The S1C17 Core s ID code is 0x10 ...

Page 31: ...x403f 0x4000 0x401f reserved I2C SPI Interrupt controller reserved 16 bit timer Ch 2 16 bit timer Ch 1 16 bit timer Ch 0 8 bit timer reserved UART reserved Prescaler reserved Debug RAM area 64 bytes Internal RAM area 4K bytes 1 cycle Device size 32 bits 0x5360 0x5fff 0x5340 0x535f 0x5320 0x533f 0x5300 0x531f 0x52c0 0x52ff 0x52a0 0x52bf 0x5280 0x529f 0x5200 0x527f 0x5140 0x51ff 0x5120 0x513f 0x5100...

Page 32: ... when the CPU accesses the display RAM area eight bit device set to two access cycles by a 16 bit read or write instruction 2 cycles 2 bus accesses 4 CCLK cycles 3 1 1 Restrictions on Access Size The modules shown below have a restriction on the access size Appropriate instructions should be used in programming Flash memory The Flash memory allows only 16 bit write instructions for programming Rea...

Page 33: ...x09000 0x09fff 1 0x11000 0x11fff 9 0x08000 0x08fff 0 0x10000 0x10fff 8 Note The 32 bits 0x17ffc 0x17fff at the end of Sector 15 are reserved for the system as the protect bits Do not program this area with data other than protect settings 3 2 3 Protect Bits In order to protect the memory contents the Flash memory provides two protection features write protection and data read protection that can b...

Page 34: ...ting Init R W Remarks FLASHC Control Register MISC_FL 0x5320 8 bits D7 3 reserved 0 when being read D2 0 FLCYC 2 0 FLASHC read access cycle FLCYC 2 0 Read cycle 0x3 R W 0x7 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 cycles 5 cycles 4 cycles 3 cycles 2 cycles D 7 3 Reserved D 2 0 FLCYC 2 0 FLASHC Read Access Cycle Setup Bits Sets the number of read access cycles for the Flash controller Table 3 2 4 1 Setti...

Page 35: ...ding and writing and allows high speed execution of the instruction codes copied into it as well as storing variables and other data Note The 64 byte area at the end of the RAM 0xfc0 0xfff is reserved for the on chip debugger When using the debug functions under application development do not access this area from the application program This area can be used for applications of mass produced devi...

Page 36: ...es for the SRAM controller In order to read write data from to the display RAM properly set the appropriate number of access cycles according to the CCLK frequency using the SRCYC 1 0 bits D 1 0 MISC_SR register 0x5321 SRAMC Control Register MISC_SR Register name Address Bit Name Function Setting Init R W Remarks SRAMC Control Register MISC_SR 0x5321 8 bits D7 2 reserved 0 when being read D1 0 SRC...

Page 37: ...vice 16 bit timers T16 16 bit device Interrupt controller ITC 16 bit device SPI SPI 16 bit device I2C I2C 16 bit device 3 5 2 Internal Peripheral Area 2 0x5000 The internal peripheral area 2 beginning with address 0x5000 contains the I O memory for the peripheral functions listed below and this area can be accessed in three cycles Clock timer CT 8 bit device Stopwatch timer SWT 8 bit device Watchd...

Page 38: ... timer Ch 2 16 bit device 0x4260 T16_CLK2 16 bit Timer Ch 2 Input Clock Select Register Selects a prescaler output clock 0x4262 T16_TR2 16 bit Timer Ch 2 Reload Data Register Sets reload data 0x4264 T16_TC2 16 bit Timer Ch 2 Counter Data Register Counter data 0x4266 T16_CTL2 16 bit Timer Ch 2 Control Register Sets the timer mode and starts stops the timer 0x4268 0x427f Reserved Interrupt controlle...

Page 39: ...upt occurrence status 0x50a7 0x50bf Reserved 8 bit OSC1 timer 8 bit device 0x50c0 T8OSC1_CTL 8 bit OSC1 Timer Control Register Sets the timer mode and starts stops the timer 0x50c1 T8OSC1_CNT 8 bit OSC1 Timer Counter Data Register Counter data 0x50c2 T8OSC1_CMP 8 bit OSC1 Timer Compare Data Register Sets compare data 0x50c3 T8OSC1_IMSK 8 bit OSC1 Timer Interrupt Mask Register Enables disables inte...

Page 40: ...er 16 bit device 0x5300 T16E_CA PWM Timer Compare Data A Register Sets compare data A 0x5302 T16E_CB PWM Timer Compare Data B Register Sets compare data B 0x5304 T16E_TC PWM Timer Counter Data Register Counter data 0x5306 T16E_CTL PWM Timer Control Register Sets the timer mode and starts stops the timer 0x5308 T16E_CLK PWM Timer Input Clock Select Register Selects a prescaler output clock 0x530a T...

Page 41: ...6 1 I O Map S1C17 Core I O Area Peripheral Address Register name Function S1C17 Core I O 0xffff80 TTBR Vector Table Base Register Indicates the vector table base address 0xffff84 IDIR Processor ID Register Indicates the processor ID 0xffff90 DBRAM Debug RAM Base Register Indicates the debug RAM base address See Section 2 4 Vector Table and Section 2 5 Processor Information for TTBR and IDIR respec...

Page 42: ...3 MEMORY MAP BUS CONTROL 3 12 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 43: ...of the S1C17704 is as follows For normal operation 1 8 V to 3 6 V For Flash programming 2 7 V to 3 6 V Supply a voltage within the range to the VDD pins with the VSS pins as the GND level The S1C17704 provides two VDD pins and three VSS pins Do not leave any pins open and be sure to connect them to power source and GND ...

Page 44: ...drive external circuits Internal logic voltage regulator The internal logic voltage regulator generates the VD1 operating voltage for the internal logic circuits and oscillators The VD1 voltage value can be switched in the program set it to 1 8 V for normal operation and 2 5 V for Flash programming Power voltage booster The power voltage booster generates the VD2 operating voltage for the LCD syst...

Page 45: ... within the range from 1 8 V to 2 5 V use the power voltage booster to generate double the VDD voltage and drive the LCD system voltage regulator with the VD2 output voltage Set the PBON bit D0 LCD_PWR register to 1 to turn the power voltage booster on In addition set the VDSEL bit D1 LCD_PWR register to 1 to drive the LCD system voltage regulator with the VD2 voltage output from the power voltage...

Page 46: ...on Control bits Operating mode VDD LCD driver VD1MD PBON VDSEL DSPC 1 0 Normal operation 1 8 to 2 5 V Used 0 1 1 Other than 0x0 2 5 to 3 6 V Used 0 0 0 Other than 0x0 1 8 to 3 6 V Not used 0 0 0 0x0 Flash erase program 1 8 to 2 7 V use prohibited 2 7 to 3 6 V Used 1 0 0 Other than 0x0 2 7 to 3 6 V Not used 1 0 0 0x0 For the DSPC 1 0 settings see 0x50a0 LCD Display Control Register LCD_DCTL in Sect...

Page 47: ...ut Use the heavy load protection function when a heavy load such as a lamp or buzzer is driven with a port output HVLD VD1 Heavy Load Protection Mode Bit in the VD1 Control VD1_CTL Register D4 0x5120 The LCD system voltage regulator enters heavy load protection mode by writing 1 to the LHVLD bit D4 LCD_VREG register and it ensures stable VC1 VC5 outputs Use the heavy load protection function when ...

Page 48: ...s the VD1 voltage and heavy load protection mode 0x50a3 LCD_VREG LCD Voltage Regulator Control Register Controls the LCD drive voltage regulator 0x50a4 LCD_PWR LCD Power Voltage Booster Control Register Controls the LCD voltage booster The following describes each power control register These are all 8 bit registers Note When setting the registers be sure to write a 0 and not a 1 for all reserved ...

Page 49: ... regulator enters heavy load protection mode by writing 1 to HVLD and it ensures stable VD1 output Use the heavy load protection function when a heavy load such as a lamp or buzzer is driven with a port output Current consumption increases in heavy load protection mode therefore do not set if unnecessary D 3 1 Reserved D0 VD1MD Flash Erase Program Mode Bit Selects the VD1 internal operating voltag...

Page 50: ...en being read D 7 5 Reserved D4 LHVLD LCD Heavy Load Protection Mode Bit Sets the LCD system voltage regulator into heavy load protection mode 1 R W Heavy load protection On 0 R W Heavy load protection Off default The LCD system voltage regulator enters heavy load protection mode by writing 1 to LHVLD and it ensures stable VC1 VC5 outputs Use the heavy load protection function when the LCD display...

Page 51: ...e power supply voltage VDD is 2 5 V or more write 0 to VDSEL to drive the LCD system voltage regulator with VDD In this case the power voltage booster should be turned off to reduce current consumption D0 PBON Power Voltage Booster Control Bit Controls the power voltage booster 1 R W On 0 R W Off default When the power supply voltage VDD is within the range from 1 8 V to 2 5 V write 1 to PBON to t...

Page 52: ...the operating mode is switched the internal operating voltage requires 5 ms max to stabilize Flash memory programming should be started after the stabilization time has elapsed When the power voltage booster is turned on the VD2 output voltage requires about 1 ms to stabilize Do not switch the power source for the LCD system voltage regulator to VD2 until the stabilization time has elapsed Current...

Page 53: ...ial Reset Circuit The CPU and peripheral circuits are initialized by the active signal from an initial reset source When the reset signal is negated the CPU starts reset handling The reset handling reads the reset vector reset handler start address from the beginning of the vector table and starts executing the program initial routine beginning with the read address 5 1 1 RESET Pin By setting the ...

Page 54: ...y set to low level while the application program is running The P0 port key entry reset function cannot be used for power on reset as it must be enabled with software The P0 port key entry reset function cannot be used in SLEEP mode 5 1 3 Resetting by the Watchdog Timer The S1C17704 has a built in watchdog timer to detect runaway of the CPU The watchdog timer overflows if it is not reset with soft...

Page 55: ...OSC3 clock after reset state is canceled fOSC3 OSC3 clock frequency Note The oscillation stabilization time described in this section does not include oscillation start time Therefore the time interval until the CPU starts executing instructions after power is turned on or SLEEP mode is canceled may be longer than that indicated in the figure below Boot vector Oscillation stabilization waiting tim...

Page 56: ...e beginning of the vector table is loaded by the reset handling The internal RAM and display memory should be initialized with software as they are not initialized at initial reset The internal peripheral modules are initialized to the default values except some undefined registers Change the settings with software if necessary For the default values set at initial reset see the list of I O regist...

Page 57: ...ion program to set the interrupt level priority of each interrupt system that determines the order of handling when two or more interrupts occur at the same time in the list above represents the number of interrupt causes supported in each interrupt system Use the control register in the peripheral module to select the interrupt causes for generating an interrupt request For more information on in...

Page 58: ...0 Hz timer signal 10 Hz timer signal 1 Hz timer signal 7 0x07 0x801c Clock timer interrupt 32 Hz timer signal 8 Hz timer signal 2 Hz timer signal 1 Hz timer signal 8 0x08 0x8020 8 bit OSC1 timer interrupt Compare match 9 0x09 0x8024 SVD interrupt Low supply voltage detected 10 0x0a 0x8028 LCD interrupt Frame signal 11 0x0b 0x802c PWM capture timer interrupt Compare match A Compare match B 12 0x0c ...

Page 59: ...mer interrupt timer underflow IIFT0 D8 ITC_IFLG register 13 16 bit timer Ch 0 interrupt timer underflow IIFT1 D9 ITC_IFLG register 14 16 bit timer Ch 1 interrupt timer underflow IIFT2 D10 ITC_IFLG register 15 16 bit timer Ch 2 interrupt timer underflow IIFT3 D11 ITC_IFLG register 16 UART interrupt transmit buffer empty receive buffer full receive error IIFT4 D12 ITC_IFLG register 17 Remote control...

Page 60: ...C_EN register 9 SVD interrupt EIFT5 D5 ITC_IFLG register EIEN5 D5 ITC_EN register 10 LCD interrupt EIFT6 D6 ITC_IFLG register EIEN6 D6 ITC_EN register 11 PWM capture timer interrupt EIFT7 D7 ITC_IFLG register EIEN7 D7 ITC_EN register 12 8 bit timer interrupt IIFT0 D8 ITC_IFLG register IIEN0 D8 ITC_EN register 13 16 bit timer Ch 0 interrupt IIFT1 D9 ITC_IFLG register IIEN1 D9 ITC_EN register 14 16 ...

Page 61: ...IILV5 2 0 D 10 8 ITC_ILV2 register 0x4312 18 SPI interrupt IILV6 2 0 D 2 0 ITC_ILV3 register 0x4314 19 I2 C interrupt IILV7 2 0 D 10 8 ITC_ILV3 register 0x4314 The highest interrupt level is 7 and the lowest is 0 The set interrupt level is sent to the S1C17 Core at the same time the ITC sends an interrupt request and is used by the S1C17 Core to disable subsequent interrupts that have the same or ...

Page 62: ... ITC_ELV2 register 0x430a LCD interrupt EITG6 D4 ITC_ELV3 register 0x430c PWM capture timer interrupt EITG7 D12 ITC_ELV3 register 0x430c The interrupt source modules that set the IIFT flags output only a pulse signal to the ITC to request an interrupt therefore no trigger mode select bit is provided Pulse trigger mode In pulse trigger mode the ITC samples interrupt signals at the rising edge of th...

Page 63: ...Core accepts the interrupt request and must reset the interrupt signal after that pclk Interrupt signal from an interrupt source Interrupt flag in ITC The interrupt source negates the interrupt signal Figure 6 3 5 2 Level Trigger Mode Note The following S1C17704 interrupts use level trigger mode The interrupt handler routine must reset write 1 to the interrupt flag provided in the peripheral modul...

Page 64: ...s allowed to signal an interrupt request to the S1C17 Core The other interrupts with lower priorities are kept pending until the above conditions are met The S1C17 Core keeps sampling interrupt requests every cycle When the S1C17 Core accepts an interrupt request it enters interrupt processing after completing execution of the instruction that was being executed The following lists the contents ex...

Page 65: ...r generates a non maskable interrupt NMI The vector number of NMI is 2 with the vector address set to the vector table s starting address 8 bytes This interrupt is prioritized over other interrupts and is unconditionally accepted by the S1C17 Core For how to generate NMI see Chapter 17 Watchdog Timer WDT ...

Page 66: ...nstructions allowing the software to generate any interrupts The operand imm5 specifies a vector number 0 31 in the vector table In addition to this the intl instruction has the operand imm3 to specify the interrupt level 0 7 to be set to the IL field in the PSR The processor performs the same interrupt handling as that of the hardware interrupt ...

Page 67: ...Interrupt Causes A cause of interrupt clears HALT or SLEEP mode to start up the CPU The program execution sequence whether it branches to the interrupt handler routine after the CPU starts up depends on the clock status in HALT SLEEP mode See C 1 Power Saving by Clock Control in Appendix C for details ...

Page 68: ...2 External Interrupt Level Setup Register 2 Sets the 8 bit OSC1 timer and SVD interrupt levels and trigger modes 0x430c ITC_ELV3 External Interrupt Level Setup Register 3 Sets the LCD and PWM capture timer interrupt levels and trigger modes 0x430e ITC_ILV0 Internal Interrupt Level Setup Register 0 Sets the 8 bit timer and 16 bit timer Ch 0 interrupt levels 0x4310 ITC_ILV1 Internal Interrupt Level ...

Page 69: ...g is reset 0 W Has no effect The interrupt flag is set to 1 when a cause of interrupt occurs in each peripheral circuit If the following conditions are met at this time an interrupt is generated to the S1C17 Core 1 The corresponding bit of the Interrupt Enable Register is set to 1 2 No other interrupt request of higher priority has occurred 3 The IE bit of the PSR is set to 1 interrupt enabled 4 T...

Page 70: ...T0 D0 P0 port interrupt P00 P07 port inputs EIFT1 D1 P1 port interrupt P10 P17 port inputs EIFT2 D2 Stopwatch timer interrupt 100 Hz 10 Hz 1 Hz signal EIFT3 D3 Clock timer interrupt 32 Hz 8 Hz 2 Hz 1 Hz signal EIFT4 D4 8 bit OSC1 timer interrupt compare match EIFT5 D5 SVD interrupt low supply voltage detection EIFT6 D6 LCD interrupt frame signal EIFT7 D7 PWM capture timer interrupt compare A compa...

Page 71: ... 1 R W Interrupt enabled 0 R W Interrupt disabled default Interrupts are enabled when the corresponding interrupt enable bit is set to 1 and are disabled when the bit is set to 0 Table 6 7 4 Causes of Hardware Interrupt and Interrupt Enable Bits Interrupt enable bits Cause of hardware interrupt EIEN0 D0 P0 port interrupt P00 P07 port inputs EIEN1 D1 P1 port interrupt P10 P17 port inputs EIEN2 D2 S...

Page 72: ...e Function Setting Init R W Remarks ITC Control Register ITC_CTL 0x4304 16 bits D15 1 reserved 0 when being read D0 ITEN ITC enable 1 Enable 0 Disable 0 R W D 15 1 Reserved D0 ITEN ITC Enable Bit Enables the ITC to control interrupt generation 1 R W Enable 0 R W Disable default Before the ITC can be used this bit must be set to 1 ...

Page 73: ...pt flag EIFTx Therefore the interrupt source module must hold the interrupt signal to high until the S1C17 Core accepts the interrupt request and must reset the interrupt signal after that D11 Reserved D 10 8 EILV1 2 0 P1 Port Interrupt Level Bits Sets the interrupt level 0 to 7 of the P1 port interrupt Default 0 If the level is set below the IL value of the PSR the S1C17 Core does not accept the ...

Page 74: ...Selects the trigger mode of the clock timer interrupt Set this bit 1 in the S1C17704 1 R W Level trigger mode 0 R W Pulse trigger mode default See the description of EITG1 D12 in the ITC_ELV0 register 0x4306 D11 Reserved D 10 8 EILV3 2 0 Clock Timer Interrupt Level Bits Sets the interrupt level 0 to 7 of the clock timer interrupt Default 0 See the description of EILV1 2 0 D 10 8 in the ITC_ELV0 re...

Page 75: ...elect Bit Selects the trigger mode of the SVD interrupt Set this bit 1 in the S1C17704 1 R W Level trigger mode 0 R W Pulse trigger mode default See the description of EITG1 D12 in the ITC_ELV0 register 0x4306 D11 Reserved D 10 8 EILV5 2 0 SVD Interrupt Level Bits Sets the interrupt level 0 to 7 of the SVD interrupt Default 0 See the description of EILV1 2 0 D 10 8 in the ITC_ELV0 register 0x4306 ...

Page 76: ...ger Mode Select Bit Selects the trigger mode of the PWM capture timer interrupt Set this bit 1 in the S1C17704 1 R W Level trigger mode 0 R W Pulse trigger mode default See the description of EITG1 D12 in the ITC_ELV0 register 0x4306 D11 Reserved D 10 8 EILV7 2 0 PWM Capture Timer Interrupt Level Bits Sets the interrupt level 0 to 7 of the PWM capture timer interrupt Default 0 See the description ...

Page 77: ...ccur simultaneously If two or more causes of interrupt that have been enabled by the interrupt enable register occur simultaneously the cause of interrupt whose Interrupt Level Setup Register contains the highest value is allowed by the ITC to send an interrupt request to the S1C17 Core If two or more causes of interrupt that have the same interrupt level occur the interrupt with the smallest vect...

Page 78: ... 0x0 R W D7 3 reserved 0 when being read D2 0 IILV2 2 0 T16 Ch 1 interrupt level 0 to 7 0x0 R W D 15 11 Reserved D 10 8 IILV3 2 0 16 bit Timer Ch 2 Interrupt Level Bits Sets the interrupt level 0 to 7 of the 16 bit timer Ch 2 interrupt Default 0 See the description of IILV1 2 0 D 10 8 in the ITC_ILV0 register 0x430e D 7 3 Reserved D 2 0 IILV2 2 0 16 bit Timer Ch 1 Interrupt Level Bits Sets the int...

Page 79: ... level 0 to 7 0x0 R W D7 3 reserved 0 when being read D2 0 IILV4 2 0 UART interrupt level 0 to 7 0x0 R W D 15 11 Reserved D 10 8 IILV5 2 0 Remote Controller Interrupt Level Bits Sets the interrupt level 0 to 7 of the remote controller interrupt Default 0 See the description of IILV1 2 0 D 10 8 in the ITC_ILV0 register 0x430e D 7 3 Reserved D 2 0 IILV4 2 0 UART Interrupt Level Bits Sets the interru...

Page 80: ... I2 C interrupt level 0 to 7 0x0 R W D7 3 reserved 0 when being read D2 0 IILV6 2 0 SPI interrupt level 0 to 7 0x0 R W D 15 11 Reserved D 10 8 IILV7 2 0 I2C Interrupt Level Bits Sets the interrupt level 0 to 7 of the I2C interrupt Default 0 See the description of IILV1 2 0 D 10 8 in the ITC_ILV0 register 0x430e D 7 3 Reserved D 2 0 IILV6 2 0 SPI Interrupt Level Bits Sets the interrupt level 0 to 7...

Page 81: ...e following S1C17704 interrupts use level trigger mode P0 port interrupt P1 port interrupt Stopwatch timer interrupt Clock timer interrupt 8 bit OSC1 timer interrupt SVD interrupt LCD interrupt PWM capture timer interrupt Set all EITGx bits in the ITC_ELVx register 0x4306 to 0x430c to 1 level trigger mode Furthermore the interrupt handler routine must reset write 1 to the interrupt flag provided i...

Page 82: ...6 INTERRUPT CONTROLLER ITC 6 26 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 83: ...SC3 oscillator 8 2 MHz OSC1 oscillator 32 768 kHz Divider 1 1 1 4 Wait circuit for wakeup Clock gear 1 1 1 8 Gate S1C17 Core BCLK Internal bus RAM Flash ITC T16 T8F UART SPI I2C T16E P MISC VD1 SVD REMC Control registers CT SWT WDT T8OSC1 LCD PCLK CLK_256Hz LCLK Gate OSC3 OSC4 Clock source select System clock FOUT3 FOUT1 output circuit FOUT1 Noise filter RESET OSC1 OSC2 SLEEP On Off control Gear s...

Page 84: ...Figure 7 2 1 OSC3 Oscillator Circuit When the crystal ceramic oscillator model is selected connect a crystal X tal3 or ceramic resonator Ceramic and a feedback resistor Rf between the OSC3 and OSC4 pins and two capacitors CG3 CD3 to the OSC3 and OSC4 pins and VSS When the CR oscillator model is selected connect only a resistor RCR3 between the OSC3 and OSC4 pins Controlling the OSC3 oscillation on...

Page 85: ... can be selected from four kinds of number of clock cycles using OSC3WT 1 0 D 5 4 OSC_CTL register OSC3WT 1 0 OSC3 Wait Cycle Select Bits in the Oscillation Control OSC_CTL Register D 5 4 0x5061 Table 7 2 2 Setting Stable Oscillation Wait Time OSC3WT 1 0 Stable oscillation wait time 0x3 128 cycles 0x2 256 cycles 0x1 512 cycles 0x0 1024 cycles Default 0x0 The stable oscillation wait time is set to ...

Page 86: ...d a trimmer capacitor CG1 0 25 pF between the OSC1 and VSS Controlling the OSC1 oscillation on and off Setting OSC1EN D1 OSC_CTL register to 0 causes the OSC1 oscillator circuit to stop setting it to 1 causes the OSC1 oscillator circuit to start oscillating Also the OSC1 oscillator circuit stops when the S1C17 Core enters SLEEP mode OSC1EN OSC1 Enable Bit in the Oscillation Control OSC_CTL Registe...

Page 87: ...SC1 clock cycle period The OSC3 oscillation cannot be stopped before switching the system clock to OSC1 OSC1 to OSC3 1 Set a stable oscillation wait time see Table 7 2 2 longer than the OSC3 oscillation start time using OSC3WT 1 0 D 5 4 OSC_CTL register This control is not necessary if it has been set already OSC3WT 1 0 OSC3 Wait Cycle Select Bits in the Oscillation Control OSC_CTL Register D 5 4 ...

Page 88: ...ted as the source clock it is not necessary to select a division ratio The OSC1 clock Typ 32 768 kHz is sent directly to the LCD driver When the OSC3 clock is used When OSC3 is selected as the source clock select a division ratio using LCKDV 2 0 D 4 2 OSC_LCLK register LCKDV 2 0 LCD Clock Division Ratio Select Bits in the LCD Clock Setup OSC_LCLK Register D 4 2 0x5063 Table 7 5 1 Selecting Divisio...

Page 89: ...SC1 register T8O1CK 2 0 T8OSC1 Clock Division Ratio Select Bits in the T8OSC1 Clock Control OSC_T8OSC1 Register D 3 1 0x5065 Table 7 6 1 Selecting Division Ratio for Generating T8OSC1 Clock T8O1CK 2 0 Division ratio 0x7 0x6 Reserved 0x5 OSC1 1 32 0x4 OSC1 1 16 0x3 OSC1 1 8 0x2 OSC1 1 4 0x1 OSC1 1 2 0x0 OSC1 1 1 Default 0x0 Controlling the clock supply Use T8O1CE D0 OSC_T8OSC1 register to control t...

Page 90: ...ster D0 0x52a3 Selecting the FOUT3 clock frequency The output clock frequency can be selected from three kinds Select an OSC3 clock division ratio using FOUT3D 1 0 D 3 2 OSC_FOUT register to set up the clock frequency FOUT3D 1 0 FOUT3 Clock Division Ratio Select Bits in the FOUT Control OSC_FOUT Register D 3 2 0x5064 Table 7 7 1 Selecting Division Ratio for Generating FOUT3 Clock FOUT3D 1 0 Divisi...

Page 91: ...n the P1 Port Function Select P1_PMUX Register D3 0x52a1 Controlling the clock output Use FOUT1E D0 OSC_FOUT register to control the clock output When FOUT1E is set to 1 the FOUT1 clock is output from the FOUT1 pin and the output is disabled when FOUT1E is set to 0 FOUT1E FOUT1 Output Enable Bit in the FOUT Control OSC_FOUT Register D0 0x5064 FOUT1E FOUT1 output P13 0 0 1 Figure 7 7 3 FOUT1 Output...

Page 92: ...passed when RSTFE 0 NMI input noise filter Noise will be removed when NMIFE D0 OSC_NFEN register 1 the filter is bypassed when NMIFE 0 RSTFE Reset Noise Filter Enable Bit in the Noise Filter Enable OSC_NFEN Register D1 0x5062 NMIFE NMI Noise Filter Enable Bit in the Noise Filter Enable OSC_NFEN Register D0 0x5062 The noise filter operates with a divide by 8 system clock OSC3 or OSC1 clock When it ...

Page 93: ...ls oscillation 0x5062 OSC_NFEN Noise Filter Enable Register Enables disables noise filters 0x5063 OSC_LCLK LCD Clock Setup Register Sets up the LCD clock 0x5064 OSC_FOUT FOUT Control Register Controls clock output 0x5065 OSC_T8OSC1 T8OSC1 Clock Control Register Sets up the 8 bit OSC1 timer clock The following describes each OSC module control register These are all 8 bit registers Note When settin...

Page 94: ...3 0 R W D 7 1 Reserved D0 CLKSRC System Clock Source Select Bit Selects the system clock source 1 R W OSC1 0 R W OSC3 default Select OSC3 for normal high speed operation When the OSC3 clock is not necessary select OSC1 as the system clock and stop OSC3 oscillation to reduce current consumption Note When the system clock is switched from OSC3 to OSC1 immediately after the OSC1 oscillator starts osc...

Page 95: ...Wait Time OSC3WT 1 0 Stable oscillation wait time 0x3 128 cycles 0x2 256 cycles 0x1 512 cycles 0x0 1024 cycles Default 0x0 At initial reset the oscillation stabilization wait time is set to 1024 cycles OSC3 clock The CPU does not start operating until the set time has elapsed after the reset state is canceled Note The oscillation start time will vary somewhat depending on the resonator and externa...

Page 96: ...s that have a width of 16 system clock OSC1 or OSC3 clock cycles or more will pass through the filter and are input to the S1C17 Core Pulses that have a width of less than 16 cycles will be rejected as noise Enable the filter under normal circumstances D0 NMIFE NMI Noise Filter Enable Bit Enables disables the noise filter for the NMI input 1 R W Enable reject noise 0 R W Disable bypass default Whe...

Page 97: ...ratio when OSC3 is selected for the LCD clock source Table 7 9 3 Selecting the LCD Clock Division Ratio LCKDV 2 0 Division ratio 0x7 0x5 Reserved 0x4 OSC3 1 512 0x3 OSC3 1 256 0x2 OSC3 1 128 0x1 OSC3 1 64 0x0 OSC3 1 32 Default 0x0 It is not necessary to select a division ratio when OSC1 is selected for the LCD clock source D1 LCKSRC LCD Clock Source Select Bit Select the LCD clock source 1 R W OSC...

Page 98: ...ck to be output to a device outside the IC 1 R W Enable On 0 R W Disable Off default When FOUT3E is set to 1 the FOUT3 clock is output from the FOUT3 pin and is stopped when FOUT3E is set to 0 The FOUT3 pin is shared with the P30 port and it functions as the P30 port pin by default When using the pin for the FOUT3 output write 1 to the P30MUX bit D0 P3_PMUX register to switch the pin function P30M...

Page 99: ...Clock Division Ratio Select Bits Selects a division ratio of the OSC1 clock to configure the 8 bit OSC1 timer operating clock Table 7 9 5 Selecting Division Ratio for T8OSC1 Clock T8O1CK 2 0 Division ratio 0x7 0x6 Reserved 0x5 OSC1 1 32 0x4 OSC1 1 16 0x3 OSC1 1 8 0x2 OSC1 1 4 0x1 OSC1 1 2 0x0 OSC1 1 1 Default 0x0 D0 T8O1CE T8OSC1 Clock Output Enable Bit Enables disables supplying the operating clo...

Page 100: ...ctrical Characteristics When the system clock is switched from OSC3 to OSC1 immediately after the OSC1 oscillator starts oscillating the system clock is halted until the OSC1 clock is activated 256 OSC1 clock cycle period The OSC3 oscillator cannot be disabled when OSC3 is used as the system clock The OSC1 oscillator cannot be disabled when OSC1 is used as the system clock Since the FOUT3 FOUT1 si...

Page 101: ...ource select System clock FOUT3 FOUT1 output circuit FOUT1 Noise filter RESET OSC1 OSC2 SLEEP On Off control Gear select OSC3 OSC1 Clock source select wakeup HALT On Off control S1C17 Core S1C17 Core Division ratio select Divider 1 1 1 16K Division ratio select On Off control Divider 1 32 1 512 On Off control Gate LCD Division ratio select On Off control On Off control SLEEP On Off control Noise f...

Page 102: ...ar for reducing the system clock speed CCLKGR 1 0 CCLK Clock Gear Ratio Select Bits in the CCLK Control CLG_CCLK Register D 1 0 0x5081 Table 8 2 1 Selecting a CCLK Gear CCLKGR 1 0 Gear ratio 0x3 1 8 0x2 1 4 0x1 1 2 0x0 1 1 Default 0x0 Controlling the clock supply To stop the CCLK clock to be supplied to the S1C17 Core execute the halt instruction This does not stop the system clock so the peripher...

Page 103: ...se bits are set to 0x3 by default so that the clock is supplied to the peripheral modules If all the peripheral modules in the internal peripheral area listed above can be idle disable the clock supply to reduce current consumption Note Be sure to avoid setting PCKEN 1 0 D 1 0 CLG_PCLK register to 0x2 or 0x1 as some peripheral modules will stop operating Peripheral modules that operate with a cloc...

Page 104: ... Register name Function 0x5080 CLG_PCLK PCLK Control Register Controls the PCLK output 0x5081 CLG_CCLK CCLK Control Register Configures the CCLK division ratio The following describes each CLG module control register These are all 8 bit registers Note When setting the registers be sure to write a 0 and not a 1 for all reserved bits ...

Page 105: ...s set to 0x3 and the clock supply is enabled by default When the peripheral modules listed below are not used disable the clock supply to reduce current consumption Peripheral modules that operate with PCLK Prescaler PWM capture timer remote controller P port UART 8 bit timer 16 bit timer Ch 0 2 Interrupt controller SPI I2C SVD circuit Power control circuit P port port MUX PWM capture timer MISC r...

Page 106: ...clock gear ratio select CCLKGR 1 0 Gear ratio 0x0 R W 0x3 0x2 0x1 0x0 1 8 1 4 1 2 1 1 D 7 2 Reserved D 1 0 CCLKGR 1 0 CCLK Clock Gear Ratio Select Bits Selects a gear ratio to decelerate the system clock This determines the rate of the CCLK clock for driving the S1C17 Core Drive the S1C17 Core with the slowest clock possible to reduce current consumption Table 8 4 3 Selecting CCLK Gear Ratio CCLKG...

Page 107: ... controller SPI I2C SVD circuit Power control circuit P port port MUX PWM capture timer MISC register Remote controller The peripheral modules listed below operate with a clock other than PCLK except for accessing their control registers Therefore PCLK is not required after the control registers are set once and the module starts operating Clock timer Stopwatch timer Watchdog timer 8 bit OSC1 time...

Page 108: ...8 CLOCK GENERATOR CLG 8 8 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 109: ...ler P port Figure 9 1 1 Prescaler The prescaler is controlled by the PRUN bit D0 PSC_CTL register Write 1 to PRUN to run the prescaler and write 0 to stop the prescaler When the timer and interface modules are idle stop the prescaler to reduce current consumption At initial reset the prescaler stops operating PRUN Prescaler Run Stop Control Bit in the Prescaler Control PSC_CTL Register D0 0x4020 N...

Page 110: ... D1 PRUND Prescaler run stop in debug mode 1 Run 0 Stop 0 R W D0 PRUN Prescaler run stop control 1 Run 0 Stop 0 R W D 7 2 Reserved D1 PRUND Prescaler Run Stop Setting Bit for Debug Mode Selects the prescaler operation in debug mode 1 R W Run 0 R W Stop default If PRUND is set to 1 the prescaler operates in debug mode If PRUND is set to 0 the prescaler stops operating when the S1C17 Core enters deb...

Page 111: ...9 PRESCALER PSC S1C17704 TECHNICAL MANUAL EPSON 9 3 9 3 Precaution Supply PCLK from the clock generator before the prescaler can be used ...

Page 112: ...9 PRESCALER PSC 9 4 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 113: ... a typical I O port VDD VSS Internal data bus Pxy Peripheral input Peripheral output Peripheral I O control PxPUy PxIOy PxSMy PxOUTy PxyMUX Pull up enable I O direction select Schmitt trigger control Output data Function select Figure 10 1 1 Structure of I O Port The P0 and P1 ports can generate input interrupts The P0 3 0 ports can be used as the key entry reset ports see Section 5 1 2 P0 Port Ke...

Page 114: ...6CH0 P17 SPISS SPI P17MUX D7 P1 Port Function Select P1_PMUX Register 0x52a1 P20 SDI SPI P20MUX D0 P2 Port Function Select P2_PMUX Register 0x52a2 P21 SDO SPI P21MUX D1 P22 SPICLK SPI P22MUX D2 P23 SIN UART P23MUX D3 P24 SOUT UART P24MUX D4 P25 SCLK UART P25MUX D5 P26 TOUT T16E P26MUX D6 P27 EXCL3 T16E P27MUX D7 P30 FOUT3 OSC P30MUX D0 P3 Port Function Select P3_PMUX Register 0x52a3 DCLK DBG P31 P...

Page 115: ... 7 0 Px_IN register so the data is 1 when the pin status is a high VDD level or 0 when the pin status is a low VSS level P0IN 7 0 P0 7 0 Port Input Data Bits in the P0 Port Input Data P0_IN Register D 7 0 0x5200 P1IN 7 0 P1 7 0 Port Input Data Bits in the P1 Port Input Data P1_IN Register D 7 0 0x5210 P2IN 7 0 P2 7 0 Port Input Data Bits in the P2 Port Input Data P2_IN Register D 7 0 0x5220 P3IN 3...

Page 116: ...1 default and the port pin will be pulled up when the port is in input mode When set to 0 the pull up resistor is disabled When the port is in output mode the PxPU 7 0 settings are ignored and the pull up resistor is disabled For unused ports enable the pull up resistors The pull up settings are effective even if the port pin is configured for a peripheral module When changing the port pin from lo...

Page 117: ... Port Schmitt Trigger Input Enable Bits in the P1 Port Schmitt Trigger Control P1_SM Register D 7 0 0x5214 P2SM 7 0 P2 7 0 Port Schmitt Trigger Input Enable Bits in the P2 Port Schmitt Trigger Control P2_SM Register D 7 0 0x5224 P3SM 3 0 P3 3 0 Port Schmitt Trigger Input Enable Bits in the P3 Port Schmitt Trigger Control P3_SM Register D 3 0 0x5234 When PxSM 7 0 is set to 1 default the port is con...

Page 118: ...LK 512 µs 0x2 512 fPCLK 256 µs 0x1 256 fPCLK 128 µs 0x0 Disabled Off Default 0x0 when OSC3 2 MHz PCLK OSC3 Notes The check time to eliminate chattering means the maximum pulse width that can be eliminated The valid interrupt input needs a pulse width of the set check time minimum to twice that of the check time maximum Input interrupts cannot be accepted in SLEEP mode if the CPU enters SLEEP mode ...

Page 119: ... 7 0 0x5205 P1IE 7 0 P1 7 0 Port Interrupt Enable Bits in the P1 Port Interrupt Mask P1_IMSK Register D 7 0 0x5215 By setting PxIE 7 0 to 1 the corresponding port is enabled to generate an interrupt The port whose PxIE bit is set to 0 default does not generate an interrupt In addition it is necessary to set the interrupt controller to actually generate an interrupt For setting the interrupt contro...

Page 120: ...he P port module asserts the P0 or P1 port interrupt signal sent to the ITC To generate a port interrupt set the interrupt level and enable the port interrupt using the ITC registers Table 10 7 1 lists the control bits for the port interrupt in the ITC Table 10 7 1 Control Bits in ITC Port Interrupt flag Interrupt enable Interrupt level setting Trigger mode setting P0 EIFT0 D0 ITC_IFLG EIEN0 D0 IT...

Page 121: ...NICAL MANUAL EPSON 10 9 Interrupt vectors The following shows the vector numbers and vector addresses for the port interrupts Table 10 7 2 Port Interrupt Vectors Port Vector number Vector address P0 4 0x04 0x8010 P1 5 0x05 0x8014 ...

Page 122: ... Controls the P1 port Schmitt trigger input 0x5215 P1_IMSK P1 Port Interrupt Mask Register Enables disables the P1 port interrupt 0x5216 P1_EDGE P1 Port Interrupt Edge Select Register Selects the signal edge for generating P1 port interrupts 0x5217 P1_IFLG P1 Port Interrupt Flag Register Indicates resets the P1 port interrupt occurrence status 0x5220 P2_IN P2 Port Input Data Register P2 port input...

Page 123: ...er P3_IN 0x5230 8 bits D7 4 reserved 0 when being read D3 0 P3IN 3 0 P3 3 0 port input data 1 1 H 0 0 L R Note The letter x in bit names etc denotes a port number from 0 to 3 D 7 0 PxIN 7 0 Px 7 0 Port Input Data Bits P3IN 3 0 for the P3 ports These bits are used to read data from I O port pins Default external pin status 1 R High level 0 R Low level The PxIN 7 0 bits correspond to the Px 7 0 port...

Page 124: ...L 0 R W P3 Port Output Data Register P3_OUT 0x5231 8 bits D7 4 reserved 0 when being read D3 0 P3OUT 3 0 P3 3 0 port output data 1 1 H 0 0 L 0 R W Note The letter x in bit names etc denotes a port number from 0 to 3 D 7 0 PxOUT 7 0 Px 7 0 Port Output Data Bits P3OUT 3 0 for the P3 ports These bits are used to set data to be output from I O port pins 1 R W High level 0 R W Low level default The PxO...

Page 125: ...1 Output 0 Input 0 R W P3 Port I O Direction Control Register P3_IO 0x5232 8 bits D7 4 reserved 0 when being read D3 0 P3IO 3 0 P3 3 0 port I O direction select 1 Output 0 Input 0 R W Note The letter x in bit names etc denotes a port number from 0 to 3 D 7 0 PxIO 7 0 Px 7 0 Port I O Direction Select Bits P3IO 3 0 for the P3 ports Sets the I O ports in input or output mode 1 R W Output mode 0 R W I...

Page 126: ...resistor incorporated in each port 1 R W Enable default 0 R W Disable The PxPU 7 0 bits are the pull up control bits corresponding to the Px 7 0 ports respectively When a bit is set to 1 the pull up resistor is enabled and the corresponding I O port is pulled up during input mode if it is set to 0 the I O port is not pulled up When the port is in output mode the PxPU 7 0 settings are ignored and t...

Page 127: ... 0 P2 7 0 port Schmitt trigger input enable 1 Enable Schmitt 0 Disable CMOS 1 0xff R W P3 Port Schmitt Trigger Control Register P3_SM 0x5234 8 bits D7 4 reserved 0 when being read D3 0 P3SM 3 0 P3 3 0 port Schmitt trigger input enable 1 Enable Schmitt 0 Disable CMOS 1 0xff R W Note The letter x in bit names etc denotes a port number from 0 to 3 D 7 0 PxSM 7 0 Px 7 0 Port Schmitt Trigger Input Enab...

Page 128: ... W Note The letter x in bit names etc denotes a port number 0 or 1 D 7 0 PxIE 7 0 Px 7 0 Port Interrupt Enable Bits Enables disables the P0 7 0 and P1 7 0 port interrupts individually 1 R W Enable interrupt 0 R W Disable interrupt default Setting a PxIE 7 0 bit to 1 enables the interrupt of the corresponding port setting to 0 disables the interrupt The input level transition at the port pin whose ...

Page 129: ...gister P1_EDGE 0x5216 8 bits D7 0 P1EDGE 7 0 P1 7 0 port interrupt edge select 1 Falling edge 0 Rising edge 0 R W Note The letter x in bit names etc denotes a port number 0 or 1 D 7 0 PxEDGE 7 0 Px 7 0 Port Interrupt Edge Select Bits Selects an input signal edge to generate the P0 7 0 and P1 7 0 port interrupts individually 1 R W Falling edge 0 R W Rising edge default When a PxEDGE 7 0 bit is set ...

Page 130: ...dge rising edge or falling edge of the input signal if the corresponding PxIE 7 0 bit Px_IMSK register has been set to 1 At the same time a P0 or P1 interrupt request signal is output to the ITC The interrupt request signal sets the P0 or P1 port interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the ITC and S1C17 Core settings The settings shown below are re...

Page 131: ...4 is used or not and also select an input level check time when the filter is used Table 10 8 2 Setting Input Level Check Time P0CFx 2 0 Check time 0x7 16384 fPCLK 8 ms 0x6 8192 fPCLK 4 ms 0x5 4096 fPCLK 2 ms 0x4 2048 fPCLK 1 ms 0x3 1024 fPCLK 512 µs 0x2 512 fPCLK 256 µs 0x1 256 fPCLK 128 µs 0x0 Disabled Off Default 0x0 when OSC3 2 MHz PCLK OSC3 Notes The check time to eliminate chattering means t...

Page 132: ...P0KRST 1 0 Port used for resetting 0x3 P00 P01 P02 P03 0x2 P00 P01 P02 0x1 P00 P01 0x0 Not used Default 0x0 The P0 key entry reset is one of the initial reset features and it generates an initial reset signal when the ports selected here is set to low level at the same time For example if P0KRST 1 0 is set to 0x3 an initial reset will take place when the four ports P00 P03 are set to low level at ...

Page 133: ...eing read D5 P05MUX P05 port function select 1 REMO 0 P05 0 R W D4 P04MUX P04 port function select 1 REMI 0 P04 0 R W D3 0 reserved 0 when being read The P04 and P05 I O port pins are shared with a peripheral module This register configures the pin functions D 7 6 Reserved D5 P05MUX P05 Port Function Select Bit 1 R W REMO REMC 0 R W P05 port default D4 P04MUX P04 Port Function Select Bit 1 R W REM...

Page 134: ... port function select 1 SDA 0 P14 0 R W D3 P13MUX P13 port function select 1 FOUT1 0 P13 0 R W D2 0 reserved 0 when being read The P13 P15 and P17 I O port pins are shared with a peripheral module This register configures the pin functions D7 P17MUX P17 Port Function Select Bit 1 R W SPISS SPI 0 R W P17 port default D6 Reserved D5 P15MUX P15 Port Function Select Bit 1 R W SCL I2C 0 R W P15 port de...

Page 135: ...0 P21 0 R W D0 P20MUX P20 port function select 1 SDI 0 P20 0 R W The P20 P27 I O port pins are shared with a peripheral module This register configures the pin functions D7 P27MUX P27 Port Function Select Bit 1 R W EXCL3 T16E 0 R W P27 port default D6 P26MUX P26 Port Function Select Bit 1 R W TOUT T16E 0 R W P26 port default D5 P25MUX P25 Port Function Select Bit 1 R W SCLK UART 0 R W P25 port def...

Page 136: ...0 DST2 0 R W D1 P31MUX P31 port function select 1 P31 0 DCLK 0 R W D0 P30MUX P30 port function select 1 FOUT3 0 P30 0 R W The P30 P33 I O port pins are shared with a peripheral module This register configures the pin functions D 7 4 Reserved D3 P33MUX P33 Port Function Select Bit 1 R W P33 port 0 R W DSIO DBG default D2 P32MUX P32 Port Function Select Bit 1 R W P32 port 0 R W DST2 DBG default D1 P...

Page 137: ...t occurs reset the interrupt flag in the P0IF 7 0 0x5207 or P1IF 7 0 0x5217 of the P port module in the interrupt handler routine this also resets the interrupt flag in the ITC P0 port chattering filter Input interrupts cannot be accepted in SLEEP mode if the CPU enters SLEEP mode when the chattering filter is active The chattering filter should be disabled off before executing the slp instruction...

Page 138: ...10 I O PORTS P 10 26 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 139: ...pulse width measurement function using I O port pins Figure 11 1 1 shows the structure of the 16 bit timer Reload data register T16_TRx PRUN DF 3 0 PCLK 1 1 1 16K Underflow Run stop control Internal data bus Count clock select Interrupt request Serial transfer clock To ITC To SPI from Ch 1 To I2C from Ch 2 P16 Ch 0 P07 Ch 1 P06 Ch 2 PRESER Timer reset Down counter T16_TCx Control circuit External ...

Page 140: ...w signal is used to generate an interrupt and a clock for the internal serial interface The period until an underflow occurs can be programmed minutely according to the prescaler clock and counter initial value selections so this mode is useful for generating a serial transfer clock or a one shot time measurement Selecting the count clock Use the DF 3 0 bits D 3 0 T16_CLKx register to select the c...

Page 141: ...rporate a chattering filter and it is effective for the EXCLx input signal For controlling the chattering filter see Section 10 6 Chattering Filter for P0 Ports Selecting the signal polarity The external clock mode allows selection of a input signal edge to perform counting Either falling edge or rising edge can be selected using the CKACTV D10 T16_CTLx register CKACTV External Clock Active Level ...

Page 142: ...n the case of the internal clock mode the timer operates with the prescaler output clock selected using DF 3 0 D 3 0 T16_CLKx register Select an appropriate clock according to the approximate input pulse width and measurement accuracy see Table 11 2 1 1 Selecting the signal polarity Use CKACTV D10 T16_CTLx register to select the active level for the pulse to be measured When CKACTV is 1 default th...

Page 143: ...ws the timer presets the reload data register value to the counter and continues counting The timer outputs the underflow pulses periodically Set the 16 bit timer in this mode when generating periodical interrupts with a given interval or generating the serial transfer clock One shot mode TRMD 1 The 16 bit timer is set in one shot mode when TRMD is set to 1 In this mode the 16 bit timer automatica...

Page 144: ... period of time from starting the timer until an underflow occurs and between underflows This makes it possible to obtain a desired wait time a periodical interrupt interval or programmable transfer clock for the serial interface One shot mode Counter Repeat mode Counter 0 1 n 1 n n Preset by resetting the timer Preset by resetting the timer Preset automatically Underflow Preset automatically n Re...

Page 145: ...etting the 16 bit Timer To reset the 16 bit timer write 1 to the PRESER bit D1 T16_CTLx register This initializes the counter by presetting the reload data register value PRESER Timer Reset Bit in the 16 bit Timer Ch x Control T16_CTLx Register D1 0x4226 0x4246 0x4266 ...

Page 146: ...al value has not been preset When the counter underflows the timer outputs an underflow pulse and presets the initial value again At the same time an interrupt request is sent to the interrupt controller ITC If the timer is set in one shot mode the timer stops counting If the timer is set in repeat mode the timer continues counting from the reloaded initial value To stop the 16 bit timer from the ...

Page 147: ...erflow signal Timer output serial transfer clock Interrupt request to the ITC Figure 11 7 1 Timer Output Clock The generated clocks are sent to the internal serial interfaces as below 16 bit timer Ch 1 output clock SPI 16 bit timer Ch 2 output clock I2C The reload data register value to obtain a desired transfer rate is calculated by the expression below clk_in SPI TR 1 bps 2 clk_in I2C TR 1 bps 2...

Page 148: ...st to the S1C17 Core To disable the timer interrupt set the interrupt enable bit to 0 The interrupt flag is always set to 1 by the timer underflow pulse regardless of how the interrupt enable bit is set even when set to 0 The interrupt level setup bits set the interrupt level 0 to 7 of the timer interrupt If the same interrupt level is set timer Ch 0 has highest priority and timer Ch 2 has lowest ...

Page 149: ...ects a prescaler output clock 0x4242 T16_TR1 16 bit Timer Ch 1 Reload Data Register Sets reload data 0x4244 T16_TC1 16 bit Timer Ch 1 Counter Data Register Counter data 0x4246 T16_CTL1 16 bit Timer Ch 1 Control Register Sets the timer mode and starts stops the timer 0x4260 T16_CLK2 16 bit Timer Ch 2 Input Clock Select Register Selects a prescaler output clock 0x4262 T16_TR2 16 bit Timer Ch 2 Reloa...

Page 150: ... Note The letter x in register names etc denotes a channel number from 0 to 2 0x4220 16 bit Timer Ch 0 Input Clock Select Register T16_CLK0 0x4240 16 bit Timer Ch 1 Input Clock Select Register T16_CLK1 0x4260 16 bit Timer Ch 2 Input Clock Select Register T16_CLK2 D 15 4 Reserved D 3 0 DF 3 0 Timer Input Clock Select Bits These bits select the count clock of the 16 bit timer from 15 prescaler outpu...

Page 151: ...er Ch 1 Reload Data Register T16_TR1 0x4262 16 bit Timer Ch 2 Reload Data Register T16_TR2 D 15 0 TR 15 0 16 bit Timer Reload Data Set the initial value for the counter Default 0x0 The reload data written in this register is preset to the respective counter when the timer is reset or when the counter underflows When starting the 16 bit timer after resetting the timer counts down from the reload va...

Page 152: ...15 0 16 bit timer counter data TC15 MSB TC0 LSB 0x0 to 0xffff 0xffff R Note The letter x in register names etc denotes a channel number from 0 to 2 0x4224 16 bit Timer Ch 0 Counter Data Register T16_TC0 0x4244 16 bit Timer Ch 1 Counter Data Register T16_TC1 0x4264 16 bit Timer Ch 2 Counter Data Register T16_TC2 D 15 0 TC 15 0 16 bit Timer Counter Data The counter data can be read from this registe...

Page 153: ... width measurement mode CKSL 1 0 0x2 select the polarity of the external input pulse D 9 8 CKSL 1 0 Input Clock and Pulse Width Measurement Mode Select Bits Selects a 16 bit timer operating mode Table 11 9 3 Selecting Operating Mode CKSL 1 0 Operating mode 0x3 Reserved 0x2 Pulse width measurement mode 0x1 External clock mode 0x0 Internal clock mode Default 0x0 In internal clock mode the timer uses...

Page 154: ...set in one shot mode when TRMD is set to 1 In this mode the 16 bit timer automatically stops counting when the counter underflows so only one interrupt can be generated after starting the timer When an underflow occurs the counter is preset with the reload data register value before the timer operation stops Set the 16 bit timer in this mode when a certain waiting time must be generated or measuri...

Page 155: ...RS T16 S1C17704 TECHNICAL MANUAL EPSON 11 17 11 10 Precautions Before the 16 bit timer can start counting the prescaler must be run When setting the count clock or count mode make sure the 16 bit timer is turned off ...

Page 156: ...11 16 BIT TIMERS T16 11 18 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 157: ...rate an interrupt and the clock for UART The underflow period can be programmed by selecting a prescaler clock and setting reload data This allows the application program to get any desired time intervals and programmable serial transfer rates The fine mode provides a function to minimize transfer rate error Figure 12 1 1 shows the structure of the 8 bit timer Reload data register T8F_TR PRUN DF 3...

Page 158: ...oad data register value to the counter and continues counting The timer outputs the underflow pulses periodically Set the 8 bit timer in this mode when generating periodical interrupts with a given interval or generating the serial transfer clock One shot mode TRMD 1 The 8 bit timer is set in one shot mode when TRMD is set to 1 In this mode the 8 bit timer automatically stops counting when the cou...

Page 159: ..._CLK Register D 3 0 0x4200 Table 12 3 1 Selecting the Count Clock DF 3 0 Prescaler output clock DF 3 0 Prescaler output clock 0xf Reserved 0x7 PCLK 1 128 0xe PCLK 1 16384 0x6 PCLK 1 64 0xd PCLK 1 8192 0x5 PCLK 1 32 0xc PCLK 1 4096 0x4 PCLK 1 16 0xb PCLK 1 2048 0x3 PCLK 1 8 0xa PCLK 1 1024 0x2 PCLK 1 4 0x9 PCLK 1 512 0x1 PCLK 1 2 0x8 PCLK 1 256 0x0 PCLK 1 1 Default 0x0 Notes Before the 8 bit timer ...

Page 160: ...ws This makes it possible to obtain a desired wait time a periodical interrupt interval or programmable transfer clock for the serial interface One shot mode Counter Repeat mode Counter 0 1 n 1 n n Preset by resetting the timer Preset by resetting the timer Preset automatically Underflow Preset automatically n Reload data 0 1 n 1 n n Underflow Timer starts Timer starts Preset automatically 0 1 n 1...

Page 161: ... 5 12 5 Resetting the 8 bit Timer To reset the 8 bit timer write 1 to the PRESER bit D1 T8F_CTL register This initializes the counter by presetting the Reload Data Register value PRESER Timer Reset Bit in the 8 bit Timer Control T8F_CTL Register D1 0x4206 ...

Page 162: ...as not been preset When the counter underflows the timer outputs an underflow pulse and presets the initial value again At the same time an interrupt request is sent to the interrupt controller ITC If the timer is set in one shot mode the timer stops counting If the timer is set in repeat mode the timer continues counting from the reloaded initial value To stop the 8 bit timer from the application...

Page 163: ...Interrupt request to the ITC Figure 12 7 1 Timer Output Clock Also this pulse is used to generate a serial transfer clock and the clock is sent to the UART The reload data register value to obtain a desired transfer rate is calculated by the expression below clk_in bps T8F_TR 1 16 TFMD clk_in T8F_TR TFMD 16 16 bps clk_in Count clock prescaler output clock frequency Hz T8F_TR Reload data 0 255 bps ...

Page 164: ...a pattern of delays to be inserted in a 16 underflow period The output clock period will be prolonged for one count clock period per one delay inserted Also this setting will delay interrupt timings Table 12 8 1 Delay Patterns Specified with TFMD 3 0 TFMD 3 0 Underflow number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x0 0x1 D 0x2 D D 0x3 D D D 0x4 D D D D 0x5 D D D D D 0x6 D D D D D D 0x7 D D D D D ...

Page 165: ... corresponding to that interrupt flag has been set to 1 the ITC sends an interrupt request to the S1C17 Core To disable the timer interrupt set the interrupt enable bit to 0 The interrupt flag is always set to 1 by the timer underflow pulse regardless of how the interrupt enable bit is set even when set to 0 The interrupt level setup bits set the interrupt level 0 to 7 of the timer interrupt An in...

Page 166: ...ter Selects a prescaler output clock 0x4202 T8F_TR 8 bit Timer Reload Data Register Sets reload data 0x4204 T8F_TC 8 bit Timer Counter Data Register Counter data 0x4206 T8F_CTL 8 bit Timer Control Register Sets the timer mode and starts stops the timer The following describes each 8 bit timer register These are all 16 bit registers Note When setting the registers be sure to write a 0 and not a 1 f...

Page 167: ...PCLK 1 1024 PCLK 1 512 PCLK 1 256 PCLK 1 128 PCLK 1 64 PCLK 1 32 PCLK 1 16 PCLK 1 8 PCLK 1 4 PCLK 1 2 PCLK 1 1 D 15 4 Reserved D 3 0 DF 3 0 Timer Input Clock Select Bits These bits select the count clock of the 8 bit timer from 15 prescaler output clocks Table 12 10 2 Selecting the Count Clock DF 3 0 Prescaler output clock DF 3 0 Prescaler output clock 0xf Reserved 0x7 PCLK 1 128 0xe PCLK 1 16384 ...

Page 168: ...load Data Set the initial value for the counter Default 0x0 The reload data written in this register is preset to the respective counter when the timer is reset or when the counter underflows When starting the 8 bit timer after resetting the timer counts down from the reload value So the reload value and the input clock frequency determine the period of time from starting the timer until an underf...

Page 169: ...nit R W Remarks 8 bit Timer Counter Data Register T8F_TC 0x4204 16 bits D15 8 reserved 0 when being read D7 0 TC 7 0 8 bit timer counter data TC7 MSB TC0 LSB 0x0 to 0xff 0xff R D 15 8 Reserved D 7 0 TC 7 0 8 bit Timer Counter Data The counter data can be read from this register Default 0xff This is a read only register so the writing operation is invalid ...

Page 170: ...or Default 0x0 The TFMD 3 0 bits specify a pattern of delays to be inserted in a 16 underflow period The output clock period will be prolonged for one count clock period per one delay inserted Table 12 10 3 Delay Patterns Specified with TFMD 3 0 TFMD 3 0 Underflow number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x0 0x1 D 0x2 D D 0x3 D D D 0x4 D D D D 0x5 D D D D D 0x6 D D D D D D 0x7 D D D D D D D 0...

Page 171: ...MD is set to 1 In this mode the 8 bit timer automatically stops counting when the counter underflows so only one interrupt can be generated after starting the timer When an underflow occurs the counter is preset with the reload data register value before the timer operation stops Set the 8 bit timer in this mode when a certain waiting time must be generated Note When setting the count mode make su...

Page 172: ...ER T8F 12 16 EPSON S1C17704 TECHNICAL MANUAL 12 11 Precautions Before the 8 bit timer can start counting the prescaler must be run When setting the count clock or count mode make sure the 8 bit timer is turned off ...

Page 173: ...mer Figure 13 1 1 Structure of PWM Capture Timer In the PWM capture timer a 16 bit up counter T16E_TC register as well as two 16 bit compare data registers T16E_CA and T16E_CB registers and their buffers are provided The 16 bit counter can be reset to 0 or set with an initial value by software and counts up using the prescaler output clock or an external signal input from the P27 port The counter ...

Page 174: ...rved 0x7 PCLK 1 128 0xe PCLK 1 16384 0x6 PCLK 1 64 0xd PCLK 1 8192 0x5 PCLK 1 32 0xc PCLK 1 4096 0x4 PCLK 1 16 0xb PCLK 1 2048 0x3 PCLK 1 8 0xa PCLK 1 1024 0x2 PCLK 1 4 0x9 PCLK 1 512 0x1 PCLK 1 2 0x8 PCLK 1 256 0x0 PCLK 1 1 Default 0x0 Notes Before the PWM capture timer can start counting in internal clock mode the prescaler must be run When setting the count clock make sure the PWM capture timer...

Page 175: ...et Bit in the PWM Timer Control T16E_CTL Register D1 0x5306 Normally reset the counter before starting count up by writing 1 to this control bit After the counter starts counting it will be reset by the hardware when the counter reaches compare data B Furthermore any data can be set to the counter by writing it to T16ETC 15 0 D 15 0 T16E_TC register T16ETC 15 0 Counter Data in the PWM Timer Counte...

Page 176: ...ite compare data A to T16ECA 15 0 D 15 0 T16E_CA register and compare data B to T16ECB 15 0 D 15 0 T16E_CB register T16ECA 15 0 Compare Data A in the PWM Timer Compare Data A T16E_CA Register D 15 0 0x5300 T16ECB 15 0 Compare Data B in the PWM Timer Compare Data B T16E_CB Register D 15 0 0x5302 When CBUFEN is set to 0 these registers allow direct reading writing from to the compare data register W...

Page 177: ... counter retains its count so that the timer can start counting again from that point When both T16ERUN and T16ERST are set to 1 at the same time the timer starts counting after resetting the coun ter If the count of the counter matches the set value of the compare data A register during count up the timer outputs the compare A match signal as a cause of interrupt When the counter matches compare ...

Page 178: ...urned off Setting the signal active level By default an active high signal normal low is generated This logic can be inverted using INVOUT D4 T16E_CTL register When 1 is written to INVOUT the timer generates an active low normal high signal INVOUT Inverse Output Control Bit in the PWM Timer Control T16E_CTL Register D4 0x5306 Note that the initial output level set by INITOL is inverted when INVOUT...

Page 179: ...itial output level when output is started until the counter becomes equal to the compare data A set in the T16E_CA register 0x5300 When the counter is incremented to the next value from the compare data A the output pin goes high and a cause of compare A interrupt occurs When the counter becomes equal to the compare data B set in the T16E_CB register 0x5302 the counter is reset and the output pin ...

Page 180: ...Clock Output in Fine Mode As shown in the figure above in fine mode the output clock duty ratio can be adjusted in the half cycle of the input clock However when compare data A is 0 the timer outputs a pulse with a 1 cycle width as the input clock the same as the default setting In fine mode the maximum value of compare data B is 215 1 32 767 and the range of compare data A that can be set is 0 to...

Page 181: ...interrupt has oc curred due to a compare A match or another cause Furthermore the interrupt handler routine must reset write 1 to CAIF in the T16E module not the PWM capture timer interrupt flag in the ITC to clear the cause of interrupt Compare B match interrupt This interrupt request occurs when the count of the counter matches the set value of the compare data B register during count up and it ...

Page 182: ...o the S1C17 Core To disable the PWM capture timer inter rupt set EIEN7 to 0 EIFT7 is always set to 1 by the interrupt signal sent from the T16E module regardless of how EIEN7 is set even when set to 0 EILV7 2 0 sets the interrupt level 0 to 7 of the PWM capture timer interrupt An interrupt request to the S1C17 Core is accepted only when all the conditions described below are met The interrupt enab...

Page 183: ...Data Register Counter data 0x5306 T16E_CTL PWM Timer Control Register Sets the timer mode and starts stops the timer 0x5308 T16E_CLK PWM Timer Input Clock Select Register Selects a prescaler output clock 0x530a T16E_IMSK PWM Timer Interrupt Mask Register Enables disables interrupt 0x530c T16E_IFLG PWM Timer Interrupt Flag Register Indicates resets interrupt occurrence status The following describe...

Page 184: ...ult 0x0 When CBUFEN D5 T16E_CTL register is set to 0 compare data is directly read or writing from to the compare data A register When CBUFEN is set to 1 compare data is read or written from to the compare data A buffer through this register The content of the buffer is loaded to the compare data A register when the counter is reset The data set in this register is compared with the counter data W...

Page 185: ...e timer Default 0x0 When CBUFEN D5 T16E_CTL register is set to 0 compare data is directly read or writing from to the compare data B register When CBUFEN is set to 1 compare data is read or written from to the compare data B buffer through this register The content of the buffer is loaded to the compare data B register when the counter is reset The data set in this register is compared with the co...

Page 186: ... Name Function Setting Init R W Remarks PWM Timer Counter Data Register T16E_TC 0x5304 16 bits D15 0 T16ETC 15 0 Counter data T16ETC15 MSB T16ETC0 LSB 0x0 to 0xffff 0x0 R W D 15 0 T16ETC 15 0 Counter Data The counter data can be read from this register Default 0x0 Furthermore data can be set to the counter by writing it to this register ...

Page 187: ... 1 to T16ERST D1 However this level is inverted if INVOUT D4 is set to 1 D7 Reserved D6 SELFM Fine Mode Select Bit Sets fine mode for clock output 1 R W Fine mode 0 R W Normal output default When SELFM is set to 1 clock output is set in fine mode which allows adjustment of the output signal duty ratio in units of a half cycle for the input clock When SELFM is set to 0 normal clock output will be p...

Page 188: ...W Enable 0 R W Disable default The TOUT signal is output from the TOUT P26 output pin by writing 1 to OUTEN Clock output is stopped by writing 0 to OUTEN and goes to the off level according to the set values of INVOUT D4 and INITOL D8 In this case the P26 pin must be set for the TOUT output using the P26 port func tion select register before outputting the TOUT signal D1 T16ERST Timer Reset Bit Re...

Page 189: ...1 1024 PCLK 1 512 PCLK 1 256 PCLK 1 128 PCLK 1 64 PCLK 1 32 PCLK 1 16 PCLK 1 8 PCLK 1 4 PCLK 1 2 PCLK 1 1 D 15 4 Reserved D 3 0 T16EDF 3 0 Timer Input Clock Select Bits These bits select the count clock of the PWM capture timer from 15 prescaler output clocks Table 13 8 2 Selecting the Count Clock T16EDF 3 0 Prescaler output clock T16EDF 3 0 Prescaler output clock 0xf Reserved 0x7 PCLK 1 128 0xe P...

Page 190: ...ompare B interrupt 1 R W Enable interrupt 0 R W Disable interrupt default Setting CBIE to 1 enables the compare B interrupt setting to 0 disables the interrupt In addition it is necessary to set the PWM capture timer interrupt enable bits in the ITC to interrupt enabled to actually generate an interrupt D0 CAIE Compare A Interrupt Enable Bit Enables disables the compare A interrupt 1 R W Enable in...

Page 191: ... and S1C17 Core settings D0 CAIF Compare A Interrupt Flag This is the interrupt flag to indicate the compare A interrupt cause occurrence status 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Has no effect CAIF is the interrupt flag for the compare A interrupt The interrupt flag is set to 1 when the count of the counter matches the set valu...

Page 192: ...the timer output clock cycle is the input clock 1 2 When compare data are set as A B or set as A B 2 in fine mode the compare B match signal will be gen erated but no compare A match signal will be generated In this case the timer output signal is fixed at the low or high when INVOUT 1 To avoid occurrence of unnecessary interrupts be sure to reset CAIF D0 T16E_IFLG register or CBIF D1 T16E_IFLG re...

Page 193: ...ect T8ORMD Interrupt enable T8OIE 8 bit OSC1 Timer OSC OSC1 oscillator divider Gate Division ratio select Figure 14 1 1 Structure of 8 bit OSC1 Timer In the 8 bit OSC1 timer an 8 bit up counter T8OSC1_CNT register and an 8 bit compare data register T8OSC1_CMP register are provided The 8 bit counter can be reset to 0 with software and counts up using an divided OSC1 clock OSC1 1 1 OSC1 1 32 The cou...

Page 194: ...value matches to the compare data the timer resets the counter and continues counting At the same time the timer outputs the interrupt signal Set the 8 bit OSC1 timer in this mode when generating periodical interrupts with a given interval One shot mode T8ORMD 1 The 8 bit OSC1 timer is set in one shot mode when T8ORMD is set to 1 In this mode the 8 bit OSC1 timer automatically stops counting when ...

Page 195: ...io 0x7 0x6 Reserved 0x5 OSC1 1 32 0x4 OSC1 1 16 0x3 OSC1 1 8 0x2 OSC1 1 4 0x1 OSC1 1 2 0x0 OSC1 1 1 Default 0x0 Use the T8O1CE bit D0 OSC_T8OSC1 register to control the clock supply to the 8 bit OSC1 timer T8O1CE is set to 0 by default so the clock is disabled for supplying When the T8O1CE is set to 1 the clock selected as above is supplied to the 8 bit OSC1 timer If the 8 bit OSC1 timer does not ...

Page 196: ...e T8ORST bit D4 T8OSC1_CTL register This initializes the counter to 0 T8ORST Timer Reset Bit in the 8 bit OSC1 Timer Control T8OSC1_CTL Register D4 0x50c0 Normally reset the counter before starting count up by writing 1 to this control bit After the counter starts counting it will be reset by the hardware when the counter reaches compare data ...

Page 197: ... compare data register is set to 0x0 The timer compares the compare data register and count data and when the two values are equal resets the counter and generates a compare match signal This compare match signal is used to generate an interrupt The compare match period is calculated by the expression below CMP 1 Compare match period s clk_in clk_in Compare match cycle Hz CMP 1 CMP Compare data T8...

Page 198: ...counter data Even when the timer has stopped counting the counter retains its count so that the timer can start counting again from that point When both T8ORUN and T8ORST are set to 1 at the same time the timer starts counting after resetting the counter If the count of the counter matches the set value of the compare data register during count up the timer outputs the compare match signal as a ca...

Page 199: ...occurrence of unnecessary interrupts be sure to reset the T8OIF flag before the compare match interrupt is enabled using T8OIE ITC registers for 8 bit OSC1 timer interrupt When a compare match occurs according to the interrupt condition settings shown above the 8 bit OSC1 timer asserts the interrupt signal sent to the ITC To generate an 8 bit OSC1 timer interrupt set the interrupt level and enable...

Page 200: ...urred For details on these interrupt control registers as well as the device operation when an interrupt has occurred see Chapter 6 Interrupt Controller ITC Note The settings shown below are required to manage the cause of interrupt occurrence status using the interrupt flag in the T8OSC1 module 1 Set the 8 bit OSC1 timer interrupt trigger mode in the ITC to level trigger 2 After an interrupt occu...

Page 201: ...NT 8 bit OSC1 Timer Counter Data Register Counter data 0x50c2 T8OSC1_CMP 8 bit OSC1 Timer Compare Data Register Sets compare data 0x50c3 T8OSC1_IMSK 8 bit OSC1 Timer Interrupt Mask Register Enables disables interrupt 0x50c4 T8OSC1_IFLG 8 bit OSC1 Timer Interrupt Flag Register Indicates resets interrupt occurrence status The following describes each 8 bit OSC1 timer register These are all 8 bit reg...

Page 202: ...unting until the application program stops the timer When the counter value matches to the compare data the timer resets the counter and continues counting At the same time the timer outputs the interrupt signal Set the 8 bit OSC1 timer in this mode when generating periodical interrupts with a given interval The 8 bit OSC1 timer is set in one shot mode when T8ORMD is set to 1 In this mode the 8 bi...

Page 203: ...CNT 7 0 Counter Data The counter data can be read from this register Default 0x0 This is a read only register so the writing operation is invalid Note If this register is read while the counter is running the read value may not represent the current counter value an indefinite value may be read out The counter value should be obtained by one of the following procedures Read the counter value after...

Page 204: ... OSC1 Timer Compare Data Register T8OSC1_CMP 0x50c2 8 bits D7 0 T8OCMP 7 0 Compare data T8OCMP7 MSB T8OCMP0 LSB 0x0 to 0xff 0x0 R W D 7 0 T8OCMP 7 0 Compare Data Sets the compare data for the 8 bit OSC1 timer Default 0x0 The data set in this register is compared with the counter data When the contents match a cause of compare interrupt is generated At the same time the counter is reset to 0 ...

Page 205: ...D0 T8OIE 8 bit OSC1 timer interrupt enable 1 Enable 0 Disable 0 R W D 7 1 Reserved D0 T8OIE 8 bit OSC1 Timer Interrupt Enable Bit Enables disables the compare match interrupt 1 R W Enable interrupt 0 R W Disable interrupt default Setting T8OIE to 1 enables the 8 bit OSC1 timer to request interrupts to the ITC setting to 0 disables the interrupt In addition it is necessary to set the 8 bit OSC1 tim...

Page 206: ...to 1 when the count of the counter matches the set value of the compare data register during count up if T8OIE D0 T8OSC1_IMSK register has been set to 1 At the same time the 8 bit OSC1 timer interrupt request signal is output to the ITC The interrupt request signal sets the 8 bit OSC1 timer interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the ITC and S1C17 ...

Page 207: ...ssary interrupts be sure to reset T8OIF D0 T8OSC1_IFLG register before the compare match interrupt is enabled using T8OIE D0 T8OSC1_IMSK register If the counter data register is read while the counter is running the read value may not represent the current counter value an indefinite value may be read out To obtain the counter value read the counter data register after stopping the counter Or read...

Page 208: ...14 8 BIT OSC1 TIMER T8OSC1 14 16 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 209: ...re the clock timer can generate an interrupt using the 32 Hz 8 Hz 2 Hz and 1 Hz signals Normally the clock timer is used for various timing functions such as a clock Figure 15 1 1 shows the structure of the clock timer 256 Hz Internal data bus Clock timer interrupt request To ITC 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz Count control circuit Interrupt control circuit Run Stop control Interrupt...

Page 210: ...C1 clock by 128 Therefore the clock frequency is 256 Hz when the OSC1 clock frequency is 32 768 kHz Be aware that the frequencies described in this chapter change if the OSC1 clock has another frequency The OSC module does not provide a control bit for the 256 Hz clock The 256 Hz clock is always supplied to the clock timer when the OSC1 oscillator is on For control of the OSC1 oscillator see Chapt...

Page 211: ...esetting the Clock Timer To reset the clock timer write 1 to the CTRST bit D4 CT_CTL register This initializes the counter to 0 CTRST Clock Timer Reset Bit in the Clock Timer Control CT_CTL Register D4 0x5000 The counter is also initialized to 0 at initial reset ...

Page 212: ... When both CTRUN and CTRST are set to 1 at the same time the timer starts counting after resetting the counter While the timer is running a cause of interrupt occurs at the falling edge of the 32 Hz 8 Hz 2 Hz and 1 Hz signals If the interrupt has been enabled an interrupt request is sent to the interrupt controller ITC 256 Hz 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz 32 Hz interrupt 8 Hz interr...

Page 213: ...1 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask CT_IMSK Register D0 0x5002 If CTIF is set to 1 the CT module outputs the interrupt request signal to the ITC The interrupt request signal sets the clock timer interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the ITC and S1C17 Core settings The clock timer interrupt handler routine should read the C...

Page 214: ... in the S1C17 Core is set to 1 The clock timer interrupt has a higher interrupt level than the value that is set in the IL field of the PSR No other cause of interrupt having higher priority such as NMI has occurred For details on these interrupt control registers as well as the device operation when an interrupt has occurred see Chapter 6 Interrupt Controller ITC Note The settings shown below are...

Page 215: ...starts stops the timer 0x5001 CT_CNT Clock Timer Counter Register Counter data 0x5002 CT_IMSK Clock Timer Interrupt Mask Register Enables disables interrupt 0x5003 CT_IFLG Clock Timer Interrupt Flag Register Indicates resets interrupt occurrence status The following describes each clock timer register These are all 8 bit registers Note When setting the registers be sure to write a 0 and not a 1 fo...

Page 216: ...served D4 CTRST Clock Timer Reset Bit Resets the clock timer 1 W Reset 0 W Has no effect 0 R Always 0 when read default Writing 1 to this bit resets the counter to 0x0 When the clock timer is reset in Run state it restarts immediately after resetting In Stop state the counter maintains 0x0 D 3 1 Reserved D0 CTRUN Clock Timer Run Stop Control Bit Starts stops the clock timer 1 R W Run 0 R W Stop de...

Page 217: ...This is a read only register so the writing operation is invalid Each bit corresponds to the frequency as follows D7 1 Hz D6 2 Hz D5 4 Hz D4 8 Hz D3 16 Hz D2 32 Hz D1 64 Hz D0 128 Hz Note If this register is read while the counter is running the read value may not represent the current counter value an indefinite value may be read out The counter value should be obtained by one of the following pr...

Page 218: ... Setting CTIE bit to 1 enables the clock timer interrupt request by the falling edge of the corresponding signal setting it to 0 disables the interrupt In addition it is necessary to set the clock timer interrupt enable bit in the ITC to interrupt enabled to actually generate an interrupt D 7 4 Reserved D3 CTIE32 32 Hz Interrupt Enable Bit Enables disables the 32 Hz interrupt 1 R W Enable interrup...

Page 219: ...g of the CT module in the interrupt handler routine this also resets the interrupt flag in the ITC The CTIF flags are reset by writing 1 Note To avoid occurrence of unnecessary interrupts be sure to reset the CTIF flags before the clock timer interrupt is enabled using CTIE D 7 4 Reserved D3 CTIF32 32 Hz Interrupt Flag This is the interrupt flag to indicate the 32 Hz interrupt cause occurrence sta...

Page 220: ...ally enters Stop status Figure 15 7 1 shows the timer operation at start stop CTRUN WR CT_CNT register 0x57 0x58 0x59 0x5a 0x5b 0x5c CTRUN RD 256 Hz Figure 15 7 1 Clock Timer Start Stop Operation If the slp instruction is executed while the clock timer is running CTRUN 1 the clock timer will be unstable immediately after SLEEP status is canceled Therefore the clock timer should be stopped CTRUN 0 ...

Page 221: ... with software Furthermore the stopwatch timer can generate an interrupt using the 100 Hz approximate 100 Hz 10 Hz approximate 10 Hz and 1 Hz signals Figure 16 1 1 shows the structure of the stopwatch timer 256 Hz Internal data bus Interrupt request To ITC Feedback divider 1 100 s 4 bit BCD counter 1 10 s 4 bit BCD counter Count control circuit Interrupt control circuit Run Stop control Interrupt ...

Page 222: ... 10 second counter 1 Hz 1 10 second counter output 25 256 1 100 second counter count up pattern 2 s 26 256 6 25 256 4 1 s 26 256 s 26 256 s 25 256 s 25 256 s 26 256 s 26 256 s 25 256 s 25 256 s 26 256 s 26 256 s s 26 256 3 256 3 256 3 256 2 256 3 256 2 256 3 256 2 256 3 256 2 256 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 1 10 second counter count up pattern Figure 16 2 1 Count up...

Page 223: ... OSC1 clock by 128 Therefore the clock frequency is 256 Hz when the OSC1 clock frequency is 32 768 kHz Be aware that the frequencies described in this chapter change if the OSC1 clock has another frequency The OSC module does not provide a control bit for the 256 Hz clock The 256 Hz clock is always supplied to the stopwatch timer when the OSC1 oscillator is on For control of the OSC1 oscillator se...

Page 224: ...g the Stopwatch Timer To reset the stopwatch timer write 1 to the SWTRST bit D4 SWT_CTL register This initializes the counter to 0 SWTRST Stopwatch Timer Reset Bit in the Stopwatch Timer Control SWT_CTL Register D4 0x5020 The counter is also initialized to 0 at initial reset ...

Page 225: ... are set to 1 at the same time the stopwatch timer starts counting after resetting the counter While the stopwatch timer is running a cause of interrupt occurs at the falling edge of the 100 Hz approximate 100 Hz 10 Hz approximate 10 Hz and 1 Hz signals If the interrupt has been enabled an interrupt request is sent to the interrupt controller ITC BCD100 0 BCD100 1 BCD100 2 BCD100 3 100 Hz interrup...

Page 226: ... D0 0x5022 If SIF is set to 1 the SWT module outputs the interrupt request signal to the ITC The interrupt request signal sets the stopwatch timer interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the ITC and S1C17 Core settings The stopwatch timer interrupt handler routine should read the SIF flags to check the signal that causes occurrence of the interrupt...

Page 227: ...r in the S1C17 Core is set to 1 The stopwatch timer interrupt has a higher interrupt level than the value that is set in the IL field of the PSR No other cause of interrupt having higher priority such as NMI has occurred For details on these interrupt control registers as well as the device operation when an interrupt has occurred see Chapter 6 Interrupt Controller ITC Note The settings shown belo...

Page 228: ...stops the timer 0x5021 SWT_BCNT Stopwatch Timer BCD Counter Register BCD counter data 0x5022 SWT_IMSK Stopwatch Timer Interrupt Mask Register Enables disables interrupt 0x5023 SWT_IFLG Stopwatch Timer Interrupt Flag Register Indicates resets interrupt occurrence status The following describes each stopwatch timer register These are all 8 bit registers Note When setting the registers be sure to wri...

Page 229: ...erved D4 SWTRST Stopwatch Timer Reset Bit Resets the stopwatch timer 1 W Reset 0 W Has no effect 0 R Always 0 when read default Writing 1 to this bit resets the counter to 0x0 When the stopwatch timer is reset in Run state it restarts immediately after resetting In Stop state the counter maintains 0x0 D 3 1 Reserved D0 SWTRUN Stopwatch Timer Run Stop Control Bit Starts stops the stopwatch timer 1 ...

Page 230: ...d Default 0 This is a read only register so the writing operation is invalid D 3 0 BCD100 3 0 1 100 Sec BCD Counter Value The 1 100 second counter data can be read Default 0 This is a read only register so the writing operation is invalid Note If this register is read while the counter is running the read value may not represent the current counter value an indefinite value may be read out The cou...

Page 231: ...Hz 10 Hz and 1 Hz signals individually Setting SIE bit to 1 enables the stopwatch timer interrupt request by the falling edge of the corresponding signal setting it to 0 disables the interrupt In addition it is necessary to set the stopwatch timer interrupt enable bit in the ITC to interrupt enabled to actually generate an interrupt D 7 3 Reserved D2 SIE1 1 Hz Interrupt Enable Bit Enables disables...

Page 232: ...nce status using this register 1 Set the stopwatch timer interrupt trigger mode in the ITC to level trigger 2 After an interrupt occurs reset the interrupt flag of the SWT module in the interrupt handler routine this also resets the interrupt flag in the ITC The SIF flags are reset by writing 1 Note To avoid occurrence of unnecessary interrupts be sure to reset the SIF flags before the stopwatch t...

Page 233: ... enters Stop status Figure 16 8 1 shows the timer operation at start stop SWTRUN WR SWT_BCNT register 27 28 29 30 31 32 SWTRUN RD 256 Hz Figure 16 8 1 Stopwatch Timer Start Stop Operation If the slp instruction is executed while the stopwatch timer is running SWTRUN 1 the stopwatch timer will be unstable immediately after SLEEP status is canceled Therefore the stopwatch timer should be stopped SWT...

Page 234: ...16 STOPWATCH TIMER SWT 16 14 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 235: ...selectable with software is generated and output to the CPU By programming the watchdog timer to be reset within this period so that an NMI reset will not occur it is possible to detect program runaway as if the processing has not been executed Figure 17 1 1 shows the structure of the watchdog timer 256 Hz NMI Reset 10 bit counter Interrupt control circuit Run Stop control NMI reset mode select WD...

Page 236: ...clock by 128 Therefore the clock frequency is 256 Hz when the OSC1 clock frequency is 32 768 kHz Be aware that the frequencies and times described in this chapter change if the OSC1 clock has another frequency The OSC module does not provide a control bit for the 256 Hz clock The 256 Hz clock is always supplied to the watchdog timer when the OSC1 oscillator is on For control of the OSC1 oscillator...

Page 237: ...routine is processed within 131072 fOSC1 second cycles 4 seconds when fOSC1 32 768 kHz After the watchdog counter is reset it starts counting NMI reset generation cycles all over again If the watchdog timer is not reset within the NMI reset generation cycle for some reason the CPU is placed into interrupt handling by an NMI or reset signal In the interrupt handling the CPU reads the interrupt vect...

Page 238: ...r name Function 0x5040 WDT_CTL Watchdog Timer Control Register Resets and starts stops the timer 0x5041 WDT_ST Watchdog Timer Status Register Sets the timer mode and indicates NMI status The following describes each watchdog timer register These are all 8 bit registers Note When setting the registers be sure to write a 0 and not a 1 for all reserved bits ...

Page 239: ...ed D4 WDTRST Watchdog Timer Reset Bit Resets the watchdog timer 1 W Reset 0 W Has no effect 0 R Always 0 when read default When the watchdog timer is used it must be reset by writing 1 to this bit within the NMI reset generation cycle 4 seconds when fOSC1 32 768 kHz The up counter is thereby reset to 0 then starts counting NMI reset generation cycles all over again D 3 0 WDTRUN 3 0 Watchdog Timer ...

Page 240: ... counter overflows 1 R W Reset 0 R W NMI default When this bit is set to 1 a reset signal will be output when the counter overflows When this bit is set to 0 an NMI signal will be output D0 WDTST NMI Status Bit Indicates that an NMI has occurred due to a counter overflow 1 R NMI has occurred counter overflowed 0 R NMI has not occurred default This bit is provided to check if an NMI has occurred by...

Page 241: ...EPSON 17 7 17 5 Precautions When the watchdog timer is used it must be reset within 131072 fOSC1 second cycle 4 seconds when fOSC1 32 768 kHz Reset the watchdog timer before starting thus preventing the generation of unnecessary NMI or reset signals ...

Page 242: ...17 WATCHDOG TIMER WDT 17 8 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 243: ...bit is fixed at one bit In data receive operation overrun framing and parity errors are detectable The UART can generate three types of interrupts transmit buffer empty receive buffer full and receive error this makes it possible to process serial data transfer simply in an interrupt handler Furthermore the UART module contains an RZI modulator demodulator allowing an infrared ray communication ci...

Page 244: ...he I O ports P23 P24 P25 and they are initialized as general purpose I O port pins by default Before using these pins for the UART the pin functions must be switched using the P2_PMUX register Set the control bits shown below to 1 to configure the pins for the serial interface P23 SIN P23MUX P23 Port Function Select Bit in the P2 Port Function Select P2_PMUX Register D3 0x52a2 P24 SOUT P24MUX P24 ...

Page 245: ...rnal clock is selected The UART uses the 8 bit timer output clock as the transfer clock Therefore it is necessary to program the 8 bit timer so that it will output a clock according to the transfer rate See Chapter 12 8 bit Timer T8F for controlling the 8 bit timer External clock When SSCK is set to 1 an external clock is selected Configure the P25 pin as the SCLK pin see Section 18 2 and input an...

Page 246: ...ther the parity function is enabled or not When PREN is set to 0 default parity function is disabled In this case a parity bit will not be added to transfer data and the parity check will not be performed when data is received When PREN is set to 1 parity function is enabled In this case a parity bit will be added to transfer data and the parity check will be performed when data is received When t...

Page 247: ...OUT pin sequentially After the MSB has been output a parity bit if parity is enabled and a stop bit are output The transmitter provides two status flags TDBE D0 UART_ST register and TRBS D2 UART_ST register TDBE Transmit Data Buffer Empty Flag in the UART Status UART_ST Register D0 0x4100 TRBS Transmit Busy Flag in the UART Status UART_ST Register D2 0x4100 The TDBE flag indicates the transmit dat...

Page 248: ...once This reading clears the read data and resets the RDRY flag The buffer status returns to 1 above If the receive data buffer is read twice the second read value is invalid data 3 RDRY 1 RD2B 1 Two data have been received Read the receive data buffer twice The receive data buffer outputs the older received data in the first reading This reading clears the read data and resets the RD2B flag The b...

Page 249: ...rity bit Rd Data read from RXD 7 0 Figure 18 5 2 Data Receive Timing Chart Disabling data transmission reception After data transfer both transmission and reception has finished write 0 to the RXEN bit to disable data transmission reception Always make sure that the TDBE flag is 1 and TRBS and RDRY flags are 0 before data transmission reception is disabled When the RXEN bit is set to 0 the transmi...

Page 250: ... D5 0x4100 Framing error If data with a stop bit 0 is received the UART assumes that the data is out of sync and generates a framing error If two stop bits are used only the first stop bit is checked When this error occurs the framing error flag FER D6 UART_ST register is set to 1 Even when this error occurs the received data in error is loaded to the receive data buffer and the receive operation ...

Page 251: ...cause When TDBE 1 the UART interrupt handler routine can write the next transmit data to the transmit data buffer Receive buffer full interrupt Set the RIEN bit D5 UART_CTL register to 1 when using this interrupt If RIEN is set to 0 default an interrupt request by this cause will not be sent to the ITC RIEN Receive Buffer Full Interrupt Enable Bit in the UART Control UART_CTL Register D5 0x4104 Wh...

Page 252: ...00 Interrupt enable bits IIEN4 UART Interrupt Enable Bit in the Interrupt Enable ITC_EN Register D12 0x4302 Interrupt level setup bits IILV4 2 0 UART Interrupt Level Bits in the Internal Interrupt Level Setup ITC_ILV2 Register 2 D 2 0 0x4312 When the UART outputs an interrupt request pulse the corresponding interrupt flag is set to 1 If the interrupt enable bit corresponding to that interrupt flag...

Page 253: ...put to the demodulator to convert the low pulse width into 16 sclk cycles before input to the shift register for receiving To detect low pulses input to the demodulator minimum pulse width 1 41 µs at 115200 bps the demodulator uses a pulse detection clock selected from the prescaler output clocks separately with the transfer clock sclk S1 Start bit S2 S3 Stop bits P Parity bit sclk irclk Demodulat...

Page 254: ...CLK 1 8 0x2 PCLK 1 4 0x1 PCLK 1 2 0x0 PCLK 1 1 Default 0x0 This clock must be faster than the transfer clock sclk supplied from the 8 bit timer or input from the SCLK pin The demodulator regards a low pulse of which the width is longer than two cycles of the IrDA receive detection clock as a valid low pulse and converts it to a 16 sclk cycles width of low pulse Select an appropriate prescaler outp...

Page 255: ...T_TXD UART Transmit Data Register Transmit data 0x4102 UART_RXD UART Receive Data Register Receive data 0x4103 UART_MOD UART Mode Register Sets transfer data format 0x4104 UART_CTL UART Control Register Controls data transfer 0x4105 UART_EXP UART Expansion Register Sets IrDA mode The following describes each UART register These are all 8 bit registers Note When setting the registers be sure to wri...

Page 256: ...urred 0 R No error has occurred default 1 W Reset to 0 0 W Has no effect When a parity error has occurred PER is set to 1 The parity check function is effective only when PREN D3 UART_MOD register is set to 1 This check is performed when the received data is transferred from the shift register to the receive data buffer PER is reset by writing 1 or when RXEN D0 UART_CTL register is set to 0 D4 OER...

Page 257: ... Data Ready Flag Indicates that the receive data buffer contains valid received data 1 R Data is ready to read out 0 R Buffer is empty default RDRY is set to 1 when received data is loaded to the receive data buffer and is reset to 0 when all data are read out from the receive data buffer D0 TDBE Transmit Data Buffer Empty Flag Indicates the status of the transmit data buffer 1 R Empty default 0 R...

Page 258: ...it data buffer Default 0x0 When data is written to this register the UART starts transmitting The data written to TXD 7 0 enters the transmit data buffer and waits for transmission When the data in the transmit data buffer is transferred a cause of transmit buffer empty interrupt occurs In 7 bit mode TXD7 MSB is ignored The serial converted data is output from the SOUT pin beginning with the LSB i...

Page 259: ...e shift register contains received data an overrun error will occur if the received data is not read by the time the next data receiving begins The receive data buffer status flags RDRY D1 UART_ST register and RD2B D3 UART_ST register are provided to indicate that the receive data buffer contains valid received data and the second data respectively When the receive data buffer has received the num...

Page 260: ...et to 1 the received data is checked for parity A parity bit is automatically added to the transmit data When PREN is set to 0 parity is not checked and no parity bit is added D2 PMD Parity Mode Select Bit Selects the parity mode 1 R W Odd parity 0 R W Even parity default Odd parity is selected by writing 1 to PMD and even parity is selected by writing 0 Parity check and the addition of a parity b...

Page 261: ...es an interrupt request to be output to the ITC when the transmit data written to the transmit data buffer is transferred to the shift register when data transmission starts 1 R W Enable 0 R W Disable default Set this bit to 1 when writing transmit data to the transmit data buffer in the interrupt handler routine D 3 2 Reserved D1 RBFI Receive Buffer Full Interrupt Condition Setup Bit Sets the num...

Page 262: ...ulse detection clock Table 18 9 2 Selecting the IrDA Receive Detection Clock IRCLK 2 0 Prescaler output clock 0x7 PCLK 1 128 0x6 PCLK 1 64 0x5 PCLK 1 32 0x4 PCLK 1 16 0x3 PCLK 1 8 0x2 PCLK 1 4 0x1 PCLK 1 2 0x0 PCLK 1 1 Default 0x0 This clock must be faster than the transfer clock sclk supplied from the 8 bit timer or input from the SCLK pin The demodulator regards a low pulse of which the width is...

Page 263: ...imited to 115200 bps Do not set a transfer rate that exceeds the limit When the RXEN bit is set to 0 to disable transmit receive operations the transmit receive data buffers are cleared initialized Therefore make sure that the buffers do not contain any data waiting for transmission or reading before writing 0 to the RXEN bit The IrDA receive detection clock must be faster than the transfer clock ...

Page 264: ...18 UART 18 22 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 265: ...er and a receive data buffer separately from the shift registers and can generate two types of interrupts transmit data buffer empty and receive data buffer full this makes it possible to process continuous serial data transfers simply in an interrupt handler Figure 19 1 1 shows the structure of the SPI module SDI SPICLK SPISS SDO Shift register Receive data buffer 1 byte SPI clock from 16 bit tim...

Page 266: ...t pins SDI SDO SPICLK SPISS are shared with the I O ports P20 P21 P22 P17 and they are initialized as general purpose I O port pins by default Before using these pins for the SPI the pin functions must be switched using the P2_PMUX and P1_PMUX registers Set the control bits shown below to 1 to configure the pins for the SPI P20 SDI P20MUX P20 Port Function Select Bit in the P2 Port Function Select...

Page 267: ...imers T16 for controlling the timer PCLK 16 bit timer Ch 1 underflow signal SPI clock SPICLK output Figure 19 3 1 SPI Clock in Master Mode In slave mode the SPI module inputs the SPI clock from the SPICLK pin Since the internal circuit operates with the internal PCLK clock the input clock is differentiated and used to sync with the PCLK clock Note The frequency of the clock input from the SPICLK p...

Page 268: ...ansfer using the internal clock In slave mode the SPI performs data transfer using a clock input from the master device MSSL Master Slave Mode Select Bit in the SPI Control SPI_CTL Register D1 0x4326 Setting the SPI clock polarity and phase Use CPOL D2 SPI_CTL register to select the SPI clock polarity The SPI clock is configured as active low when CPOL is set to 1 or active high when CPOL is set t...

Page 269: ...is transmitted first CPHA Clock Phase Select Bit in the SPI Control SPI_CTL Register D3 0x4326 CPOL Clock Polarity Select Bit in the SPI Control SPI_CTL Register D2 0x4326 The SPI module provides two status flags for data transmit control SPTBE D0 SPI_ST register and SPBSY D2 SPI_ST register SPTBE Transmit Data Buffer Empty Flag in the SPI Status SPI_ST Register D0 0x4320 SPBSY Transfer Busy Flag ...

Page 270: ...r see Figure 19 4 1 The MSB of data is received first When eight data bits are received in the shift register the received data is loaded into the receive data buffer The received data in the buffer can be read from the SPI_RXD register 0x4324 SPI_RXD SPI Receive Data Register 0x4324 The SPI module provides the SPRBF flag D1 SPI_ST register for data receive control SPRBF Receive Data Buffer Full F...

Page 271: ...t Disabling data transmission reception After data transfer both transmission and reception has finished write 0 to the SPEN bit to disable data transmission reception Always make sure that the SPTBE flag is 1 and SPRBF flag is 0 before data transmission reception is disabled When the SPEN bit is set to 0 the transmit and receive data buffers are placed in empty status data is cleared if any remai...

Page 272: ...nterrupt request by this cause will not be sent to the ITC SPRIE Receive Data Buffer Full Interrupt Enable Bit in the SPI Control SPI_CTL Register D5 0x4326 When data received in the shift register is loaded to the receive data buffer the SPI module sets the SPRBF bit D1 SPI_ST register to 1 to indicate that the received data buffer is full At the same time the SPI module outputs an interrupt requ...

Page 273: ...t to 1 The SPI interrupt has a higher interrupt level than the value that is set in the IL field of the PSR No other cause of interrupt having higher priority such as NMI has occurred For details on these interrupt control registers as well as the device operation when an interrupt has occurred see Chapter 6 Interrupt Controller ITC Interrupt vector The following shows the vector number and vector...

Page 274: ...a 0x4324 SPI_RXD SPI Receive Data Register Receive data 0x4326 SPI_CTL SPI Control Register Sets the SPI mode and enables data transfer The following describes each SPI register These are all 16 bit registers Notes When setting the registers be sure to write a 0 and not a 1 for all reserved bits Be sure to use 16 bit access instructions for reading writing from to the SPI registers The SPI registe...

Page 275: ... SPISS signal status 1 R Low level this SPI is selected 0 R High level this SPI is deselected default SPBSY is set to 1 when the master device activates the SPISS signal to select this SPI module slave device and is reset to 0 when the master device negates the SPISS signal to deselect this SPI module D1 SPRBF Receive Data Buffer Full Flag Indicates the receive data buffer status 1 R Full 0 R Not ...

Page 276: ...e data transmission begins by writing data to this register In slave mode the register contents are transferred to the shift register to start data transmission when a clock is input from the master device SPTBE D0 SPI_ST register is set to 1 empty when the data is transferred to the shift register At the same time a cause of transmit data buffer empty interrupt occurs The next transmit data can b...

Page 277: ... is loaded to the receive data buffer SPRBF D1 SPI_ST register is set to 1 buffer full At the same time a cause of receive data buffer full interrupt occurs Thereafter the data can be read out at any time before a receive operation for the next data is completed If the next data receive operation is completed before this register is read out the data in it is overwritten with the newly received da...

Page 278: ...uffer receive operation completed When SPRIE is set to 0 SPI interrupts caused by receive data full are not generated D4 SPTIE Transmit Data Buffer Empty Interrupt Enable Bit Enables disables SPI interrupt caused by transmit data buffer empty 1 R W Enable 0 R W Disable default When SPTIE is set to 1 SPI transmit data buffer empty interrupt requests to the ITC are enabled A transmit data buffer emp...

Page 279: ...erforms data transfer using the clock generated by the 16 bit timer Ch 1 In slave mode the SPI performs data transfer using a clock input from the master device D0 SPEN SPI Enable Bit Enables disables operation of the SPI module 1 R W Enable 0 R W Disable default When SPEN is set to 1 the SPI module is activated and data transfer is enabled When SPEN is set to 0 the SPI module goes off Note Make s...

Page 280: ...ting from to the SPI registers 0x4320 to 0x4326 The SPI registers do not allow reading writing using 32 bit and 8 bit access instructions Do not access the SPI_CTL register 0x4326 while the SPBSY flag D2 SPI_ST register is set to 1 during data transfer SPBSY Transfer Busy Flag in the SPI Status SPI_ST Register D2 0x4320 ...

Page 281: ...e data transfer Also it can generate two types of interrupts transmit buffer empty and receive buffer full interrupts this makes it possible to process continuous serial data transfer simply in an interrupt handler Figure 20 1 1 shows the structure of the I2C module Shift register SDA SDA SCL SCL I2C clock from 16 bit timer Ch 2 Internal bus ITC I2C Bus I F and control registers Shift register Clo...

Page 282: ...I2C input output pins SDA SCL are shared with the I O ports P14 P15 and they are initialized as general purpose I O port pins by default Before using these pins for the I2C the pin functions must be switched using the P1_PMUX register Set the control bits shown below to 1 to configure the pins for the I2C P14 SDA P14MUX P14 Port Function Select Bit in the P1 Port Function Select P1_PMUX Register D...

Page 283: ... register and is output from the SCL pin to the slave I2C device Program the 16 bit timer Ch 2 so that it will output a clock according to the transfer rate Refer to Chapter 11 16 bit Timers T16 for controlling the 16 bit timer The I2C module does not function as a slave device The SCL input is used to check the SCL status of the I2C bus but it is not used to input synchronous clock ...

Page 284: ...ove function The I2C module contains a function to remove noise from the SDA and SCL input signals This function is enabled by setting NSERM D4 I2C_CTL register to 1 Note however that the I2C clock 16 bit timer Ch 2 output clock frequency must be a 1 6 of PCLK or lower to use the noise remove function NSERM Noise Remove On Off Bit in the I2C Control I2C_CTL Register D4 0x4342 ...

Page 285: ... 5 2 2 Set TXE D9 I2C_DAT register to 1 3 Set STRT D0 I2C_CTL register to 1 RTDT 7 0 Receive Transmit Data Bits in the I2C Data I2C_DAT Register D 7 0 0x4344 TXE Transmit Execution Bit in the I2C Data I2C_DAT Register D9 0x4344 STRT Start Control Bit in the I2C Control I2C_CTL Register D0 0x4342 This procedure generates the communication waveforms as shown in Items 2 and 3 below Be sure to follow ...

Page 286: ... The slave address should be sent in the same way To transmit byte data set the data to the RTDT 7 0 bits D 7 0 I2C_DAT register At the same time set the TXE bit D9 I2C_DAT register to 1 to execute one byte data transmission RTDT 7 0 Receive Transmit Data Bits in the I2C Data I2C_DAT Register D 7 0 0x4344 TXE Transmit Execution Bit in the I2C Data I2C_DAT Register D9 0x4344 When the TXE bit is set...

Page 287: ... received in the shift register the received data is loaded into RTDT 7 0 The I2C module provides two status bits for data receive control RBRDY D11 I2C_DAT register and RBUSY D9 I2C_CTL register RBRDY Receive Buffer Ready Bit in the I2C Data I2C_DAT Register D11 0x4344 RBUSY Receive Busy Flag in the I2C Control I2C_CTL Register D9 0x4342 The RBRDY flag indicates the received data status it goes 1...

Page 288: ...ta and ACK transfer have finished the I2C module fixes the SCL output at low and enters wait state The wait state will be canceled by writing 1 to TXE or RXE to resume data transmission reception or by writing 1 to STP to generate a STOP condition Disabling data transmission reception After data transfer both transmission and reception has finished write 0 to the I2CEN bit to disable data transmis...

Page 289: ...ta transmission ACK reception ACK received Figure 20 5 6 I2C Timing Chart 2 data transmission STOP condition A6 valid shift shift shift shift shift shift shift shift shift A 6 0 DIR A5 A4 A3 A2 A1 A0 D7 D6 DIR 0 ACK Register settings Start communication Start transmission Start reception START condition Slave address transmission Data reception ACK reception PCLK T16 Ch 2 output SCL input SCL outp...

Page 290: ...on Continuous data reception ACK transmission ACK Figure 20 5 8 I2C Timing Chart 4 data reception STOP condition Set transmit data and TXE Wait ACK reception Start transmission Interrupt generation Register settings Start communication Interrupt generation Slave address transmission Data transmission PCLK T16 Ch 2 output SCL input SCL output SDA input SDA output STRT STP TXE RXE TBUSY RBUSY RBRDY ...

Page 291: ...fault an interrupt request by this cause will not be sent to the ITC RINTE Receive Interrupt Enable Bit in the I2C Interrupt Control I2C_ICTL Register D1 0x4346 When data received in the shift register is loaded to RTDT 7 0 the I2C module outputs an interrupt request pulse to the ITC if the receive buffer full interrupt has been enabled RINTE 1 If other interrupt conditions are satisfied an interr...

Page 292: ... set to 1 The I2C interrupt has a higher interrupt level than the value that is set in the IL field of the PSR No other cause of interrupt having higher priority such as NMI has occurred For details on these interrupt control registers as well as the device operation when an interrupt has occurred see Chapter 6 Interrupt Controller ITC Interrupt vector The following shows the vector number and vec...

Page 293: ...ransfer status 0x4344 I2C_DAT I2C Data Register Transmit receive data 0x4346 I2C_ICTL I2C Interrupt Control Register Controls the I2C interrupt The following describes each I2C register These are all 16 bit registers Notes When setting the registers be sure to write a 0 and not a 1 for all reserved bits Be sure to use 16 bit access instructions for reading writing from to the I2C registers The I2C...

Page 294: ... Register I2C_EN 0x4340 16 bits D15 1 reserved 0 when being read D0 I2CEN I2C enable 1 Enable 0 Disable 0 R W D 15 1 Reserved D0 I2CEN I2C Enable Bit Enables disables operation of the I2C module 1 R W Enable 0 R W Disable default When I2CEN is set to 1 the I2C module is activated and data transfer is enabled When I2CEN is set to 0 the I2C module goes off ...

Page 295: ...tays 1 while data transmission is in progress TBUSY is reset to 0 upon completion of transmit operation Also TBUSY returns to 0 in wait state D 7 5 Reserved D4 NSERM Noise Remove On Off Bit Turns the noise remove function on and off 1 R W On 0 R W Off default The I2C module contains a function to remove noise from the SDA and SCL input signals This function is enabled by setting NSERM to 1 Note ho...

Page 296: ...t high to generate a START condition on the I2C bus This makes the I2C bus in busy status To generate a START condition set the following registers in the order shown below 1 Set the slave address to RTDT 7 0 D 7 0 I2C_DAT register First transmit data when 10 bit address is used see Figure 20 5 2 2 Set TXE D9 I2C_DAT register to 1 3 Set STRT D0 I2C_CTL register to 1 STRT is automatically reset to ...

Page 297: ...nore default The I2C module starts data reception for one byte by setting RXE to 1 and TXE D9 to 0 RXE can be set to 1 for the next data reception even if a slave address is being transmitted or data is being received RXE is reset to 0 when D6 is input to the shift register D9 TXE Transmit Execution Bit Execute a data transmission for one byte 1 R W Start data transmission 0 R W Ignore default Set...

Page 298: ...data can be read from this register Default 0x0 Data reception begins when RXE D10 is set to 1 If a slave address is being transmitted or data is being received a new reception starts after the current reception has completed When a receive operation is completed and the data received in the shift register is loaded to this register the RBRDY flag D11 is set and a cause of receive buffer full inte...

Page 299: ...ve buffer full interrupt requests to the ITC are enabled A receive buffer full interrupt request occurs when the data received in the shift register is loaded to RTDT 7 0 D 7 0 I2C_DAT register receive operation completed When RINTE is set to 0 an I2C receive buffer full interrupt is not generated D0 TINTE Transmit Interrupt Enable Bit Enables disables the I2C transmit buffer empty interrupt 1 R W...

Page 300: ...20 I2C 20 20 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 301: ...a with a designated carrier length and an edge detector for detecting rising and falling edges from the input signal Also the REMC module can generate three types of interrupts counter underflow interrupt to notify that a transmission for designated data length has finished and input rising edge detection and falling edge detection interrupts for data receive processing Figure 21 1 1 shows the str...

Page 302: ...t output pins REMI REMO are shared with the I O ports P04 P05 and they are initialized as general purpose I O port pins by default Before using these pins for the REMC the pin functions must be switched using the P0_PMUX register Set the control bits shown below to 1 to configure the pins for the REMC P04 REMI P04MUX P04 Port Function Select Bit in the P0 Port Function Select P0_PMUX Register D4 0...

Page 303: ...256 0x0 PCLK 1 1 Default 0x0 For controlling the prescaler see Chapter 9 Prescaler PSC Note Before the REMC module can be used the prescaler must be run The lengths of H period and L period of the carrier signal can be set using REMCH 5 0 D 5 0 REMC_CARH register and REMCL 5 0 D 5 0 REMC_CARL register The H L period lengths should be set as the number of clock selected as above cycles 1 REMCH 5 0 ...

Page 304: ...t interrupt caused by an input transition occurs The input data pulse width can be obtained from the difference between 0xff and the read value As in the case of the carrier generator the data length counter uses a prescaler output clock as the count clock Use the LCCLK 3 0 bits D 3 0 REMC_PSC register provided separately with the carrier generator to select one of the 15 prescaler output clocks L...

Page 305: ...MC in data transmit mode REMMD REMC Mode Select Bit in the REMC Configuration REMC_CFG Register D1 0x5340 2 Enabling data transmission Set REMEN D0 REMC_CFG register to 1 to enable the REMC operation This makes the REMC start the data transmit operation To prevent unnecessary data from being transmitted set REMDT D0 REMC_ST register to 0 and REMLEN 7 0 D 7 0 REMC_LCNT register to 0x0 before writin...

Page 306: ...LK PSC output clock Data length counter clock REMI input REMDT Sampled waveform REMRIF REMFIF Interrupt signal REMLEN 7 0 Write 0xff x 2 x 1 x 0xff 0xfe 0xfd 0xff Write 0xff Write 1 Write 1 Figure 21 5 3 Data Reception 1 Setting data receive mode Write 1 to REMMD D1 REMC_CFG register to set the REMC in data receive mode 2 Enabling data reception Set REMEN D0 REMC_CFG register to 1 to enable the RE...

Page 307: ...falling edge or rising edge interrupt occurs Read the data length counter at that point The data length can be calculated from the difference between 0xff and the read value To continue data reception set the data length counter to 0xff again and wait until the next interrupt If the data length counter reaches 0 without an interrupt generated after the counter is set to 0xff either no receive data...

Page 308: ...et the ITC and S1C17 Core settings The REMC interrupt handler routine should read the REMUIF flag to check if the interrupt has occurred due to a data length counter underflow or another cause Furthermore the interrupt handler routine must reset write 1 to REMUIF in the REMC module as well as the REMC interrupt flag in the ITC to clear the cause of interrupt Rising edge interrupt This interrupt re...

Page 309: ...pt condition settings shown above the REMC module asserts the interrupt signal sent to the ITC To generate a REMC interrupt set the interrupt level and enable the interrupt using the ITC registers The following shows the control bits for the REMC interrupt in the ITC Interrupt flag in the ITC IIFT5 Remote Controller Interrupt Flag in the Interrupt Flag ITC_IFLG Register D13 0x4300 Interrupt enable...

Page 310: ...Sets up the H period of the carrier 0x5343 REMC_CARL REMC L Carrier Length Setup Register Sets up the L period of the carrier 0x5344 REMC_ST REMC Status Register Transmit receive bit 0x5345 REMC_LCNT REMC Length Counter Register Sets the transmit receive data length 0x5346 REMC_IMSK REMC Interrupt Mask Register Enables disables interrupt 0x5347 REMC_IFLG REMC Interrupt Flag Register Indicates rese...

Page 311: ...ive 0 Transmit 0 R W D0 REMEN REMC enable 1 Enable 0 Disable 0 R W D 7 2 Reserved D1 REMMD REMC Mode Select Bit Selects the data transmit receive direction 1 R W Reception 0 R W Transmission default D0 REMEN REMC Enable Bit Enables or disables the REMC module to transmit receive data 1 R W Enable 0 R W Disable default When REMEN is set to 1 the REMC module starts data transmission or data receptio...

Page 312: ...caler output clocks Table 21 7 2 Selecting the Carrier Generator Clock CGCLK 3 0 Prescaler output clock CGCLK 3 0 Prescaler output clock 0xf Reserved 0x7 PCLK 1 128 0xe PCLK 1 16384 0x6 PCLK 1 64 0xd PCLK 1 8192 0x5 PCLK 1 32 0xc PCLK 1 4096 0x4 PCLK 1 16 0xb PCLK 1 2048 0x3 PCLK 1 8 0xa PCLK 1 1024 0x2 PCLK 1 4 0x9 PCLK 1 512 0x1 PCLK 1 2 0x8 PCLK 1 256 0x0 PCLK 1 1 Default 0x0 D 3 0 LCCLK 3 0 Le...

Page 313: ...eriod length should be set as the number of carrier generator clock cycles 1 The carrier generator clock is selected with CGCLK 3 0 D 7 4 REMC_PSC register The H carrier length is calculated by the expression below REMCH 1 H carrier length s clk_in REMCH H carrier length register data clk_in Prescaler output clock frequency The L period length is specified with REMCL 5 0 D 5 0 REMC_CARL register T...

Page 314: ...ier Length Setup Bits Sets the L period length of the carrier signal Default 0x0 The L period length should be set as the number of carrier generator clock cycles 1 The carrier generator clock is selected with CGCLK 3 0 D 7 4 REMC_PSC register The L carrier length is calculated by the expression below REMCL 1 L carrier length s clk_in REMCL L carrier length register data clk_in Prescaler output cl...

Page 315: ...a 1 1 H 0 0 L 0 R W D 7 1 Reserved D0 REMDT Transmit Receive Data Bit Set transmit data during data transmission Read the received data from this bit during data reception 1 R W 1 H 0 R W 0 L default When REMEN D0 REMC_CFG register is set to 1 the REMC module modulates the REMDT set value with the carrier signal and outputs the modulated signal from the REMO pin during data transmission During dat...

Page 316: ... data transmission During data transmission set the transmit data By writing a value equivalent to the data pulse width to this register the data length counter starts counting down from the set value and stops after generating a cause of underflow interrupt when the counter reaches 0 The next transmit data can be set using this interrupt During data reception During data reception an interrupt ca...

Page 317: ...dividually Setting an interrupt enable bit to 1 enables the interrupt request by the corresponding cause of interrupt setting it to 0 disables the interrupt In addition it is necessary to set the REMC interrupt enable bit in the ITC to interrupt enabled to actually generate an interrupt D 7 3 Reserved D2 REMFIE Falling Edge Interrupt Enable Bit Enables or disables the interrupt by detecting the fa...

Page 318: ...to 1 and an interrupt occurs if other interrupt conditions meet the ITC and S1C17 Core settings Note To avoid occurrence of unnecessary interrupts be sure to reset the interrupt flag before the REMC interrupt is enabled using the interrupt enable bit D 7 3 Reserved D2 REMFIF Falling Edge Interrupt Flag This is the interrupt flag to indicate the falling edge interrupt cause occurrence status 1 R Ca...

Page 319: ...21 REMOTE CONTROLLER REMC S1C17704 TECHNICAL MANUAL EPSON 21 19 21 8 Precaution Before the REMC module can start operating the prescaler must be run ...

Page 320: ...21 REMOTE CONTROLLER REMC 21 20 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 321: ...iver and the drive power supply COM0 COM31 SEG0 SEG55 LCLK OSC3 OSC1 Divider 1 32 1 512 Gate LC 3 0 DSPAR DSPC 1 0 LDUTY 1 0 DSPREV SEGREV COMREV OSC To ITC Frame interrupt request VC1 VC5 VDD VD2 Power voltage booster LCD system voltage regulator LCD contrast adjustment circuit Display memory Driver control circuit Clock control circuit FRMIE Interrupt control circuit Power supply circuit LCD dri...

Page 322: ... 2 LCD Power Supply The S1C17704 generates the LCD drive voltages VC1 to VC5 using the on chip LCD system voltage regulator and power voltage booster It is not necessary to supply external voltage For details of the LCD power supply see Chapter 4 Power Supply ...

Page 323: ...nerated in the LCD clock generator in the OSC module For details of the OSC module see Chapter 7 Oscillator OSC 22 3 2 Frame Signal The frame signal is generated by dividing LCLK by 1024 The frame frequency is determined as follows One frame period shown in Figures 22 4 1 and 22 4 2 is assumed as a frame frequency When OSC1 32 768 kHz typ is selected as the clock source Frame frequency 64 Hz typ W...

Page 324: ...etting the Drive Duty LDUTY 1 0 Duty Effective COM pins Effective SEG pins Max number of pixels 0x3 Reserved 0x2 1 32 COM0 COM31 SEG0 SEG55 1 792 pixels 0x1 1 16 COM0 COM15 SEG0 SEG71 1 152 pixels 0x0 Reserved Default 0x2 The COM16 COM31 SEG71 SEG56 pins are configured as common output pins when 1 32 duty is selected or configured as segment output pins when 1 16 duty is selected The drive bias is...

Page 325: ... VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS GND VC1 VC2 VC3 VC4 VC5 VC5 VC4 VC3 VC2 VC1 VSS GND VC1 VC2 VC3 VC4 VC5 31 3 2 1 0 31 3 2 1 0 FR COM0 COM1 COM2 SEG0 SEG1 COM0 SEG0 COM0 SEG1 COM0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SEG0 1 2 3 4 1 frame Frame interrupt Frame interrupt Figure 22 4 1 Drive Waveform for 1 32 Duty ...

Page 326: ...C5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS GND VC1 VC2 VC3 VC4 VC5 VC5 VC4 VC3 VC2 VC1 VSS GND VC1 VC2 VC3 VC4 VC5 15 3 2 1 0 15 3 2 1 0 FR COM0 COM1 COM2 SEG0 SEG1 COM0 SEG0 COM0 SEG1 1 frame Frame interrupt Frame interrupt Figure 22 4 2 Drive Waveform for 1 16 Duty ...

Page 327: ...addresses unused for display can be used as general purpose read write memory Display area Unused area general purpose memory Address upper 16 bits 0x800 0x801 0x802 0x803 0x804 0x805 COMREV 1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COMREV 0 COM31 COM30 COM2...

Page 328: ...a when 1 16 duty is selected When 1 16 duty is selected for the drive duty two screen areas are reserved in the display memory and the area to be displayed can be selected using DSPAR D5 LCD_DCTL register When DSPAR is set to 0 display area 0 is selected when it is set to 1 display area 1 is selected DSPAR Display Memory Area Control Bit in the LCD Display Control LCD_DCTL Register D5 0x50a0 SEG p...

Page 329: ...nitial resetting DSPC 1 0 is not reset to 0x0 display off on execution of a slp command DSPC 1 0 should be reset to 0x0 display off via software before executing a slp command since switching to SLEEP mode with the LCD display left on will degrade the LCD 22 6 2 LCD Contrast Adjustment The LCD contrast can be adjusted in 16 steps This facility is achieved to control the VC1 to VC5 voltages output ...

Page 330: ...ontrolling the pixels on and off using this interrupt gray scale display can be realized Gray levels that can be produced depend on the LCD panel characteristics The gray scale display should be performed by controlling the frame frequency and the frame cycles to turn the pixel on and off according to the panel characteristics See Section 22 7 for the frame interrupt ...

Page 331: ... of the frame signal To generate an LCD interrupt set the interrupt level and enable the interrupt using the ITC registers The following shows the control bits for the LCD interrupt in the ITC Interrupt flag in the ITC EIFT6 LCD Interrupt Flag in the Interrupt Flag ITC_IFLG Register D6 0x4300 Interrupt enable bit in the ITC EIEN6 LCD Interrupt Enable Bit in the Interrupt Enable ITC_EN Register D6 ...

Page 332: ...the LCD module 1 Set the LCD interrupt trigger mode in the ITC to level trigger 2 After an interrupt occurs reset the LCD interrupt flag FRMIF of the LCD module in the interrupt handler routine this also resets the interrupt flag in the ITC Interrupt vector The following shows the vector number and vector address for the LCD interrupt Vector number 10 0x0a Vector address 0x8028 ...

Page 333: ...r Controls the LCD clock duty 0x50a3 LCD_VREG LCD Voltage Regulator Control Register Controls the LCD drive voltage regulator 0x50a4 LCD_PWR LCD Power Voltage Booster Control Register Controls the LCD voltage booster 0x50a5 LCD_IMSK LCD Interrupt Mask Register Enables disables interrupt 0x50a6 LCD_IFLG LCD Interrupt Flag Register Indicates resets interrupt occurrence status The following describes...

Page 334: ...Figures 22 5 1 and 22 5 2 D6 COMREV Common Output Assignment Control Bit Reverses the memory bit allocation for the COM terminals 1 R W Normal default 0 R W Reverse When COMREV is 1 default the display memory bits are allocated to the COM pins in ascending order when COMREV is set to 0 the addresses are allocated in descending order See Figures 22 5 1 and 22 5 2 D5 DSPAR Display Memory Area Contro...

Page 335: ... VC1 to VC5 pins go to VSS level All on off display is achieved by directly changing the LCD drive waveform to on or off and it does not affect the display memory data The COM pins output a dynamic drive waveform when All on is selected or output a static drive waveform when All off is selected This facility allows the program to blink screen without altering the display memory data DSPC 1 0 is re...

Page 336: ...D contrast adjustment LC 3 0 Display 0x0 R W 0xf 0x0 Dark Light D 7 4 Reserved D 3 0 LC 3 0 LCD Contrast Adjustment Bits Adjusts the LCD contrast This facility is achieved to control the VC1 to VC5 voltages output from the LCD system voltage regulator Table 22 8 3 LCD Contrast Adjustment LC 3 0 Contrast 0xf High dark 0xe 0x1 0x0 Low light Default 0x0 At initial reset LC 3 0 is set to 0x0 Initializ...

Page 337: ...ed 0 when being read D1 0 LDUTY 1 0 LCD duty select LDUTY 1 0 Duty 0x2 R W 0x3 0x2 0x1 0x0 reserved 1 32 1 16 reserved D 7 2 Reserved D 1 0 LDUTY 1 0 LCD Duty Select Bits Selects a drive duty Table 22 8 4 Setting the Drive Duty LDUTY 1 0 Duty Effective COM pins Effective SEG pins Max number of pixels 0x3 Reserved 0x2 1 32 COM0 COM31 SEG0 SEG55 1 792 pixels 0x1 1 16 COM0 COM15 SEG0 SEG71 1 152 pixe...

Page 338: ...s Bit Name Function Setting Init R W Remarks LCD Voltage Regulator Control Register LCD_VREG 0x50a3 8 bits D7 5 reserved 0 when being read D4 LHVLD LCD heavy load protection mode 1 On 0 Off 0 R W D3 0 reserved 0 when being read For details of the control bits see 0x50a3 LCD Voltage Regulator Control Register LCD_VREG in Section 4 5 ...

Page 339: ...nction Setting Init R W Remarks LCD Power Voltage Booster Control Register LCD_PWR 0x50a4 8 bits D7 2 reserved 0 when being read D1 VDSEL Regulator power source select 1 VD2 0 VDD 0 R W D0 PBON Power voltage booster control 1 On 0 Off 0 R W For details of the control bits see 0x50a4 LCD Power Voltage Booster Control Register LCD_PWR in Section 4 5 ...

Page 340: ...FRMIE Frame signal interrupt enable 1 Enable 0 Disable 0 R W D 7 1 Reserved D0 FRMIE Frame Signal Interrupt Enable Bit Enables disables the frame interrupt 1 R W Enable interrupt 0 R W Disable interrupt default Setting FRMIE to 1 enables the LCD module to request interrupts to the ITC setting to 0 disables the interrupt In addition it is necessary to set the LCD interrupt enable bits in the ITC to...

Page 341: ... interrupt flag is set to 1 at the rising edge of the frame signal If FRMIE D0 LCD_IMSK register has been set to 1 at this time the LCD interrupt request signal is output to the ITC The interrupt request signal sets the LCD interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the ITC and S1C17 Core settings The settings shown below are required to manage the ca...

Page 342: ...MANUAL 22 9 Precautions To avoid occurrence of unnecessary interrupts be sure to reset FRMIF D0 LCD_IFLG register before the LCD interrupt is enabled using FRMIE D0 LCD_IMSK register For precautions on the LCD power supply see Section 4 6 Precautions ...

Page 343: ...he circuit on and off to set an evaluate voltage level and to read the detection results Also it can generate an interrupt when voltage drop has been detected Figure 23 1 1 shows the structure of the SVD module VDD Internal data bus SVD interrupt request To ITC Voltage comparator Interrupt control circuit Compare voltage setup circuit Detection result SVDDT SVD SVDC 3 0 Interrupt enable SVDIE SVD ...

Page 344: ...r than the compare voltage The compare voltage can be selected from the 13 levels listed in Table 23 2 1 using SVDC 3 0 D 3 0 SVD_CMP register SVDC 3 0 SVD Compare Voltage Select Bits in the SVD Compare Voltage SVD_CMP Register D 3 0 0x5101 Table 23 2 1 Setting the Compare Voltage SVDC 3 0 Compare voltage 0xf 2 7 V 0xe 2 6 V 0xd 2 5 V 0xc 2 4 V 0xb 2 3 V 0xa 2 2 V 0x9 2 1 V 0x8 2 05 V 0x7 2 0 V 0x...

Page 345: ...ur when the supply voltage drops under the compare voltage and it sets the detection result to 1 By using this interrupt the application program can display for battery exhaustion or setting heavy load protection mode See the subsequent section for control of the interrupt When an interrupt occurs due to temporary voltage sags it will not be canceled even if the voltage returns over the compare vo...

Page 346: ...E ITC registers for SVD interrupt When the SVD module has detected supply voltage drop the SVD asserts the interrupt signal sent to the ITC according to the interrupt condition settings shown above To generate an SVD interrupt set the interrupt level and enable the interrupt using the ITC registers The following shows the control bits for the SVD interrupt in the ITC Interrupt flag in the ITC EIFT...

Page 347: ...flag in the SVD module 1 Set the SVD interrupt trigger mode in the ITC to level trigger 2 After an interrupt occurs reset the SVDIF interrupt flag of the SVD module in the interrupt handler routine this also resets the interrupt flag in the ITC Interrupt vector The following shows the vector number and vector address for the SVD interrupt Vector number 9 0x09 Vector address 0x8024 ...

Page 348: ...VD_CMP SVD Compare Voltage Register Sets compare voltage 0x5102 SVD_RSLT SVD Detection Result Register Voltage detection results 0x5103 SVD_IMSK SVD Interrupt Mask Register Enables disables interrupt 0x5104 SVD_IFLG SVD Interrupt Flag Register Indicates resets interrupt occurrence status The following describes each SVD register These are all 8 bit registers Note When setting the registers be sure...

Page 349: ...1 R W Enable 0 R W Disable default The SVD module starts operating to detect the supply voltage level by setting SVDEN to 1 and stops when it is set to 0 Notes After the SVD module starts operating 500 µs max is required until a stable detection result can be read When reading the detection results without using an interrupt wait for the stabilization time before reading SVDDT D0 SVD_RSLT register...

Page 350: ...2 V 2 1 V 2 05 V 2 0 V 1 95 V 1 9 V 1 85 V 1 8 V D 7 4 Reserved D 3 0 SVDC 3 0 SVD Compare Voltage Select Bits Selects a compare voltage for detecting supply voltage drop from the 13 levels Table 23 5 2 Setting the Compare Voltage SVDC 3 0 Compare voltage 0xf 2 7 V 0xe 2 6 V 0xd 2 5 V 0xc 2 4 V 0xb 2 3 V 0xa 2 2 V 0x9 2 1 V 0x8 2 05 V 0x7 2 0 V 0x6 1 95 V 0x5 1 9 V 0x4 1 85 V 0x3 1 8 V 0x2 to 0x0 ...

Page 351: ...ing read D0 SVDDT SVD detection result 1 Low 0 Normal R D 7 1 Reserved D0 SVDDT SVD Detection Result Bit Indicates the supply voltage detection results 1 R Supply voltage VDD Compare voltage 0 R Supply voltage VDD Compare voltage The SVD module keeps comparing the supply voltage VDD and the voltage level set with SVDC 3 0 D 3 0 SVD_CMP register while SVDEN D0 SVD_EN register is set to 1 By reading...

Page 352: ... read D0 SVDIE SVD interrupt enable 1 Enable 0 Disable 0 R W D 7 1 Reserved D0 SVDIE SVD Interrupt Enable Bit Enables disables the supply voltage drop interrupt 1 R W Enable interrupt 0 R W Disable interrupt default Setting SVDIE to 1 enables the SVD module to request interrupts to the ITC setting to 0 disables the interrupt In addition it is necessary to set the SVD interrupt enable bits in the I...

Page 353: ...e The interrupt flag is set to 1 when the SVD module has detected supply voltage drop If SVDIE D0 SVD_IMSK register has been set to 1 at this time the SVD interrupt request signal is output to the ITC The interrupt request signal sets the SVD interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the ITC and S1C17 Core settings The settings shown below are requir...

Page 354: ...t wait for the stabilization time before reading SVDDT D0 SVD_RSLT register after writing 1 to SVDEN D0 SVD_EN register The SVD operation increases current consumption Therefore set SVDEN D0 SVD_EN register to 0 to disable the SVD operation if supply voltage detection is not necessary To avoid occurrence of unnecessary interrupts be sure to reset the SVDIF flag D0 SVD_IFLG register before the SVD ...

Page 355: ... 24 1 1 List of Debug Pins Pin name I O Size Function DCLK P31 O 1 On chip debugger clock output pin This pin outputs a clock to the ICD Mini S5U1C17001H DSIO P33 I O 1 On chip debugger data input output pin This pin inputs outputs data for debugging and inputs a break signal DST2 P32 O 1 On chip debugger status signal output pin This pin outputs the processor status during debugging The on chip d...

Page 356: ...aler output clock The prescaler provides PRUND D1 PSC_CTL register for specifying prescaler operating condition in debug mode When PRUND is set to 1 the prescaler operates in debug mode This allows the above peripheral modules to operate When PRUND is 0 default the prescaler and above peripheral modules stop operating when the S1C17 Core enters debug mode PRUND Prescaler Run Stop Setting in Debug ...

Page 357: ...egister name Function 0x5322 MISC_OSC1 OSC1 Peripheral Control Register Selects the OSC1 peripheral operation in debug mode 0xffff90 DBRAM Debug RAM Base Register Indicates the debug RAM base address The following describes the registers for debugging individually Note When setting the registers be sure to write a 0 and not a 1 for all reserved bits ...

Page 358: ...ing read D0 O1DBG OSC1 peripheral control in debug mode 1 Run 0 Stop 0 R W D 7 1 Reserved D0 O1DBG OSC1 Peripheral Control in Debug Mode Bit Sets the operating condition for the OSC1 peripheral modules in debug mode 1 R W Operate 0 R W Stop default The following lists the OSC1 peripheral modules that operate with the OSC1 clock Clock timer Watchdog timer Stopwatch timer Note that the 8 bit OSC1 ti...

Page 359: ...tion Setting Init R W Remarks Debug RAM Base Register DBRAM 0xffff90 32 bits D31 24 Unused fixed at 0 0x0 0x0 R D23 0 DBRAM 23 0 Debug RAM base address 0xfc0 0xfc0 R D 31 24 Unused fixed at 0 D 23 0 DBRAM 23 0 Debug RAM Base Address Bits This is a read only register that contains the start address of a work area 64 bytes for debugging ...

Page 360: ...24 ON CHIP DEBUGGER DBG 24 6 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 361: ...for CR oscillation Recommended value 32 768 kHz 0 25 pF 0 2 8 MHz 0 2 8 MHz 1 MΩ 15 pF crystal 30 pF ceramic 15 pF crystal 30 pF ceramic 30 kΩ Symbol C1 C2 C3 C4 C5 C6 C7 C9 C10 C11 CP Cres Name Capacitor between VSS and VD1 Capacitor between VSS and VC1 Capacitor between VSS and VC2 Capacitor between VSS and VC3 Capacitor between VSS and VC4 Capacitor between VSS and VC5 Booster capacitors Capaci...

Page 362: ...25 BASIC EXTERNAL WIRING DIAGRAM 25 2 EPSON S1C17704 TECHNICAL MANUAL THIS PAGE IS BLANK ...

Page 363: ...nditions Ta 20 to 70 C Item Symbol Condition Min Typ Max Unit Operating power voltage VDD Normal operation mode 1 8 3 6 V Flash programming mode 2 7 3 6 V Operating frequency fOSC3 Crystal ceramic oscillation 0 2 8 2 MHz CR oscillation 0 2 2 2 MHz fOSC1 Crystal oscillation 32 768 100 kHz Capacitor between VSS and VD1 1 C1 0 1 µF Capacitor between VSS and VC1 1 C2 0 1 µF Capacitor between VSS and V...

Page 364: ... 0 1VDD 0 5VDD V High level schmitt input voltage 2 1 VT2 Pxx 0 5VDD 0 9VDD V Low level schmitt input voltage 2 1 VT2 Pxx 0 1VDD 0 5VDD V High level output current IOH Pxx VOH 0 9VDD 0 5 mA Low level output current IOL Pxx VOL 0 1VDD 0 5 mA Input leak current ILI Pxx RESET 1 1 µA Output leak current ILO Pxx 1 1 µA Input pull up resistance RIN Pxx RESET 100 500 kΩ Input pin capacitance CIN Pxx VIN ...

Page 365: ... resistor between VSS and VC3 0 59VC5 0 63VC5 V VC4 Connect 1MΩ load resistor between VSS and VC4 0 79VC5 0 83VC5 V VC5 Connect 1MΩ load resistor be tween VSS and VC5 LC 3 0 0x0 Typ 0 94 4 20 Typ 1 06 V LC 3 0 0x1 4 30 V LC 3 0 0x2 4 40 V LC 3 0 0x3 4 50 V LC 3 0 0x4 4 60 V LC 3 0 0x5 4 70 V LC 3 0 0x6 4 80 V LC 3 0 0x7 4 90 V LC 3 0 0x8 5 00 V LC 3 0 0x9 5 10 V LC 3 0 0xa 5 20 V LC 3 0 0xb 5 30 V...

Page 366: ...t Erase time 1 tSE Erase 4K bytes 25 ms Programming time 1 tBP Program 16 bits 20 µs Erase program count 2 CFEP 1000 times 1 Data transfer and data verification are included and erase program start control time is not included 2 The erase program count assumes that erasing programming or programming only is one count and the programmed data is guaranteed to be retained for 10 years ...

Page 367: ...5V LHVLD 1 35 60 µA SVD circuit current 5 ISVD VDD 3 6V 5 10 µA Flash memory erasing current 6 IFERS When the CPU runs with 8MHz clock VD1MD 1 7 14 mA Flash memory pro gramming current 7 IFPRG When the CPU runs with 8MHz clock VD1MD 1 7 14 mA 1 This value is added to the current consumption in HALT mode or current consumption during execution when the LCD circuit is active Current consumption incr...

Page 368: ... delay time tSDO 20 ns Slave mode Unless otherwise specified VDD 1 8 to 3 6V VSS 0V Ta 20 to 70 C Item Symbol Min Typ Max Unit SPICLK cycle time tSPCK 500 ns SDI setup time tSDS 10 ns SDI hold time tSDH 10 ns SDO output delay time tSDO 80 ns 26 6 2 I2C AC Characteristics SCL SDA tSCL tSTH tSDD tSPH Unless otherwise specified VDD 1 8 to 3 6V VSS 0V Ta 20 to 70 C Item Symbol Min Typ Max Unit SCL cyc...

Page 369: ...0 to 70 C Item Symbol Min Typ Max Unit EXCLx input High pulse width tECH 2 fSYS s EXCLx input Low pulse width tECL 2 fSYS s UART transfer rate RU 115200 bps Input rise time tCR 80 ns Input fall time tCF 80 ns fSYS System operating clock frequency 26 6 4 System AC Characteristics RESET tSR VIH VIL Unless otherwise specified VDD 1 8 to 3 6V VSS 0V VIH 0 8VDD VIL 0 2VDD Ta 20 to 70 C Item Symbol Min ...

Page 370: ...10 pF Frequency IC deviation f IC VDD constant 10 10 ppm Frequency power voltage deviation f V 1 ppm V Frequency adjustment range f CG VDD constant CG 0 to 25pF 25 ppm 1 C 002RX manufactured by Seiko Epson OSC3 Crystal Unless otherwise specified VDD 1 8 to 3 6V VSS 0V Ta 25 C crystal resonator CA 301 1 Rf 1MΩ CG3 CD3 15pF Item Symbol Condition Min Typ Max Unit Oscillation start time 2 tsta 10 ms 1...

Page 371: ...ues High level output current voltage characteristic Ta 70 C Max value 0 0 0 3 6 9 12 15 0 2 0 4 0 6 0 8 1 0 VDD VOH V VDD 1 8 V VDD 2 4 V VDD 3 6 V I OH mA Low level output current voltage characteristic Ta 70 C Min value 0 0 15 12 9 6 3 0 0 1 0 2 0 3 0 4 0 5 0 6 VOL V VDD 1 8 V I OL mA VDD 2 4 V VDD 3 6 V ...

Page 372: ...nnected between VSS and VC5 no panel load Ta 25 C Typ value 1 5 2 0 2 5 3 0 3 5 4 0 7 0 6 0 5 0 4 0 3 0 2 0 VDD V LCx 0xf LCx 0x0 V C5 V LCD drive voltage supply voltage characteristic with the power voltage booster used When a 1 MΩ load resistor is connected between VSS and VC5 no panel load Ta 25 C Typ value 1 5 1 8 2 1 2 4 2 7 3 0 7 0 6 0 5 0 4 0 3 0 2 0 VDD V LCx 0xf LCx 0x0 V C5 V ...

Page 373: ...teristic Typ value 50 1 05VC5 1 04VC5 1 03VC5 1 02VC5 1 01VC5 1 00VC5 0 99VC5 0 98VC5 0 97VC5 0 96VC5 0 95VC5 25 0 25 50 75 100 Ta C V C5 V LCD drive voltage load characteristic When a load is connected to the VC5 pin only LCx 0xf Ta 25 C Typ value 0 5 80 5 75 5 70 5 65 5 60 5 55 5 50 4 8 12 16 20 IVC5 μA V C5 V ...

Page 374: ... 75 100 Ta C V SVD V HALT state current consumption temperature characteristic during operation with OSC1 Crystal oscillation fOSC1 32 768 kHz OSC3 OFF VD1MD 0 PCKEN 0 Typ value 50 10 8 6 4 2 0 25 0 25 50 75 100 Ta C I HALT1 μA Run state current consumption temperature characteristic during operation with OSC1 Crystal oscillation fOSC1 32 768 kHz Typ value 50 50 45 40 35 30 25 20 15 10 5 0 25 0 25...

Page 375: ...0 0 2 0 4 0 6 0 8 0 10 0 I EXE2 μA 1 0 3 0 5 0 7 0 9 0 FLCYC 4 1 cycle FLCYC 0 2 cycles OSC3 clock frequency MHz Run status current consumption resistor characteristic during operation with OSC3 CR oscillation Ta 25 C Typ value 10 4000 3500 3000 2500 2000 1500 1000 500 0 100 1000 RCR3 kΩ I EXE3 I EXE31 μA VD1MD 0 VD1MD 1 OSC3 oscillation frequency resistor characteristic CR oscillation Ta 25 C Typ...

Page 376: ... 50 10000 1000 100 25 25 50 0 75 100 Ta C f OSC3 kHz Processing power frequency characteristic VDD 3 6V VD1MD 0 Typ value 0 0 1600 1400 1200 1000 800 600 400 200 0 2 0 4 0 6 0 8 0 10 0 1 0 3 0 5 0 7 0 9 0 FLCYC 4 1 cycle FLCYC 0 2 cycles OSC3 clock frequency MHz Executable instructions per unit of time for 1 μ A of current consumption normalized to 1 second ...

Page 377: ...E S1C17704 TECHNICAL MANUAL EPSON 27 1 27 Package TQFP24 144 pin package Unit mm 16 0 1 18 0 4 16 0 1 18 0 4 37 72 1 36 108 73 144 109 INDEX 1 0 0 1 0 1 1 2 max 0 16 0 4 0 10 0 05 1 0 5 0 2 0 8 0 125 0 05 0 025 ...

Page 378: ...GA6U96 Package Top View Bottom View A1 Corner A1 Corner Index D S S e y E A A 1 ZD Z E φ φ b M e L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 Symbol D E A A1 e b X y ZD ZE Min 0 26 Dimension in Millimeters Nom 6 6 0 23 0 5 0 5 0 5 Max 1 2 0 36 0 08 0 1 ...

Page 379: ...61 Package Top View Bottom View A1 Corner A1 Corner Index D S S e y E A A 1 ZD Z E φ φ b M e N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol D E A A1 e b X y ZD ZE Min 0 26 Dimension in Millimeters Nom 7 7 0 23 0 5 0 5 0 5 Max 1 0 0 36 0 08 0 1 ...

Page 380: ... 144 Package Top View Bottom View A1 Corner A1 Corner Index D S S e y E A A 1 SD S E φ φ b M e M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 Symbol D E A A1 e b X y SD SE Min 0 38 Dimension in Millimeters Nom 10 10 0 3 0 8 0 4 0 4 Max 1 0 0 48 0 08 0 1 ...

Page 381: ...yout 28 1 Diagram of Pad Layout 3 99 mm Y X 0 0 3 97 mm 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 5 1 10 15 20 25 30 35 40 45 50 55 60 65 70 Die No CJ701D Pad opening Pad No 1 36 73 109 70 104 µm Pad No 37 72 110 145 104 70 µm Chip thickness 400 µm ...

Page 382: ... 870 0 175 17 SEG33 0 120 1 880 53 COM18 SEG69 1 870 0 145 89 P24 SOUT 0 045 1 880 126 COM13 1 870 0 095 18 SEG34 0 040 1 880 54 COM17 SEG70 1 870 0 065 90 P23 SIN 0 035 1 880 127 COM14 1 870 0 015 19 SEG35 0 040 1 880 55 COM16 SEG71 1 870 0 015 91 P22 SPICLK 0 115 1 880 128 COM15 1 870 0 065 20 SEG36 0 120 1 880 56 VSS 1 870 0 175 92 P21 SDO 0 195 1 880 129 SEG0 1 870 0 225 21 SEG37 0 200 1 880 5...

Page 383: ...ler output clock 0x4262 T16_TR2 16 bit Timer Ch 2 Reload Data Register Sets reload data 0x4264 T16_TC2 16 bit Timer Ch 2 Counter Data Register Counter data 0x4266 T16_CTL2 16 bit Timer Ch 2 Control Register Sets the timer mode and starts stops the timer 0x4268 0x427f Reserved Interrupt controller 16 bit device 0x4300 ITC_IFLG Interrupt Flag Register Indicates resets interrupt occurrence status 0x4...

Page 384: ...x50c0 T8OSC1_CTL 8 bit OSC1 Timer Control Register Sets the timer mode and starts stops the timer 0x50c1 T8OSC1_CNT 8 bit OSC1 Timer Counter Data Register Counter data 0x50c2 T8OSC1_CMP 8 bit OSC1 Timer Compare Data Register Sets compare data 0x50c3 T8OSC1_IMSK 8 bit OSC1 Timer Interrupt Mask Register Enables disables interrupt 0x50c4 T8OSC1_IFLG 8 bit OSC1 Timer Interrupt Flag Register Indicates ...

Page 385: ...M Timer Counter Data Register Counter data 0x5306 T16E_CTL PWM Timer Control Register Sets the timer mode and starts stops the timer 0x5308 T16E_CLK PWM Timer Input Clock Select Register Selects a prescaler output clock 0x530a T16E_IMSK PWM Timer Interrupt Mask Register Enables disables interrupt 0x530c T16E_IFLG PWM Timer Interrupt Flag Register Indicates resets interrupt occurrence status 0x530e...

Page 386: ...020 Prescaler Register name Address Bit Name Function Setting Init R W Remarks Prescaler Con trol Register PSC_CTL 0x4020 8 bits D7 2 reserved 0 when being read D1 PRUND Prescaler run stop in debug mode 1 Run 0 Stop 0 R W D0 PRUN Prescaler run stop control 1 Run 0 Stop 0 R W ...

Page 387: ...lder data in the buf fer is read out first UART Mode Register UART_MOD 0x4103 8 bits D7 5 reserved 0 when being read D4 CHLN Character length 1 8 bits 0 7 bits 0 R W D3 PREN Parity enable 1 With parity 0 No parity 0 R W D2 PMD Parity mode select 1 Odd 0 Even 0 R W D1 STPB Stop bit select 1 2 bits 0 1 bit 0 R W D0 SSCK Input clock select 1 External 0 Internal 0 R W UART Control Register UART_CTL 0x...

Page 388: ... PCLK 1 4 PCLK 1 2 PCLK 1 1 8 bit Timer Reload Data Register T8F_TR 0x4202 16 bits D15 8 reserved 0 when being read D7 0 TR 7 0 8 bit timer reload data TR7 MSB TR0 LSB 0x0 to 0xff 0x0 R W 8 bit Timer Counter Data Register T8F_TC 0x4204 16 bits D15 8 reserved 0 when being read D7 0 TC 7 0 8 bit timer counter data TC7 MSB TC0 LSB 0x0 to 0xff 0xff R 8 bit Timer Control Register T8F_CTL 0x4206 16 bits...

Page 389: ...ead D4 TRMD Count mode select 1 One shot 0 Repeat 0 R W D3 2 reserved 0 when being read D1 PRESER Timer reset 1 Reset 0 Ignored 0 W D0 PRUN Timer run stop control 1 Run 0 Stop 0 R W 16 bit Timer Ch 1 Input Clock Select Register T16_CLK1 0x4240 16 bits D15 4 reserved 0 when being read D3 0 DF 3 0 Timer input clock select Prescaler output clock DF 3 0 Clock 0x0 R W 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x...

Page 390: ... Ch 2 Reload Data Register T16_TR2 0x4262 16 bits D15 0 TR 15 0 16 bit timer reload data TR15 MSB TR0 LSB 0x0 to 0xffff 0x0 R W 16 bit Timer Ch 2 Counter Data Register T16_TC2 0x4264 16 bits D15 0 TC 15 0 16 bit timer counter data TC15 MSB TC0 LSB 0x0 to 0xffff 0xffff R 16 bit Timer Ch 2 Control Register T16_CTL2 0x4266 16 bits D15 11 reserved 0 when being read D10 CKACTV External clock active lev...

Page 391: ...0 R W D1 EIEN1 P1 port interrupt enable 0 R W D0 EIEN0 P0 port interrupt enable 0 R W ITC Control Register ITC_CTL 0x4304 16 bits D15 1 reserved 0 when being read D0 ITEN ITC enable 1 Enable 0 Disable 0 R W External Interrupt Level Setup Register 0 ITC_ELV0 0x4306 16 bits D15 13 reserved 0 when being read D12 EITG1 P1 interrupt trigger mode 1 Level 0 Pulse 0 R W Be sure to set to 1 D11 reserved 0 ...

Page 392: ... 0x4310 16 bits D15 11 reserved 0 when being read D10 8 IILV3 2 0 T16 Ch 2 interrupt level 0 to 7 0x0 R W D7 3 reserved 0 when being read D2 0 IILV2 2 0 T16 Ch 1 interrupt level 0 to 7 0x0 R W Internal Interrupt Level Setup Register 2 ITC_ILV2 0x4312 16 bits D15 11 reserved 0 when being read D10 8 IILV5 2 0 REMC interrupt level 0 to 7 0x0 R W D7 3 reserved 0 when being read D2 0 IILV4 2 0 UART int...

Page 393: ...read D7 0 SPTDB 7 0 SPI transmit data buffer SPTDB7 MSB SPTDB0 LSB 0x0 to 0xff 0x0 R W SPI Receive Data Register SPI_RXD 0x4324 16 bits D15 8 reserved 0 when being read D7 0 SPRDB 7 0 SPI receive data buffer SPRDB7 MSB SPRDB0 LSB 0x0 to 0xff 0x0 R SPI Control Register SPI_CTL 0x4326 16 bits D15 6 reserved 0 when being read D5 SPRIE Receive data buffer full int enable 1 Enable 0 Disable 0 R W D4 SP...

Page 394: ...f 1 On 0 Off 0 R W D3 2 reserved 0 when being read D1 STP Stop control 1 Stop 0 Ignored 0 R W D0 STRT Start control 1 Start 0 Ignored 0 R W I2C Data Register I2C_DAT 0x4344 16 bits D15 12 reserved 0 when being read D11 RBRDY Receive buffer ready 1 Ready 0 Empty 0 R D10 RXE Receive execution 1 Receive 0 Ignored 0 R W D9 TXE Transmit execution 1 Transmit 0 Ignored 0 R W D8 RTACK Receive transmit ACK...

Page 395: ...alue 0x0 to 0xff 0 R Clock Timer Interrupt Mask Register CT_IMSK 0x5002 8 bits D7 4 reserved 0 when being read D3 CTIE32 32 Hz interrupt enable 1 Enable 0 Disable 0 R W D2 CTIE8 8 Hz interrupt enable 1 Enable 0 Disable 0 R W D1 CTIE2 2 Hz interrupt enable 1 Enable 0 Disable 0 R W D0 CTIE1 1 Hz interrupt enable 1 Enable 0 Disable 0 R W Clock Timer Interrupt Flag Register CT_IFLG 0x5003 8 bits D7 4 ...

Page 396: ...D10 3 0 1 10 sec BCD counter value 0 to 9 0 R D3 0 BCD100 3 0 1 100 sec BCD counter value 0 to 9 0 R Stopwatch Timer Interrupt Mask Register SWT_IMSK 0x5022 8 bits D7 3 reserved 0 when being read D2 SIE1 1 Hz interrupt enable 1 Enable 0 Disable 0 R W D1 SIE10 10 Hz interrupt enable 1 Enable 0 Disable 0 R W D0 SIE100 100 Hz interrupt enable 1 Enable 0 Disable 0 R W Stopwatch Timer Interrupt Flag Re...

Page 397: ...egister WDT_CTL 0x5040 8 bits D7 5 reserved 0 when being read D4 WDTRST Watchdog timer reset 1 Reset 0 Ignored 0 W D3 0 WDTRUN 3 0 Watchdog timer run stop control Other than 1010 Run 1010 Stop 1010 R W Watchdog Timer Status Register WDT_ST 0x5041 8 bits D7 2 reserved 0 when being read D1 WDTMD NMI Reset mode select 1 Reset 0 NMI 0 R W D0 WDTST NMI status 1 NMI occurred 0 Not occurred 0 R ...

Page 398: ...e 0 Disable 0 R W LCD Clock Setup Register OSC_LCLK 0x5063 8 bits D7 5 reserved 0 when being read D4 2 LCKDV 2 0 LCD clock division ratio select LCKDV 2 0 Division ratio 0x0 R W 0x7 0x5 0x4 0x3 0x2 0x1 0x0 reserved OSC3 1 512 OSC3 1 256 OSC3 1 128 OSC3 1 64 OSC3 1 32 D1 LCKSRC LCD clock source select 1 OSC1 0 OSC3 1 R W D0 LCKEN LCD clock enable 1 Enable 0 Disable 0 R W FOUT Control Register OSC_F...

Page 399: ...LK Control Register CLG_PCLK 0x5080 8 bits D7 2 reserved 0 when being read D1 0 PCKEN 1 0 PCLK enable PCKEN 1 0 PCLK supply 0x3 R W 0x3 0x2 0x1 0x0 Enable Not allowed Not allowed Disable CCLK Control Register CLG_CCLK 0x5081 8 bits D7 2 reserved 0 when being read D1 0 CCLKGR 1 0 CCLK clock gear ratio select CCLKGR 1 0 Gear ratio 0x0 R W 0x3 0x2 0x1 0x0 1 8 1 4 1 2 1 1 ...

Page 400: ...ment LC 3 0 Display 0x0 R W 0xf 0x0 Dark Light LCD Clock Control Register LCD_CCTL 0x50a2 8 bits D7 2 reserved 0 when being read D1 0 LDUTY 1 0 LCD duty select LDUTY 1 0 Duty 0x2 R W 0x3 0x2 0x1 0x0 reserved 1 32 1 16 reserved LCD Voltage Regulator Control Register LCD_VREG 0x50a3 8 bits D7 5 reserved 0 when being read D4 LHVLD LCD heavy load protection mode 1 On 0 Off 0 R W D3 0 reserved 0 when b...

Page 401: ...Data Register T8OSC1_CNT 0x50c1 8 bits D7 0 T8OCNT 7 0 Timer counter data T8OCNT7 MSB T8OCNT0 LSB 0x0 to 0xff 0x0 R 8 bit OSC1 Timer Compare Data Register T8OSC1_CMP 0x50c2 8 bits D7 0 T8OCMP 7 0 Compare data T8OCMP7 MSB T8OCMP0 LSB 0x0 to 0xff 0x0 R W 8 bit OSC1 Timer Interrupt Mask Register T8OSC1_IMSK 0x50c3 8 bits D7 1 reserved 0 when being read D0 T8OIE 8 bit OSC1 timer interrupt enable 1 Ena...

Page 402: ... R W 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 2 7 V 2 6 V 2 5 V 2 4 V 2 3 V 2 2 V 2 1 V 2 05 V 2 0 V 1 95 V 1 9 V 1 85 V 1 8 V SVD Detection Result Register SVD_RSLT 0x5102 8 bits D7 1 reserved 0 when being read D0 SVDDT SVD detection result 1 Low 0 Normal R SVD Interrupt Mask Register SVD_IMSK 0x5103 8 bits D7 1 reserved 0 when being read D0 SVDIE SVD interrupt enable 1 Ena...

Page 403: ... Register name Address Bit Name Function Setting Init R W Remarks VD1 Control Register VD1_CTL 0x5120 8 bits D7 5 reserved 0 when being read D4 HVLD VD1 heavy load protection mode 1 On 0 Off 0 R W D3 1 reserved 0 when being read D0 VD1MD Flash erase program mode 1 Flash 2 5 V 0 Norm 1 8 V 0 R W ...

Page 404: ...ot occurred 0 R W Reset by writing 1 P0 Port Chattering Filter Control Register P0_CHAT 0x5208 8 bits D7 reserved 0 when being read D6 4 P0CF2 2 0 P0 7 4 chattering filter time P0CF2 2 0 Filter time 0 R W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384 fPCLK 8192 fPCLK 4096 fPCLK 2048 fPCLK 1024 fPCLK 512 fPCLK 256 fPCLK None 0x0 R W D3 reserved 0 when being read D2 0 P0CF1 2 0 P0 3 0 chattering filter time...

Page 405: ...when being read D3 0 P3IO 3 0 P3 3 0 port I O direction select 1 Output 0 Input 0 R W P3 Port Pull up Control Register P3_PU 0x5233 8 bits D7 4 reserved 0 when being read D3 0 P3PU 3 0 P3 3 0 port pull up enable 1 Enable 0 Disable 1 0xff R W P3 Port Schmitt Trigger Control Register P3_SM 0x5234 8 bits D7 4 reserved 0 when being read D3 0 P3SM 3 0 P3 3 0 port Schmitt trigger input enable 1 Enable S...

Page 406: ...D3 CLKSEL Input clock select 1 External 0 Internal 0 R W D2 OUTEN Clock output enable 1 Enable 0 Disable 0 R W D1 T16ERST Timer reset 1 Reset 0 Ignored 0 W 0 when being read D0 T16ERUN Timer run stop control 1 Run 0 Stop 0 R W PWM Timer Input Clock Select Register T16E_CLK 0x5308 16 bits D15 4 reserved 0 when being read D3 0 T16EDF 3 0 Timer input clock select Prescaler output clock T16EDF 3 0 Clo...

Page 407: ...ccess cycle FLCYC 2 0 Read cycle 0x3 R W 0x7 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 cycles 5 cycles 4 cycles 3 cycles 2 cycles SRAMC Control Register MISC_SR 0x5321 8 bits D7 2 reserved 0 when being read D1 0 SRCYC 1 0 SRAMC access cycle SRWAIT 1 0 Access cycle 0x3 R W 0x3 0x2 0x1 0x0 5 cycles 4 cycles 3 cycles 2 cycles OSC1 Peripheral Control Register MISC_OSC1 0x5322 8 bits D7 1 reserved 0 when bein...

Page 408: ...bits D7 6 reserved 0 when being read D5 0 REMCH 5 0 H carrier length setup 0x0 to 0x3f 0x0 R W REMC L Carrier Length Setup Register REMC_CARL 0x5343 8 bits D7 6 reserved 0 when being read D5 0 REMCL 5 0 L carrier length setup 0x0 to 0x3f 0x0 R W REMC Status Register REMC_ST 0x5344 8 bits D7 1 reserved 0 when being read D0 REMDT Transmit receive data 1 1 H 0 0 L 0 R W REMC Length Counter Register R...

Page 409: ...tor Table Base Register TTBR 0xffff80 32 bits D31 24 Unused fixed at 0 0x0 0x0 R D23 0 TTBR 23 0 Vector table base address 0x8000 0x80 00 R Processor ID Register IDIR 0xffff84 8 bits D7 0 IDIR 7 0 Processor ID 0x10 S1C17 Core 0x10 0x10 R Debug RAM Base Register DBRAM 0xffff90 32 bits D31 24 Unused fixed at 0 0x0 0x0 R D23 0 DBRAM 23 0 Debug RAM base address 0xfc0 0xfc0 R ...

Page 410: ...ackage ICD e g S5U1C17001H 4 pin to 4 pin target system connecting cable included with the ICD package USB Target board Figure B 1 1 Flash Programming System using Debugger To program the S1C17704 Flash memory using this function a four pin connector is required on the target board for connecting the ICD e g S5U1C17001H Use the S1C17704 DCLK P31 DST2 P32 and DSIO P33 pins as the debug pins and con...

Page 411: ...ed to erase and program the Flash memory while the S1C17704 is running on the target board For the S1C17704 an object file that includes the functional routines for self programming is provided as the self programming package By linking this object with the application program a self programming function can be implemented easily For details refer to the manual supplied with the self programming p...

Page 412: ...l bus RAM Flash ITC T16 T8F UART SPI I2C T16E P MISC VD1 SVD REMC Control registers CT SWT WDT T8OSC1 LCD PCLK CLK_256Hz LCLK Gate OSC3 OSC4 Clock source select System clock FOUT3 FOUT1 output circuit FOUT1 Noise filter RESET OSC1 OSC2 SLEEP On Off control Gear select OSC3 OSC1 Clock source select wakeup HALT On Off control S1C17 Core S1C17 Core Division ratio select Divider 1 1 1 16K Division rat...

Page 413: ...struction Execute the halt instruction if there is no task to be processed by the CPU such as when the display on the LCD is only required or when the CPU is waiting an interrupt Although the CPU enters HALT mode and stops operating the peripheral modules keep the status when the halt instruction is executed So the LCD driver and the peripheral modules used to generate an interrupt can be made to ...

Page 414: ... IE flag in the CPU has been set to disable the I O port interrupt the CPU does not accept the interrupt request and starts executing the instructions that follow the halt or slp instruction When the interrupt has been enabled and PCLK was activated before the halt or slp instruction is executed the CPU executes the interrupt handler When PCLK was stopped before the halt or slp instruction is exec...

Page 415: ...a heavy load LCD system voltage regulator Turning the power voltage booster on increases current consumption If the supply voltage VDD is 2 5 V or more turn the power voltage booster off and drive the LCD system voltage regulator with VDD The power voltage booster should be used when the supply voltage VDD is less than 2 5 V Enabling the heavy load protection function for the LCD system voltage re...

Page 416: ...round 0 1 to 0 2 mm Furthermore do not configure digital signal lines in parallel with these components and lines when arranging them on the same or another layer of the board Such an arrangement is strictly prohibited even with clearance of three millimeters or more Also avoid arranging digital signal lines across these components and signal lines 3 Shield the OSC1 OSC3 and OSC2 OSC4 pins and lin...

Page 417: ...wing points to prevent this 1 The power supply should be connected to the VDD and VSS pins with patterns as short and large as possible 2 When connecting between the VDD and VSS pins with a bypass capacitor the pins should be connected as short as possible VDD VSS Bypass capacitor connection example VDD VSS Arrangement of Signal Lines In order to prevent generation of electromagnetic induction noi...

Page 418: ...z The generation of fast noise may not be observed with a low frequency oscilloscope If potential noise induced erratic operations are detected through waveform observations using an oscilloscope connect the suspected pin to the GND or power supply with low impedance 1 kΩ or less and check once again If erratic operations are no longer detected or occur at reduced frequency or if different symptom...

Page 419: ...e bonding process perform enough evaluation of data stored in the nonvolatile memory before the product is shipped Other The 0 25 µm fine pattern process is employed to manufacture this series of products Although the product is designed to meet EIAJ and MIL standards regarding basic IC reliability please pay careful attention to the following points when actually mounting the chip on a board Sinc...

Page 420: ...F long t16_0_handler 0x0d 0x34 T16 ch0 long t16_1_handler 0x0e 0x38 T16 ch1 long t16_2_handler 0x0f 0x3c T16 ch2 long uart_handler 0x10 0x40 UART long remc_handler 0x11 0x44 REMC long spi_handler 0x12 0x48 SPI long i2c_handler 0x13 0x4c I2C long int14_handler 0x14 0x50 long int15_handler 0x15 0x54 long int16_handler 0x16 0x58 long int17_handler 0x17 0x5c long int18_handler 0x18 0x60 long int19_han...

Page 421: ...lare a rodata section to locate the vector table in the vector section 2 Define addresses of the interrupt handler routines as vectors The intXX_handler symbols can be used for software interrupts 3 Describe the program code in a text section 4 Set the stack pointer 5 Set the number of access cycles for the Flash controller One cycle access can be specified only when the system clock frequency is ...

Page 422: ...r Centre 25 Harbour Road Wanchai Hong Kong Phone 852 2585 4600 FAX 852 2827 4346 Telex 65542 EPSCO HX EPSON CHINA CO LTD SHENZHEN BRANCH 12 F Dawning Mansion Keji South 12th Road Hi Tech Park Shenzhen Phone 86 755 2699 3828 FAX 86 755 2699 3838 EPSON TAIWAN TECHNOLOGY TRADING LTD 14F No 7 Song Ren Road Taipei 110 Phone 886 2 8786 6688 FAX 886 2 8786 6660 EPSON SINGAPORE PTE LTD 1 HarbourFront Plac...

Page 423: ...ECHNICAL MANUAL S1C17704 http www epson jp device semicon_e EPSON Electronic Devices Website SEMICONDUCTOR OPERATIONS DIVISION First Issue June 2008 Revised August 2008 in JAPAN D Document code 411511901 ...

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