Epson S1C17704, Technical Manual

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8 CLOCK GENERATOR (CLG)
8-2
EPSON
S1C17704 TECHNICAL MANUAL
8.2 Controlling the CPU Core Clock (CCLK)
The CLG module incorporates clock gears to decelerate the system clock before supplying the clock to the S1C17
Core. Using a clock at as low a speed as possible to run the S1C17 Core reduces current consumption. Furthermore,
the CLG stops clock supply to the S1C17 Core for power saving when the
halt
instruction is executed.
OSC3
CCLK
OSC1
Clock gear
(1/1–1/8) Gate S1C17 Core
Gear select
System clock
HALT
Figure 8.2.1 CCLK Supply System
Selecting a clock gear
Use CCLKGR[1:0] (D[1:0]/CLG_CCLK register) to select a gear for reducing the system clock speed.
∗
CCLKGR[1:0] : CCLK Clock Gear Ratio Select Bits in the CCLK Control (CLG_CCLK) Register (D[1:0]/0x5081)
Table 8.2.1 Selecting a CCLK Gear
CCLKGR[1:0] Gear ratio
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
(Default: 0x0)
Controlling the clock supply
To stop the CCLK clock to be supplied to the S1C17 Core, execute the
halt
instruction. This does not stop the
system clock, so the peripheral modules remain active.
HALT mode is canceled by occurrence of a reset, NMI, or other interrupt, and it resumes supplying CCLK.
Executing the
slp
instruction disables system clock supply to the CLG, therefore it also stops CCLK. When
SLEEP mode is canceled by an external interrupt, supplying CCLK is resumed as well as the system clock
supply to the CLG.
For control of the system clock, see Chapter 7, “Oscillator (OSC).”