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15 Quad Synchronous Serial Interface (QSPI)

S1C31D50/D51 TECHNICAL MANUAL

Seiko Epson Corporation

15-13

(Rev. 2.00)

QSPICLKn

QSDIOn[3:0]

QSPI_nINTF.TBEIF

QSPI_nINTF.TENDIF

Software operations

Data (W)

→

QSPI_nTXD

Data (W)

→

QSPI_nTXD

1 (W)

→

QSPI_nINTF.TENDIF

Data (W)

→

QSPI_nTXD

Figure 15.5.4.1 Example of Data Sending Operations in Master Mode

(QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3)

Data transmission

End

Negate the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO

= 1) or a general-purpose port

Assert the slave select signal output from

the #QSPISSn pin (QSPI_nCTL.MSTSSO

= 0) or a general-purpose port

(

)

(

)

Read the QSPI_nINTF.TBEIF bit

Set the transfer direction to output

(QSPI_nCTL.DIR = 0)

Write transmit data to

the QSPI_nTXD register

YES

Not necessary
in single transfer mode

YES

Transmit data remained?

QSPI_nINTF.TBEIF = 1 ?

Wait for an interrupt request

(QSPI_nINTF.TBEIF = 1)

Figure 15.5.4.2 Data Transmission Flowchart in Master Mode

Data transmission using DMA

By setting the QSPI_

TBEDMAEN.TBEDMAEN

bit to 1 (DMA transfer request enabled), a DMA transfer

request is sent to the DMA controller and transmit data is transferred from the specified memory to the QSPI_

TXD register via DMA Ch.

when the QSPI_

INTF.TBEIF bit is set to 1 (transmit buffer empty).

This automates the procedure from Step 3 to Step 6 described above.

The transfer source/destination and control data must be set for the DMA controller and the relevant DMA
channel must be enabled to start a DMA transfer in advance so that transmit data will be transferred to the
QSPI_

TXD register. For more information on DMA, refer to the “DMA Controller” chapter.

Summary of Contents for Buzzer S1C31D51

Page 1: ...Rev 2 00 CMOS 32 BIT SINGLE CHIP MICROCONTROLLER S1C31D50 D51 Technical Manual ...

Page 2: ... Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and further there is no representation that this material is applicable to products requiring high level reliability such as medical prod ucts Moreover no license to any intellectual property rights is granted by implication or...

Page 3: ... PROT 15 0 bits R W Read write bit R WP Read write bit with a write protection using the SYSPROT PROT 15 0 bits reserved Reserved bit Do not alter from the initial value Control bit read write values This manual describes control bit values in a hexadecimal notation except for one bit values and except when decimal or binary notation is required in terms of explanation The values are described as ...

Page 4: ... 2 3 Clock Generator CLG 2 5 2 3 1 Overview 2 5 2 3 2 Input Output Pins 2 6 2 3 3 Clock Sources 2 6 2 3 4 Operations 2 9 2 4 Operating Mode 2 13 2 4 1 Initial Boot Sequence 2 13 2 4 2 Transition between Operating Modes 2 13 2 5 Interrupts 2 15 2 6 Control Registers 2 15 PWGA Control Register 2 15 CLG System Clock Control Register 2 16 CLG Oscillation Control Register 2 17 CLG IOSC Control Register...

Page 5: ...Data Structure 6 2 6 4 1 Transfer Source End Pointer 6 3 6 4 2 Transfer Destination End Pointer 6 3 6 4 3 Control Data 6 4 6 5 DMA Transfer Mode 6 5 6 5 1 Basic Transfer 6 5 6 5 2 Auto Request Transfer 6 5 6 5 3 Ping Pong Transfer 6 6 6 5 4 Memory Scatter Gather Transfer 6 7 6 5 5 Peripheral Scatter Gather Transfer 6 8 6 6 DMA Transfer Cycle 6 9 6 7 Interrupts 6 9 6 8 Control Registers 6 10 DMAC S...

Page 6: ...x Port Enable Register 7 7 Px Port Pull up down Control Register 7 8 Px Port Interrupt Flag Register 7 8 Px Port Interrupt Control Register 7 8 Px Port Chattering Filter Enable Register 7 9 Px Port Mode Select Register 7 9 Px Port Function Select Register 7 9 P Port Clock Control Register 7 10 P Port Interrupt Flag Group Register 7 11 7 7 Control Register and Port Function Configuration of this IC...

Page 7: ...egisters 10 6 RTCA Control Register Low Byte 10 6 RTCA Control Register High Byte 10 7 RTCA Second Alarm Register 10 7 RTCA Hour Minute Alarm Register 10 8 RTCA Stopwatch Control Register 10 8 RTCA Second 1Hz Register 10 9 RTCA Hour Minute Register 10 10 RTCA Month Day Register 10 11 RTCA Year Week Register 10 11 RTCA Interrupt Flag Register 10 12 RTCA Interrupt Enable Register 10 13 11 Supply Vol...

Page 8: ... n Interrupt Flag Register 12 6 T16 Ch n Interrupt Enable Register 12 7 13 UART UART3 13 1 13 1 Overview 13 1 13 2 Input Output Pins and External Connections 13 2 13 2 1 List of Input Output Pins 13 2 13 2 2 External Connections 13 2 13 2 3 Input Pin Pull Up Function 13 2 13 2 4 Output Pin Open Drain Output Function 13 2 13 2 5 Input Output Signal Inverting Function 13 2 13 3 Clock Settings 13 2 1...

Page 9: ...Operations 14 5 14 5 1 Initialization 14 5 14 5 2 Data Transmission in Master Mode 14 6 14 5 3 Data Reception in Master Mode 14 8 14 5 4 Terminating Data Transfer in Master Mode 14 10 14 5 5 Data Transfer in Slave Mode 14 10 14 5 6 Terminating Data Transfer in Slave Mode 14 11 14 6 Interrupts 14 12 14 7 DMA Transfer Requests 14 13 14 8 Control Registers 14 13 SPIA Ch n Mode Register 14 13 SPIA Ch ...

Page 10: ...uest Enable Register 15 34 QSPI Ch n Memory Mapped Access Configuration Register 1 15 34 QSPI Ch n Remapping Start Address High Register 15 35 QSPI Ch n Memory Mapped Access Configuration Register 2 15 35 QSPI Ch n Mode Byte Register 15 37 16 I2C I2C 16 1 16 1 Overview 16 1 16 2 Input Output Pins and External Connections 16 2 16 2 1 List of Input Output Pins 16 2 16 2 2 External Connections 16 2 1...

Page 11: ...17 25 T16B Ch n Timer Counter Data Register 17 25 T16B Ch n Counter Status Register 17 26 T16B Ch n Interrupt Flag Register 17 27 T16B Ch n Interrupt Enable Register 17 28 T16B Ch n Comparator Capture m Control Register 17 29 T16B Ch n Compare Capture m Data Register 17 31 T16B Ch n Counter Max Zero DMA Request Enable Register 17 32 T16B Ch n Compare Capture m DMA Request Enable Register 17 32 18 ...

Page 12: ...ect Register 19 8 ADC12A Ch n Configuration Register 19 9 ADC12A Ch n Interrupt Flag Register 19 10 ADC12A Ch n Interrupt Enable Register 19 10 ADC12A Ch n DMA Request Enable Register m 19 11 ADC12A Ch n Result Register 19 11 20 R F Converter RFC 20 1 20 1 Overview 20 1 20 2 Input Output Pins and External Connections 20 2 20 2 1 List of Input Output Pins 20 2 20 2 2 External Connections 20 2 20 3 ...

Page 13: ... Control Register 21 21 Ch 0 Playback Speed Conversion Register 21 21 Ch n State Monitor Register 21 22 Error Status Register 21 22 Operating Status Register 21 22 Version Number Register 21 22 21 6 2 Memory Check Function Register 21 23 Function ID Register 21 23 Interrupt Mask Register 21 23 Memory Address Register 21 23 Memory Size Register 21 24 Initial Value Setting Register 21 24 Command Reg...

Page 14: ...0x0020 0300 0x0020 031e Universal Port Multiplexer UPMUX AP A 28 0x0020 0380 0x0020 0394 UART UART3 Ch 0 AP A 30 0x0020 03a0 0x0020 03ac 16 bit Timer T16 Ch 1 AP A 31 0x0020 03b0 0x0020 03be Synchronous Serial Interface SPIA Ch 0 AP A 32 0x0020 03c0 0x0020 03d6 I2C I2C Ch 0 AP A 32 0x0020 0400 0x0020 042c 16 bit PWM Timer T16B Ch 0 AP A 34 0x0020 0440 0x0020 046c 16 bit PWM Timer T16B Ch 1 AP A 36...

Page 15: ...poration xiii Rev 2 00 Appendix B Power Saving AP B 1 B 1 Operating Status Configuration Examples for Power Saving AP B 1 B 2 Other Power Saving Methods AP B 2 Appendix C Mounting Precautions AP C 1 Appendix D Measures Against Noise AP D 1 Revision History ...

Page 16: ...pose RAM when the HW processor is inactive Instruction cache 512 bytes HW processor HWP Sound play function Sound algorithm EPSON high quality and high compression algorithm EOV EPSON Original Sound Format Playback channels 2 channels with mixing supported e g Ch 0 voice Ch 1 BGM Sampling frequency 15 625 kHz Bitrate 16 24 32 40 kbps Voice speed conversion 75 to 125 5 steps Sound output Speaker ou...

Page 17: ...ction Number of PWM output or capture input ports 4 ports channel Supply voltage detector SVD3 Number of channels 1 channel Detection voltage VDD or an external voltage 2 external detection ports are available Detection level VDD 28 levels 1 8 to 5 0 V external voltage 32 levels 1 2 to 5 0 V Other Intermittent operation mode Generates an interrupt or reset according to the detection level evaluati...

Page 18: ...ignal SWCLK SWD Cache controller Cache RAM 512 bytes RAM 8K bytes D50 10K bytes D51 RAM 14K bytes D50 12K bytes D51 MTB 16 bit peripheral bus 32 bit AHB bus IOSC oscillator EXOSC input circuit Clock generator CLG Power generator PWGA VDD VSS VD1 RTC1S SDA0 2 SCL0 2 EXSVD0 1 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PD FOUT OSC1 OSC2 OSC3 OSC4 EXOSC OSC3 oscillator OSC1 oscillator I O port 01 PPORT I O port...

Page 19: ...C4 PD2 OSC3 SDACOUT_N P51 SDACOUT_P P50 P23 RFIN0 UPMUX P22 REF0 UPMUX P21 SENA0 UPMUX P20 SENB0 UPMUX P62 EXSVD1 P61 EXSVD0 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 P46 P45 P40 P17 P16 P15 P14 P13 P06 P05 P04 P03 P46 RTC1S P45 ADTRG0 P40 VREFA0 P17 UPMUX ADIN00 P16 UPMUX ADIN01 P15 UPMUX ADIN02 P14 UPMUX ADIN03 P13 UPMUX ADIN04 P06 UPMUX P05 UPMUX P04 UPMUX P03 UPMU...

Page 20: ...MUX P25 UPMUX P24 UPMUX P23 RFIN0 UPMUX P22 REF0 UPMUX P21 SENA0 UPMUX P20 SENB0 UPMUX P62 EXSVD1 P61 EXSVD0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P46 P45 P44 P43 P40 P17 P16 P15 P14 P13 P12 P11 P06 P05 P04 P03 P46 RTC1S P45 ADTRG0 P44 P43 P40 VREFA0 P17 UPMUX ADIN00 P16 UPMUX ADIN01 P15 UPMUX ADIN02 P14 UPMUX ADIN03 P13 UPMUX ADIN04 P12 UP...

Page 21: ...2 P21 P20 P64 P63 P62 P61 P46 P45 P44 P43 P42 P41 P40 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 Pin name RESET VDD OSC1 OSC2 P80 P81 P82 P83 P84 P85 P86 P87 P70 P71 P72 P73 P74 PD0 PD1 TEST V SS V D1 PD3 OSC4 PD2 OSC3 P53 P52 SDACOUT_N P51 SDACOUT_P P50 P27 UPMUX P26 UPMUX P25 UPMUX P24 UPMUX P23 RFIN0 UPMUX P22 REF0 UPMUX P21 SENA0 UPMUX P20 SENB0 UPMUX P64 P63 P62 EXSVD1 P61 EXSVD0 P46...

Page 22: ...IN0 UPMUX P22 REF0 UPMUX P21 SENA0 UPMUX P20 SENB0 UPMUX P67 P66 P65 P64 P63 P62 EXSVD1 P61 EXSVD0 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P60 P47 P46 P45 P44 P43 P42 P41 P40 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 P60 P47 P46 RTC1S P45 ADTRG0 P44 P43 P42 P41 P40 V...

Page 23: ...input P00 P00 I O Hi Z I O port UPMUX I O User selected I O universal port multiplexer P01 P01 I O Hi Z I O port UPMUX I O User selected I O universal port multiplexer P02 P02 I O Hi Z I O port UPMUX I O User selected I O universal port multiplexer P03 P03 I O Hi Z I O port UPMUX I O User selected I O universal port multiplexer P04 P04 I O Hi Z I O port UPMUX I O User selected I O universal port m...

Page 24: ...PMUX I O User selected I O universal port multiplexer P26 P26 I O Hi Z I O port UPMUX I O User selected I O universal port multiplexer P27 P27 I O Hi Z I O port UPMUX I O User selected I O universal port multiplexer P30 P30 I O Hi Z I O port RFCLKO0 O R F converter Ch 0 clock monitor output UPMUX I O User selected I O universal port multiplexer P31 P31 I O Hi Z I O port REMO O IR remote controller...

Page 25: ... P77 P77 I O Hi Z I O port P80 P80 I O Hi Z I O port P81 P81 I O Hi Z I O port P82 P82 I O Hi Z I O port P83 P83 I O Hi Z I O port EXOSC I Clock generator external clock input P84 P84 I O Hi Z I O port EXCL00 I 16 bit PWM timer Ch 0 event counter input 0 P85 P85 I O Hi Z I O port EXCL01 I 16 bit PWM timer Ch 0 event counter input 1 P86 P86 I O Hi Z I O port P87 P87 I O Hi Z I O port P90 P90 I O Hi...

Page 26: ...nput output function to be assigned to each pin from those listed below Table 1 3 2 2 Peripheral Circuit Input output Function Selectable by UPMUX Peripheral circuit Signal to be assigned I O Channel number n Function I2C I2C SCLn I O n 0 2 I2C Ch n clock input output SDAn I O I2C Ch n data input output UART UART3 USINn I n 0 2 UART3 Ch n data input USOUTn O UART3 Ch n data output Synchronous seri...

Page 27: ... and mode1 and setting the VD1 regulator into mode1 during low speed operation helps achieve low power operations Figure 2 1 1 1 shows the PWGA configuration CVDDQSPI PWGA Internal circuits VD1 regulator VDD VDD or another external power supply VD1 VD1 VSS REGMODE 1 0 REGSEL REGDIS CPW1 CPW2 I O ports except for P9 port groups Quad synchronous serial interface and I O ports P9 port group VDDQSPI F...

Page 28: ...le 2 1 4 1 System Clock Stop Period After Switching Voltage Mode System clock Stop period IOSC 4 096 cycles OSC1 Number of cycles set using the CLGOSC1 OSC1WT 1 0 bits Procedure to switch from mode0 to mode1 1 Set the MODEN bits of the peripheral circuits to 0 Stop using peripheral circuits 2 Write 0x0096 to the SYSPROT PROT 15 0 bits Remove system protection 3 Switch the system clock to a low spe...

Page 29: ...s un stable after power on or the oscillation frequency is unstable after the clock source is initiated Supports reset requests from multiple reset sources RESET pin POR and BOR Reset request from the CPU Watchdog timer reset Supply voltage detector reset Peripheral circuit software reset supports some peripheral circuits only The CPU registers and peripheral circuit control bits will be reset wit...

Page 30: ...ET state CPU RUN state X RST RUN VDD VSS VRST VRST VRST VRST VRST X X X RST RST RST RST RUN RUN RUN Figure 2 2 3 1 Example of Internal Reset by POR and BOR For the POR and BOR electrical specifications refer to POR BOR characteristics in the Electrical Charac teristics chapter Reset request from the CPU The CPU issues a reset request by writing 1 to the AIRCR SYSRESETREQ bit in the system control ...

Page 31: ...peripheral circuits The main features of CLG are outlined below Supports multiple clock sources IOSC oscillator circuit that oscillates with a fast startup and no external parts required Low power OSC1 oscillator circuit in which the oscillator type can be specified from high precision 32 768 kHz crystal oscillator an external resonator is required and internal oscillator 16 MHz max high speed OSC...

Page 32: ...1 OSC2 X tal1 Figure 2 3 1 1 CLG Configuration 2 3 2 Input Output Pins Table 2 3 2 1 lists the CLG pins Table 2 3 2 1 List of CLG Pins Pin name I O Initial status Function OSC1 A OSC1 oscillator circuit input OSC2 A OSC1 oscillator circuit output OSC3 A OSC3 oscillator circuit input OSC4 A OSC3 oscillator circuit output EXOSC I I EXOSC clock input FOUT O O L FOUT clock output Indicates the status ...

Page 33: ...l1 OSC1STAIE OSC1STAIF OSC1STPIE OSC1STPIF Interrupt controller OSC1CLK Internal data bus Crystal oscillator OSC1EN Selector OSC1SELCR Internal oscillator Clock oscillator Figure 2 3 3 2 OSC1 Oscillator Circuit Configuration Crystal oscillator This oscillator circuit includes a gain controlled oscillation inverter and a variable gate capacitor allowing use of various crystal resonators 32 768 kHz ...

Page 34: ...d gain controlled inverter allows selection of the resonator from a wide frequency range Internal oscillator This oscillator circuit features a fast startup and no external parts are required for oscillating The OSC3CLK frequency can be selected using the CLGOSC3 OSC3FQ 1 0 bits This oscillator circuit is equipped with an auto trimming function that automatically adjusts the frequency This helps r...

Page 35: ...ock using the FOUT output function The oscillation stabilization waiting time for the IOSC oscillator circuit is fixed at 16 IOSCCLK clocks The oscillation stabilization waiting time for the OSC1 oscillator circuit should be set to 16 384 OSC1CLK clocks or more when crystal oscillator is selected or 4 096 OSC1CLK clocks or more when internal oscillator is selected The oscillation stabilization wai...

Page 36: ... OSC1SELCR bit Select oscillator type CLGOSC1 OSC1WT 1 0 bits Set oscillation stabilization waiting time In addition to the above configure the following bits when using the crystal oscillator CLGOSC1 INV1N 1 0 bits Set oscillation inverter gain CLGOSC1 CGI1 2 0 bits Set internal gate capacitor CLGOSC1 INV1B 1 0 bits Set oscillation inverter gain for startup boosting period CLGOSC1 OSC1BUP bit Ena...

Page 37: ...er to Operating Mode Clock control in SLEEP mode Whether the clock sources being operated are stopped or not when the CPU enters SLEEP mode deep sleep mode can be selected in each source individually This allows the CPU to fast switch between SLEEP mode and RUN mode and the peripheral circuits to continue operating without disabling the clock in SLEEP mode The CLGOSC IOSCSLPC CLGOSC OSC1SLPC CLGOS...

Page 38: ...ratio Set the CLGFOUT FOUTEN bit to 1 Enable clock external output OSC3 oscillation auto trimming function The auto trimming function adjusts the OSC3CLK clock frequency by trimming the clock with reference to the high precision OSC1CLK clock generated by the OSC1 oscillator circuit crystal oscillator However this function is effective only when 16 MHz CLGOSC3 OSC3FQ 1 0 bits 0x3 has been selected...

Page 39: ...ter power is turned on VDD Reset request from POR IOSCCLK Initial SYSCLK Internal reset signal SYSRST H0 H1 Cortex M0 core program counter PC Cancel reset request Undefined Undefined 1 1 Reset vector reset handler start address 2 Address reset vector 2 2 Cancel reset request Reset hold time tRSTR Figure 2 4 1 1 Initial Boot Sequence Note The reset cancelation time at power on varies according to t...

Page 40: ...n c e l a t i o n s i g n a l W F I W F E i n s t r u c t i o n S L E E P D E E P 0 RUN SLEEP WFI WFE instruction SLEEPDEEP 1 HALT SLEEP cancelation signal wake up W F I W F E i n s t r u c t i o n S L E E P D E E P 0 H A L T S L E E P c a n c e l a t i o n s i g n a l C L G S C L K C L K S R C 1 0 0 x 1 C L G S C L K C L K S R C 1 0 0 x 0 EXOSC RUN C L G S C L K C L K S R C 1 0 0 x 2 C L G S C L ...

Page 41: ...ming completion CLGINTF OSC3TEDIF When the OSC3 oscillation auto trimming opera tion has completed Writing 1 OSC3 oscillation auto trimming error CLGINTF OSC3TERIF When the OSC3 oscillation auto trimming opera tion has terminated due to an error Writing 1 CLG provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the CPU core only when the interrupt fla...

Page 42: ...se bits select the SYSCLK division ratio for resetting the CLGSCLK CLKDIV 1 0 bits at wake up This setting is ineffective when the CLGSCLK WUPMD bit 0 Bits 11 10 Reserved Bits 9 8 WUPSRC 1 0 These bits select the SYSCLK clock source for resetting the CLGSCLK CLKSRC 1 0 bits at wake up When a currently stopped clock source is selected it will automatically start oscillating or clock input at wake u...

Page 43: ...Reserved Bit 11 EXOSCSLPC Bit 10 OSC3SLPC Bit 9 OSC1SLPC Bit 8 IOSCSLPC These bits control the clock source operations in SLEEP mode 1 R W Stop clock source in SLEEP mode 0 R W Continue operation state before SLEEP Each bit corresponds to the clock source as follows CLGOSC EXOSCSLPC bit EXOSC clock input CLGOSC OSC3SLPC bit OSC3 oscillator circuit CLGOSC OSC1SLPC bit OSC1 oscillator circuit CLGOSC...

Page 44: ...P Bit 15 Reserved Bit 14 OSDRB This bit enables the OSC1 oscillator circuit restart function by the oscillation stop detector when OSC1 oscillation stop is detected 1 R WP Enable Restart the OSC1 oscillator circuit when oscillation stop is detected 0 R WP Disable Bit 13 OSDEN This bit controls the oscillation stop detector in the OSC1 oscillator circuit 1 R WP OSC1 oscillation stop detector on 0 R...

Page 45: ... equal to or larger than the CLGOSC1 INV1N 1 0 bits Bits 5 4 INV1N 1 0 These bits set the oscillation inverter gain applied at normal operation of the OSC1 oscillator circuit Table 2 6 7 Setting Oscillation Inverter Gain at OSC1 Normal Operation CLGOSC1 INV1N 1 0 bits Inverter gain 0x3 Max 0x2 0x1 0x0 Min Bits 3 2 Reserved Bits 1 0 OSC1WT 1 0 These bits set the oscillation stabilization waiting ti...

Page 46: ...n 0x3 Max 0x2 0x1 0x0 Min Bit 3 OSC3STM This bit controls the OSC3CLK auto trimming function 1 WP Start trimming 0 WP Stop trimming 1 R Trimming is executing 0 R Trimming has finished Trimming operation inactivated This bit is automatically cleared to 0 when trimming has finished Notes The auto trimming function does not work if the OSC1 oscillator circuit is stopped Make sure the CLGINTF OSC1STAI...

Page 47: ...effective Each bit corresponds to the interrupt as follows CLGINTF OSC3TERIF bit OSC3 oscillation auto trimming error interrupt CLGINTF OSC1STPIF bit OSC1 oscillation stop interrupt CLGINTF OSC3TEDIF bit OSC3 oscillation auto trimming completion interrupt CLGINTF OSC3STAIF bit OSC3 oscillation stabilization waiting completion interrupt CLGINTF OSC1STAIF bit OSC1 oscillation stabilization waiting c...

Page 48: ...marks CLGFOUT 15 8 0x00 R 7 0 R 6 4 FOUTDIV 2 0 0x0 H0 R W 3 2 FOUTSRC 1 0 0x0 H0 R W 1 0 R 0 FOUTEN 0 H0 R W Bits 15 7 Reserved Bits 6 4 FOUTDIV 2 0 These bits set the FOUT clock division ratio Bits 3 2 FOUTSRC 1 0 These bits select the FOUT clock source Table 2 6 12 FOUT Clock Source and Division Ratio Settings CLGFOUT FOUTDIV 2 0 bits CLGFOUT FOUTSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSCCLK OSC1CLK OSC...

Page 49: ...ns Table 3 3 3 1 lists the debug pins Table 3 3 1 1 List of Debug Pins Pin name I O Initial state Function SWCLK O O On chip debugger clock input pin Input a clock from a debugging tool SWD I O I On chip debugger data input output pin Used to input output debugging data The debugger input output pins are shared with general purpose I O ports and are initially set as the debug pins If the debugging...

Page 50: ...000 0xe000 0000 0xdfff ffff Reserved 0xdfff ffff Reserved 0x0020 4000 0x0020 4000 0x0020 3fff Peripheral circuit area 12K bytes Device size 32 bits 0x0020 3fff Peripheral circuit area 12K bytes Device size 32 bits 0x0020 1000 0x0020 1000 0x0020 0fff Peripheral circuit area 4K bytes Device size 16 bits 0x0020 0fff Peripheral circuit area 4K bytes Device size 16 bits 0x0020 0000 0x0020 0000 0x001f f...

Page 51: ...ash memory pin Table 4 3 1 1 Flash Memory Pin Pin name I O Initial status Function VPP P Flash programming power supply For the VPP voltage refer to Recommended Operating Conditions Flash programming voltage VPP in the Elec trical Characteristics chapter Note Always leave the VPP pin open except when programming the Flash memory 4 3 2 Flash Bus Access Cycle Setting There is a limit of frequency to...

Page 52: ... 0080 CACHECTL CACHE Control Register Watchdog timer WDT2 0x0020 00a0 WDT2CLK WDT2 Clock Control Register 0x0020 00a2 WDT2CTL WDT2 Control Register 0x0020 00a4 WDT2CMP WDT2 Counter Compare Match Register Real time clock RTCA 0x0020 00c0 RTCACTLL RTCA Control Register Low Byte 0x0020 00c1 RTCACTLH RTCA Control Register High Byte 0x0020 00c2 RTCAALM1 RTCA Second Alarm Register 0x0020 00c4 RTCAALM2 R...

Page 53: ...PORTP4INTF P4 Port Interrupt Flag Register 0x0020 0248 PPORTP4INTCTL P4 Port Interrupt Control Register 0x0020 024a PPORTP4CHATEN P4 Port Chattering Filter Enable Register 0x0020 024c PPORTP4MODSEL P4 Port Mode Select Register 0x0020 024e PPORTP4FNCSEL P4 Port Function Select Register 0x0020 0250 PPORTP5DAT P5 Port Data Register 0x0020 0252 PPORTP5IOEN P5 Port Enable Register 0x0020 0254 PPORTP5RC...

Page 54: ...20 030a UPMUXP1MUX1 P12 13 Universal Port Multiplexer Setting Register 0x0020 030c UPMUXP1MUX2 P14 15 Universal Port Multiplexer Setting Register 0x0020 030e UPMUXP1MUX3 P16 17 Universal Port Multiplexer Setting Register 0x0020 0310 UPMUXP2MUX0 P20 21 Universal Port Multiplexer Setting Register 0x0020 0312 UPMUXP2MUX1 P22 23 Universal Port Multiplexer Setting Register 0x0020 0314 UPMUXP2MUX2 P24 2...

Page 55: ...h 0 Compare Capture 2 Control Register 0x0020 0422 T16B_0CCR2 T16B Ch 0 Compare Capture 2 Data Register 0x0020 0424 T16B_0CC2DMAEN T16B Ch 0 Compare Capture 2 DMA Request Enable Register 0x0020 0428 T16B_0CCCTL3 T16B Ch 0 Compare Capture 3 Control Register 0x0020 042a T16B_0CCR3 T16B Ch 0 Compare Capture 3 Data Register 0x0020 042c T16B_0CC3DMAEN T16B Ch 0 Compare Capture 3 DMA Request Enable Regi...

Page 56: ...fer Empty DMA Request Enable Register 0x0020 0612 UART3_1 RB1FDMAEN UART3 Ch 1 Receive Buffer One Byte Full DMA Request Enable Register 0x0020 0614 UART3_1CAWF UART3 Ch 1 Carrier Waveform Register UART UART3 Ch 2 0x0020 0620 UART3_2CLK UART3 Ch 2 Clock Control Register 0x0020 0622 UART3_2MOD UART3 Ch 2 Mode Register 0x0020 0624 UART3_2BR UART3 Ch 2 Baud Rate Register 0x0020 0626 UART3_2CTL UART3 C...

Page 57: ... Register 0x0020 06e4 I2C_2BR I2C Ch 2 Baud Rate Register 0x0020 06e8 I2C_2OADR I2C Ch 2 Own Address Register 0x0020 06ea I2C_2CTL I2C Ch 2 Control Register 0x0020 06ec I2C_2TXD I2C Ch 2 Transmit Data Register 0x0020 06ee I2C_2RXD I2C Ch 2 Receive Data Register 0x0020 06f0 I2C_2INTF I2C Ch 2 Status and Interrupt Flag Register 0x0020 06f2 I2C_2INTE I2C Ch 2 Interrupt Enable Register 0x0020 06f4 I2C...

Page 58: ...egister 0x0020 1014 DMACSWREQ DMAC Software Request Register 0x0020 1020 DMACRMSET DMAC Request Mask Set Register 0x0020 1024 DMACRMCLR DMAC Request Mask Clear Register 0x0020 1028 DMACENSET DMAC Enable Set Register 0x0020 102c DMACENCLR DMAC Enable Clear Register 0x0020 1030 DMACPASET DMAC Primary Alternate Set Register 0x0020 1034 DMACPACLR DMAC Primary Alternate Clear Register 0x0020 1038 DMACP...

Page 59: ...WP or R WP appearing in the R W column CACHE Control Register Register name Bit Bit name Initial Reset R W Remarks CACHECTL 15 8 0x00 R 7 2 0x00 R 1 1 R 0 CACHEEN 0 H0 R W Bits 15 1 Reserved Bit 0 CACHEEN This bit enables the instruction cache function 1 R W Enable instruction cache 0 R W Disable instruction cache FLASHC Flash Read Cycle Register Register name Bit Bit name Initial Reset R W Remark...

Page 60: ...terrupt Priority VTOR 0x00 Stack pointer initial value 1 VTOR 0x04 Reset Low input to the RESET pin Power on reset Key reset Watchdog timer overﬂow 1 Supply voltage detector reset 3 2 14 VTOR 0x08 NMI Watchdog timer overﬂow 1 2 3 13 VTOR 0x0c HardFault Bus error Undefined instruction Unaligned address etc 1 4 10 Reserved 11 5 VTOR 0x2c SVCall SVC instruction Configurable 12 13 Reserved 14 2 VTOR 0...

Page 61: ... reception NACK reception STOP condition START condition Error detection Receive buﬀer full Transmit buﬀer empty 29 13 VTOR 0x74 16 bit PWM timer Ch 0 inter rupt Capture overwrite Compare capture Counter MAX Counter zero 30 14 VTOR 0x78 16 bit PWM timer Ch 1 inter rupt Capture overwrite Compare capture Counter MAX Counter zero 31 15 VTOR 0x7c UART Ch 1 interrupt End of transmission Framing error P...

Page 62: ...the offset start address of the vector table in which interrupt vectors are programmed VTOR described in Table 5 2 1 means the value set to this register After an initial reset VTOR is set to address 0x0 Therefore even when the vector table location is changed it is necessary that at least the reset vector be written to this address For more information on VTOR refer to the Cortex M0 Technical Ref...

Page 63: ...f unnecessary interrupts the corresponding interrupt flag should be cleared before setting the interrupt enable bit to 1 interrupt enabled and before terminating the interrupt handler routine 5 4 NMI The watchdog timer embedded in this IC can generate a non maskable interrupt NMI This interrupt takes prece dence over other interrupts and is unconditionally accepted by the CPU For detailed informat...

Page 64: ...guration of the DMAC Table 6 1 1 DMAC Channel Configuration of S1C31D50 D51 Item 48 pin package 64 pin package 80 pin package 100 pin package Number of channels 4 channels Ch 0 to Ch 3 Transfer source memories Internal Flash memory external Flash memory and RAM Transfer destination memories RAM Transfer source peripheral circuits UART3 SPIA QSPI I2C T16B and ADC12A Transfer destination peripheral ...

Page 65: ...priority level is set to 1 by the DMACPRSET PRSETn bit has the high est priority If two or more channels have been set to the same priority level the smaller channel number takes pre cedence 6 4 Data Structure To perform DMA transfers a data structure that contains basic transfer control information must be provided The data structure consists of two blocks primary data structure and alternate dat...

Page 66: ...Ch 2 primary Ch 1 primary Ch 0 primary 0x1f0 0x1e0 0x1d0 0x1c0 0x1b0 0x1a0 0x190 0x180 0x170 0x160 0x150 0x140 0x130 0x120 0x110 0x100 0x0f0 0x0e0 0x0d0 0x0c0 0x0b0 0x0a0 0x090 0x080 0x070 0x060 0x050 0x040 0x030 0x020 0x010 0x000 Primary data structure Base address set with the DMACCPTR register Offset Reserved Control data Transfer destination end pointer Transfer source end pointer 0x00c 0x008 ...

Page 67: ...size Table 6 4 3 2 Size of Data Written to Transfer Destination dst_size Data size 0x3 Reserved 0x2 Word 0x1 Halfword 0x0 Byte src_inc Set the increment value of the transfer source address The setting value must be equal to or larger than the transfer data size when the address is incremented Table 6 4 3 3 Increment Value of Transfer Source Address src_inc Increment value 0x3 No increment 0x2 4 0...

Page 68: ...or a software DMA request is issued and it continues until it is completed for the set number of suc cessive transfers or it is suspended at the arbitration cycle To resume the DMA transfer suspended at the arbitration cycle a DMA transfer request must be reissued When the set number of successive transfers has completed a transfer completion interrupt occurs DMA transfer 1 DMA transfer 2 DMA tran...

Page 69: ...errupt Task D DMA transfer request DMA transfer request DMA transfer completion interrupt Task E DMA transfer request DMA transfer completion interrupt Termination cycle_ctrl 0x3 2R 4 N 6 cycle_ctrl 0x3 2R 4 N 12 cycle_ctrl 0x3 2R 2 N 2 cycle_ctrl 0x3 2R 4 N 5 cycle_ctrl 0x3 2R 4 N 7 cycle_ctrl 0x0 Figure 6 5 3 1 Ping Pong Transfer Operation Example DMA transfer procedure 1 Start data transfer by ...

Page 70: ...Transfer destination end pointer Transfer source end pointer Data structure for Task C Reserved Control data Transfer destination end pointer Transfer source end pointer Data structure for Task D Reserved Control data Transfer destination end pointer Transfer source end pointer Figure 6 5 4 1 Example of Data Structure Table for Scatter Gather Transfer Task A setting DMA transfer request Task A cyc...

Page 71: ...he other hand in peripheral scatter gather transfer mode all DMA transfers are performed by a DMA transfer request issued by a peripheral circuit or a software DMA request Task A setting DMA transfer request DMA transfer request DMA transfer request DMA transfer request Task A cycle_ctrl 0x7 2R 4 N 3 cycle_ctrl 0x6 2R 4 N 16 Copy the data structure for Task A to the alternate data structure Data t...

Page 72: ...iled DAM transfer cycle Note that the number of clock cycles for a DMA transfer may be increased due to a conflict with an access from the CPU or the Flash bus access cycle setting SYSCLK Transfer cycle DMA transfer request rc Read control data rsp Read transfer source end pointer rdp Read transfer destination end pointer RD Read data from transfer source WD Write data to transfer destination wc W...

Page 73: ...0 bits DMA transfer status 0xf 0xbf Reserved 0xa Peripheral scatter gather transfer is in progress 0x9 Transfer has completed 0x8 Transfer has been suspended 0x7 Control data is being written 0x6 Standby for transfer request to be cleared 0x5 Transfer data is being written 0x4 Transfer data is being read 0x3 Transfer destination end pointer is being read 0x2 Transfer source end pointer is being re...

Page 74: ... H0 R Bits 31 0 ACPTR 31 0 These bits show the alternate data structure base address DMAC Software Request Register Register name Bit Bit name Initial Reset R W Remarks DMACSWREQ 31 0 SWREQ 31 0 W Bits 31 0 SWREQ 31 0 These bits issue a software DMA transfer request to each channel 1 W Issue a software DMA transfer request 0 W Ineffective Each bit corresponds to a DMAC channel e g bit n correspond...

Page 75: ...abled These bits are cleared after the DMA transfer has completed Each bit corresponds to a DMAC channel The high order bits for the unimplemented channels are ineffective DMAC Enable Clear Register Register name Bit Bit name Initial Reset R W Remarks DMACENCLR 31 0 ENCLR 31 0 W Bits 31 0 ENCLR 31 0 These bits disable each DMAC channel 1 W Disable DMAC channel The DMACENSET register is cleared to ...

Page 76: ...Ineffective 1 R Priority High 0 R Priority Normal Each bit corresponds to a DMAC channel The high order bits for the unimplemented channels are ineffective DMAC Priority Clear Register Register name Bit Bit name Initial Reset R W Remarks DMACPRCLR 31 0 PRCLR 31 0 W Bits 31 0 PRCLR 31 0 These bits decrease the priority of each channel 1 W Decrease priority The DMACPRSET register is cleared to 0 0 W...

Page 77: ...0 ENDIESET 31 0 These bits enable DMA transfer completion interrupts to be generated from each DMAC channel 1 W Enable interrupt 0 W Ineffective 1 R Interrupt has been enabled 0 R Interrupt has been disabled Each bit corresponds to a DMAC channel The high order bits for the unimplemented channels are ineffective DMAC Transfer Completion Interrupt Enable Clear Register Register name Bit Bit name In...

Page 78: ...R Interrupt has been enabled 0 R Interrupt has been disabled DMAC Error Interrupt Enable Clear Register Register name Bit Bit name Initial Reset R W Remarks DMACERRIECLR 31 24 0x00 R 23 16 0x00 R 15 8 0x00 R 7 1 0x00 R 0 ERRIECLR W Bits 31 1 Reserved Bit 0 ERRIECLR This bit disables DMA error interrupts 1 W Disable interrupt The DMACERRIESET register is cleared to 0 0 W Ineffective ...

Page 79: ...figuration of PPORT Table 7 1 1 Port Configuration of S1C31D50 D51 Item 48 pin package 64 pin package 80 pin package 100 pin package Port groups included P0 P0 6 3 4 1 2 P0 6 3 4 1 2 P0 7 3 5 1 2 P0 7 0 8 1 2 P1 P1 7 3 5 1 2 P1 7 1 7 1 2 P1 7 0 8 1 2 P1 7 0 8 1 2 P2 P2 3 0 4 1 2 P2 7 0 8 1 2 P2 7 0 8 1 2 P2 7 0 8 1 2 P3 P3 2 0 3 1 2 P3 4 0 5 1 2 P3 5 0 6 1 2 P3 7 0 8 1 2 P4 P4 6 5 P40 3 1 2 P4 6 3...

Page 80: ... and Functions Figure 7 2 1 shows the I O cell Configuration Pull up down Control signal Over voltage tolerant fail safe type I O cell Input signal Input control signal Output signal Output control signal Analog signal Analog control signal Pull up down Control signal Input signal Input control signal Output signal Output control signal Analog signal Analog control signal Pull up down control Anal...

Page 81: ...igh low second VT High level Schmitt input threshold voltage V VT Low level Schmitt input threshold voltage V RINU RIND Pull up pull down resistance W CIN Pin capacitance F CBOARD Parasitic capacitance on the board F 7 2 4 CMOS Output and High Impedance State The I O cells except for analog output can output signals in the VDD and VSS levels Also the GPIO ports may be put into high impedance Hi Z ...

Page 82: ...Port pins High impedance state Port function Configured to GPIO This status continues until the ports are configured via software The debugging function ports are configured for debug signal input output Initial settings when using a port for a peripheral I O function When using the Pxy port for a peripheral I O function perform the following software initial settings 1 Set the following PPORTPxIO...

Page 83: ... Set the PPORTPxIOEN PxOENy bit to 0 Disable output Set the PPORTPxIOEN PxIENy bit to 1 Enable input Steps 1 and 5 are required for the ports with an interrupt function Step 2 is required for the ports with a chat tering filter function Table 7 4 1 1 lists the port status according to the combination of data input output control and pull up down control Table 7 4 1 1 GPIO Port Control List PPORTPx...

Page 84: ...s when using this function 1 Configure the ports to be used for key entry reset as general purpose input ports refer to Initial settings when using a port as a general purpose input port only for the ports with GPIO function 2 Configure the input pin combination for key entry reset using the PPORTCLK KRSTCFG 1 0 bits Note When enabling the key entry reset function be sure to configure the port pin...

Page 85: ...l value may be changed by the port Bits 15 8 PxOUT 7 0 These bits are used to set data to be output from the GPIO port pins 1 R W Output high level from the port pin 0 R W Output low level from the port pin When output is enabled PPORTPxIOEN PxOENy bit 1 the port pin outputs the data set here Al though data can be written when output is disabled PPORTPxIOEN PxOENy bit 0 it does not affect the pin ...

Page 86: ...wn the port when output is disabled PPORTPxIOEN PxOENy bit 0 When output is enabled PPORTPxIOEN PxOENy bit 1 the PPORTPxRCTL PxRENy bit setting is ineffective regardless of how the PPORTPxIOEN PxIENy bit is set and the port is not pulled up down These bits do not affect the pull up down control when the port is used as a peripheral I O function Px Port Interrupt Flag Register Register name Bit Bit...

Page 87: ...e bit configuration differs depending on the port group 2 The initial value may be changed by the port Bits 15 8 Reserved Bits 7 0 PxSEL 7 0 These bits select whether each port is used for the GPIO function or a peripheral I O function 1 R W Use peripheral I O function 0 R W Use GPIO function Px Port Function Select Register Register name Bit Bit name Initial Reset R W Remarks PPORTPxFNCSEL 15 14 ...

Page 88: ... 1 0 bits key entry reset 0x3 Reset when P0 3 0 inputs all low 0x2 Reset when P0 2 0 inputs all low 0x1 Reset when P0 1 0 inputs all low 0x0 Disable Bits 1 0 CLKSRC 1 0 These bits select the clock source of PPORT chattering filter The PPORT operating clock should be configured by selecting the clock source using the PPORT CLK CLKSRC 1 0 bits and the clock division ratio using the PPORTCLK CLKDIV 3...

Page 89: ...P6INT 0 H0 R 5 P5INT 0 H0 R 4 P4INT 0 H0 R 3 P3INT 0 H0 R 2 P2INT 0 H0 R 1 P1INT 0 H0 R 0 P0INT 0 H0 R 1 Only the bits corresponding to the port groups that support interrupts are provided Bits 15 13 Reserved Bits 12 0 PxINT These bits indicate that Px port group includes a port that has generated an interrupt 1 R A port generated an interrupt 0 R No port generated an interrupt The PPORTINTFGRP Px...

Page 90: ...R W Remarks 48 pin 64 pin 80 pin 100 pin P0DAT P0 Port Data Register 15 P0OUT7 0 H0 R W 14 P0OUT6 0 H0 R W 13 P0OUT5 0 H0 R W 12 P0OUT4 0 H0 R W 11 P0OUT3 0 H0 R W 10 P0OUT2 0 H0 R W 9 P0OUT1 0 H0 R W 8 P0OUT0 0 H0 R W 7 P0IN7 0 H0 R 6 P0IN6 0 H0 R 5 P0IN5 0 H0 R 4 P0IN4 0 H0 R 3 P0IN3 0 H0 R 2 P0IN2 0 H0 R 1 P0IN1 0 H0 R 0 P0IN0 0 H0 R P0IOEN P0 Port Enable Register 15 P0IEN7 0 H0 R W 14 P0IEN6 0...

Page 91: ...Register 15 8 0x00 R 7 P0IF7 0 H0 R W Cleared by writing 1 6 P0IF6 0 H0 R W 5 P0IF5 0 H0 R W 4 P0IF4 0 H0 R W 3 P0IF3 0 H0 R W 2 P0IF2 0 H0 R W 1 P0IF1 0 H0 R W 0 P0IF0 0 H0 R W P0INTCTL P0 Port Interrupt Control Register 15 P0EDGE7 0 H0 R W 14 P0EDGE6 0 H0 R W 13 P0EDGE5 0 H0 R W 12 P0EDGE4 0 H0 R W 11 P0EDGE3 0 H0 R W 10 P0EDGE2 0 H0 R W 9 P0EDGE1 0 H0 R W 8 P0EDGE0 0 H0 R W 7 P0IE7 0 H0 R W 6 P...

Page 92: ...y 0 P0SELy 1 48 pin 64 pin 80 pin 100 pin GPIO P0yMUX 0x0 Function 0 P0yMUX 0x1 Function 1 P0yMUX 0x2 Function 2 P0yMUX 0x3 Function 3 Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin P00 P00 UPMUX 1 P01 P01 UPMUX 1 P02 P02 UPMUX 1 P03 P03 UPMUX 1 P04 P04 UPMUX 1 P05 P05 UPMUX 1 P06 P06 UPMUX 1 P07 P07 UPMUX 1 1 Refer to the Universal Port Multiplexer chapter 7 7 2 P1 Port Group The P1 ...

Page 93: ...0 R W 12 P1PDPU4 0 H0 R W 11 P1PDPU3 0 H0 R W 10 P1PDPU2 0 H0 R W 9 P1PDPU1 0 H0 R W 8 P1PDPU0 0 H0 R W 7 P1REN7 0 H0 R W 6 P1REN6 0 H0 R W 5 P1REN5 0 H0 R W 4 P1REN4 0 H0 R W 3 P1REN3 0 H0 R W 2 P1REN2 0 H0 R W 1 P1REN1 0 H0 R W 0 P1REN0 0 H0 R W P1INTF P1 Port Interrupt Flag Register 15 8 0x00 R 7 P1IF7 0 H0 R W Cleared by writing 1 6 P1IF6 0 H0 R W 5 P1IF5 0 H0 R W 4 P1IF4 0 H0 R W 3 P1IF3 0 H0...

Page 94: ...CSEL P1 Port Function Select Register 15 14 P17MUX 1 0 0x0 H0 R W 13 12 P16MUX 1 0 0x0 H0 R W 11 10 P15MUX 1 0 0x0 H0 R W 9 8 P14MUX 1 0 0x0 H0 R W 7 6 P13MUX 1 0 0x0 H0 R W 5 4 P12MUX 1 0 0x0 H0 R W 3 2 P11MUX 1 0 0x0 H0 R W 1 0 P10MUX 1 0 0x0 H0 R W Table 7 7 2 2 P1 Port Group Function Assignment Port name P1SELy 0 P1SELy 1 48 pin 64 pin 80 pin 100 pin GPIO P1yMUX 0x0 Function 0 P1yMUX 0x1 Funct...

Page 95: ... R 3 P2IN3 0 H0 R 2 P2IN2 0 H0 R 1 P2IN1 0 H0 R 0 P2IN0 0 H0 R P2IOEN P2 Port Enable Register 15 P2IEN7 0 H0 R W 14 P2IEN6 0 H0 R W 13 P2IEN5 0 H0 R W 12 P2IEN4 0 H0 R W 11 P2IEN3 0 H0 R W 10 P2IEN2 0 H0 R W 9 P2IEN1 0 H0 R W 8 P2IEN0 0 H0 R W 7 P2OEN7 0 H0 R W 6 P2OEN6 0 H0 R W 5 P2OEN5 0 H0 R W 4 P2OEN4 0 H0 R W 3 P2OEN3 0 H0 R W 2 P2OEN2 0 H0 R W 1 P2OEN1 0 H0 R W 0 P2OEN0 0 H0 R W P2RCTL P2 Po...

Page 96: ... P2IE6 0 H0 R W 5 P2IE5 0 H0 R W 4 P2IE4 0 H0 R W 3 P2IE3 0 H0 R W 2 P2IE2 0 H0 R W 1 P2IE1 0 H0 R W 0 P2IE0 0 H0 R W P2CHATEN P2 Port Chattering Filter Enable Register 15 8 0x00 R 7 P2CHATEN7 0 H0 R W 6 P2CHATEN6 0 H0 R W 5 P2CHATEN5 0 H0 R W 4 P2CHATEN4 0 H0 R W 3 P2CHATEN3 0 H0 R W 2 P2CHATEN2 0 H0 R W 1 P2CHATEN1 0 H0 R W 0 P2CHATEN0 0 H0 R W P2MODSEL P2 Port Mode Select Register 15 8 0x00 R 7...

Page 97: ...p supports the GPIO and interrupt functions Table 7 7 4 1 Control Registers for P3 Port Group Register name Bit Bit name Initial Reset R W Remarks 48 pin 64 pin 80 pin 100 pin P3DAT P3 Port Data Register 15 P3OUT7 0 H0 R W 14 P3OUT6 0 H0 R W 13 P3OUT5 0 H0 R W 12 P3OUT4 0 H0 R W 11 P3OUT3 0 H0 R W 10 P3OUT2 0 H0 R W 9 P3OUT1 0 H0 R W 8 P3OUT0 0 H0 R W 7 P3IN7 0 H0 R 6 P3IN6 0 H0 R 5 P3IN5 0 H0 R 4...

Page 98: ...Register 15 8 0x00 R 7 P3IF7 0 H0 R W Cleared by writing 1 6 P3IF6 0 H0 R W 5 P3IF5 0 H0 R W 4 P3IF4 0 H0 R W 3 P3IF3 0 H0 R W 2 P3IF2 0 H0 R W 1 P3IF1 0 H0 R W 0 P3IF0 0 H0 R W P3INTCTL P3 Port Interrupt Control Register 15 P3EDGE7 0 H0 R W 14 P3EDGE6 0 H0 R W 13 P3EDGE5 0 H0 R W 12 P3EDGE4 0 H0 R W 11 P3EDGE3 0 H0 R W 10 P3EDGE2 0 H0 R W 9 P3EDGE1 0 H0 R W 8 P3EDGE0 0 H0 R W 7 P3IE7 0 H0 R W 6 P...

Page 99: ...in 64 pin 80 pin 100 pin GPIO P3yMUX 0x0 Function 0 P3yMUX 0x1 Function 1 P3yMUX 0x2 Function 2 P3yMUX 0x3 Function 3 Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin P30 P30 RFC RFCLKO0 UPMUX 1 P31 P31 REMC3 REMO UPMUX 1 P32 P32 REMC3 CLPLS UPMUX 1 P33 P33 UPMUX 1 P34 P34 UPMUX 1 P35 P35 UPMUX 1 P36 P36 UPMUX 1 P37 P37 UPMUX 1 1 Refer to the Universal Port Multiplexer chapter 7 7 5 P4 ...

Page 100: ...0 R W 12 P4PDPU4 0 H0 R W 11 P4PDPU3 0 H0 R W 10 P4PDPU2 0 H0 R W 9 P4PDPU1 0 H0 R W 8 P4PDPU0 0 H0 R W 7 P4REN7 0 H0 R W 6 P4REN6 0 H0 R W 5 P4REN5 0 H0 R W 4 P4REN4 0 H0 R W 3 P4REN3 0 H0 R W 2 P4REN2 0 H0 R W 1 P4REN1 0 H0 R W 0 P4REN0 0 H0 R W P4INTF P4 Port Interrupt Flag Register 15 8 0x00 R 7 P4IF7 0 H0 R W Cleared by writing 1 6 P4IF6 0 H0 R W 5 P4IF5 0 H0 R W 4 P4IF4 0 H0 R W 3 P4IF3 0 H0...

Page 101: ... P4SEL4 0 H0 R W 3 P4SEL3 0 H0 R W 2 P4SEL2 0 H0 R W 1 P4SEL1 0 H0 R W 0 P4SEL0 0 H0 R W P4FNCSEL P4 Port Function Select Register 15 14 P47MUX 1 0 0x0 H0 R W 13 12 P46MUX 1 0 0x0 H0 R W 11 10 P45MUX 1 0 0x0 H0 R W 9 8 P44MUX 1 0 0x0 H0 R W 7 6 P43MUX 1 0 0x0 H0 R W 5 4 P42MUX 1 0 0x0 H0 R W 3 2 P41MUX 1 0 0x0 H0 R W 1 0 P40MUX 1 0 0x0 H0 R W Table 7 7 5 2 P4 Port Group Function Assignment Port na...

Page 102: ... R 3 P5IN3 0 H0 R 2 P5IN2 0 H0 R 1 P5IN1 0 H0 R 0 P5IN0 0 H0 R P5IOEN P5 Port Enable Register 15 P5IEN7 0 H0 R W 14 P5IEN6 0 H0 R W 13 P5IEN5 0 H0 R W 12 P5IEN4 0 H0 R W 11 P5IEN3 0 H0 R W 10 P5IEN2 0 H0 R W 9 P5IEN1 0 H0 R W 8 P5IEN0 0 H0 R W 7 P5OEN7 0 H0 R W 6 P5OEN6 0 H0 R W 5 P5OEN5 0 H0 R W 4 P5OEN4 0 H0 R W 3 P5OEN3 0 H0 R W 2 P5OEN2 0 H0 R W 1 P5OEN1 0 H0 R W 0 P5OEN0 0 H0 R W P5RCTL P5 Po...

Page 103: ... P5IE6 0 H0 R W 5 P5IE5 0 H0 R W 4 P5IE4 0 H0 R W 3 P5IE3 0 H0 R W 2 P5IE2 0 H0 R W 1 P5IE1 0 H0 R W 0 P5IE0 0 H0 R W P5CHATEN P5 Port Chattering Filter Enable Register 15 8 0x00 R 7 P5CHATEN7 0 H0 R W 6 P5CHATEN6 0 H0 R W 5 P5CHATEN5 0 H0 R W 4 P5CHATEN4 0 H0 R W 3 P5CHATEN3 0 H0 R W 2 P5CHATEN2 0 H0 R W 1 P5CHATEN1 0 H0 R W 0 P5CHATEN0 0 H0 R W P5MODSEL P5 Port Mode Select Register 15 8 0x00 R 7...

Page 104: ...trol Registers for P6 Port Group Register name Bit Bit name Initial Reset R W Remarks 48 pin 64 pin 80 pin 100 pin P6DAT P6 Port Data Register 15 P6OUT7 0 H0 R W 14 P6OUT6 0 H0 R W 13 P6OUT5 0 H0 R W 12 P6OUT4 0 H0 R W 11 P6OUT3 0 H0 R W 10 P6OUT2 0 H0 R W 9 P6OUT1 0 H0 R W 8 P6OUT0 0 H0 R W 7 P6IN7 0 H0 R 6 P6IN6 0 H0 R 5 P6IN5 0 H0 R 4 P6IN4 0 H0 R 3 P6IN3 0 H0 R 2 P6IN2 0 H0 R 1 P6IN1 0 H0 R 0 ...

Page 105: ...Register 15 8 0x00 R 7 P6IF7 0 H0 R W Cleared by writing 1 6 P6IF6 0 H0 R W 5 P6IF5 0 H0 R W 4 P6IF4 0 H0 R W 3 P6IF3 0 H0 R W 2 P6IF2 0 H0 R W 1 P6IF1 0 H0 R W 0 P6IF0 0 H0 R W P6INTCTL P6 Port Interrupt Control Register 15 P6EDGE7 0 H0 R W 14 P6EDGE6 0 H0 R W 13 P6EDGE5 0 H0 R W 12 P6EDGE4 0 H0 R W 11 P6EDGE3 0 H0 R W 10 P6EDGE2 0 H0 R W 9 P6EDGE1 0 H0 R W 8 P6EDGE0 0 H0 R W 7 P6IE7 0 H0 R W 6 P...

Page 106: ...ort Group Function Assignment Port name P6SELy 0 P6SELy 1 48 pin 64 pin 80 pin 100 pin GPIO P6yMUX 0x0 Function 0 P6yMUX 0x1 Function 1 P6yMUX 0x2 Function 2 P6yMUX 0x3 Function 3 Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin P60 P60 P61 P61 SDV3 EXSVD0 P62 P62 SDV3 EXSVD1 P63 P63 P64 P64 P65 P65 P66 P66 P67 P67 7 7 8 P7 Port Group The P7 port group supports the GPIO and interrupt fu...

Page 107: ...0 R W 12 P7PDPU4 0 H0 R W 11 P7PDPU3 0 H0 R W 10 P7PDPU2 0 H0 R W 9 P7PDPU1 0 H0 R W 8 P7PDPU0 0 H0 R W 7 P7REN7 0 H0 R W 6 P7REN6 0 H0 R W 5 P7REN5 0 H0 R W 4 P7REN4 0 H0 R W 3 P7REN3 0 H0 R W 2 P7REN2 0 H0 R W 1 P7REN1 0 H0 R W 0 P7REN0 0 H0 R W P7INTF P7 Port Interrupt Flag Register 15 8 0x00 R 7 P7IF7 0 H0 R W Cleared by writing 1 6 P7IF6 0 H0 R W 5 P7IF5 0 H0 R W 4 P7IF4 0 H0 R W 3 P7IF3 0 H0...

Page 108: ...W 4 P7SEL4 0 H0 R W 3 P7SEL3 0 H0 R W 2 P7SEL2 0 H0 R W 1 P7SEL1 0 H0 R W 0 P7SEL0 0 H0 R W P7FNCSEL P7 Port Function Select Register 15 14 P77MUX 1 0 0x0 H0 R W 13 12 P76MUX 1 0 0x0 H0 R W 11 10 P75MUX 1 0 0x0 H0 R W 9 8 P74MUX 1 0 0x0 H0 R W 7 6 P73MUX 1 0 0x0 H0 R W 5 4 P72MUX 1 0 0x0 H0 R W 3 2 P71MUX 1 0 0x0 H0 R W 1 0 P70MUX 1 0 0x0 H0 R W Table 7 7 8 2 P7 Port Group Function Assignment Port...

Page 109: ... R 3 P8IN3 0 H0 R 2 P8IN2 0 H0 R 1 P8IN1 0 H0 R 0 P8IN0 0 H0 R P8IOEN P8 Port Enable Register 15 P8IEN7 0 H0 R W 14 P8IEN6 0 H0 R W 13 P8IEN5 0 H0 R W 12 P8IEN4 0 H0 R W 11 P8IEN3 0 H0 R W 10 P8IEN2 0 H0 R W 9 P8IEN1 0 H0 R W 8 P8IEN0 0 H0 R W 7 P8OEN7 0 H0 R W 6 P8OEN6 0 H0 R W 5 P8OEN5 0 H0 R W 4 P8OEN4 0 H0 R W 3 P8OEN3 0 H0 R W 2 P8OEN2 0 H0 R W 1 P8OEN1 0 H0 R W 0 P8OEN0 0 H0 R W P8RCTL P8 Po...

Page 110: ... P8IE6 0 H0 R W 5 P8IE5 0 H0 R W 4 P8IE4 0 H0 R W 3 P8IE3 0 H0 R W 2 P8IE2 0 H0 R W 1 P8IE1 0 H0 R W 0 P8IE0 0 H0 R W P8CHATEN P8 Port Chattering Filter Enable Register 15 8 0x00 R 7 P8CHATEN7 0 H0 R W 6 P8CHATEN6 0 H0 R W 5 P8CHATEN5 0 H0 R W 4 P8CHATEN4 0 H0 R W 3 P8CHATEN3 0 H0 R W 2 P8CHATEN2 0 H0 R W 1 P8CHATEN1 0 H0 R W 0 P8CHATEN0 0 H0 R W P8MODSEL P8 Port Mode Select Register 15 8 0x00 R 7...

Page 111: ...ports the GPIO and interrupt functions Table 7 7 10 1 Control Registers for P9 Port Group Register name Bit Bit name Initial Reset R W Remarks 48 pin 64 pin 80 pin 100 pin P9DAT P9 Port Data Register 15 14 0x0 R 13 P9OUT5 0 H0 R W 12 P9OUT4 0 H0 R W 11 P9OUT3 0 H0 R W 10 P9OUT2 0 H0 R W 9 P9OUT1 0 H0 R W 8 P9OUT0 0 H0 R W 7 6 0x0 R 5 P9IN5 0 H0 R 4 P9IN4 0 H0 R 3 P9IN3 0 H0 R 2 P9IN2 0 H0 R 1 P9IN...

Page 112: ...y writing 1 4 P9IF4 0 H0 R W 3 P9IF3 0 H0 R W 2 P9IF2 0 H0 R W 1 P9IF1 0 H0 R W 0 P9IF0 0 H0 R W P9INTCTL P9 Port Interrupt Control Register 15 14 0x0 R 13 P9EDGE5 0 H0 R W 12 P9EDGE4 0 H0 R W 11 P9EDGE3 0 H0 R W 10 P9EDGE2 0 H0 R W 9 P9EDGE1 0 H0 R W 8 P9EDGE0 0 H0 R W 7 6 0x0 R 5 P9IE5 0 H0 R W 4 P9IE4 0 H0 R W 3 P9IE3 0 H0 R W 2 P9IE2 0 H0 R W 1 P9IE1 0 H0 R W 0 P9IE0 0 H0 R W P9CHATEN P9 Port ...

Page 113: ...0 P92 P92 QSPI Ch 0 QSDIO01 P93 P93 QSPI Ch 0 QSDIO02 P94 P94 QSPI Ch 0 QSDIO03 P95 P95 QSPI Ch 0 QSPISS0 7 7 11 Pa Port Group The Pa port group supports the GPIO and interrupt functions Table 7 7 11 1 Control Registers for Pa Port Group Register name Bit Bit name Initial Reset R W Remarks 48 pin 64 pin 80 pin 100 pin PADAT Pa Port Data Register 15 0 R 14 PAOUT6 0 H0 R W 13 PAOUT5 0 H0 R W 12 PAOU...

Page 114: ...terrupt Flag Register 15 8 0x00 R 7 0 R 6 PAIF6 0 H0 R W Cleared by writing 1 5 PAIF5 0 H0 R W 4 PAIF4 0 H0 R W 3 PAIF3 0 H0 R W 2 PAIF2 0 H0 R W 1 PAIF1 0 H0 R W 0 PAIF0 0 H0 R W PAINTCTL Pa Port Interrupt Control Register 15 0 R 14 PAEDGE6 0 H0 R W 13 PAEDGE5 0 H0 R W 12 PAEDGE4 0 H0 R W 11 PAEDGE3 0 H0 R W 10 PAEDGE2 0 H0 R W 9 PAEDGE1 0 H0 R W 8 PAEDGE0 0 H0 R W 7 0 R 6 PAIE6 0 H0 R W 5 PAIE5 ...

Page 115: ...ction Assignment Port name PASELy 0 PASELy 1 48 pin 64 pin 80 pin 100 pin GPIO PAyMUX 0x0 Function 0 PAyMUX 0x1 Function 1 PAyMUX 0x2 Function 2 PAyMUX 0x3 Function 3 Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin Pa0 Pa0 Pa1 Pa1 Pa2 Pa2 Pa3 Pa3 CLG FOUT Pa4 Pa4 Pa5 Pa5 Pa6 Pa6 7 7 12 Pd Port Group The Pd port group support the GPIO function The Pd0 and Pd1 ports are configured as deb...

Page 116: ...3 PDREN3 0 H0 R W 2 PDREN2 0 H0 R W 1 PDREN1 0 H0 R W 0 PDREN0 0 H0 R W PPORTPDINTF PPORTPDINTCTL PPORTPDCHATEN 15 0 0x0000 R PDMODSEL Pd Port Mode Select Register 15 8 0x00 R 7 6 0x0 R 5 PDSEL5 0 H0 R W 4 PDSEL4 0 H0 R W 3 PDSEL3 0 H0 R W 2 PDSEL2 0 H0 R W 1 PDSEL1 1 H0 R W 0 PDSEL0 1 H0 R W PDFNCSEL Pd Port Function Select Register 15 12 0x0 H0 R W 11 10 PD5MUX 1 0 0x0 H0 R W 9 8 PD4MUX 1 0 0x0 ...

Page 117: ...ame Initial Reset R W Remarks 48 pin 64 pin 80 pin 100 pin PPORTCLK P Port Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R WP 7 4 CLKDIV 3 0 0x0 H0 R WP 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R WP PPORTINTFGRP P Port Interrupt Flag Group Register 15 11 0x0 R 10 PAINT 0 H0 R 9 P9INT 0 H0 R 8 P8INT 0 H0 R 7 P7INT 0 H0 R 6 P6INT 0 H0 R 5 P5INT 0 H0 R 4 P4INT 0 H0 R 3 P3INT 0 H0 R 2 P2INT 0 H0 R 1 P1INT 0 ...

Page 118: ...t data selector Peripheral circuit I O port Pxy Internal data bus Figure 8 1 1 UPMUX Configuration 8 2 Peripheral Circuit I O Function Assignment An I O function of a peripheral circuit supported may be assigned to peripheral I O function 1 of an I O port listed above The following shows the procedure to assign a peripheral I O function and enable it in the I O port 1 Configure the PPORTPxIOEN reg...

Page 119: ... Table 8 3 1 Bits 10 8 PxzPERISEL 2 0 Bits 2 0 PxyPERISEL 2 0 These bits specify a peripheral circuit See Table 8 3 1 Table 8 3 1 Peripheral I O Function Selections UPMUXPxMUXn PxyPPFNC 2 0 bits Peripheral I O function UPMUXPxMUXn PxyPERISEL 2 0 bits Peripheral circuit 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 None I2C SPIA UART3 T16B Reserved Reserved Reserved UPMUXPxMUXn PxyPERICH 1 0 bits Peripheral circ...

Page 120: ...upplied to WDT2 from the clock generator The CLK_WDT2 supply should be controlled as in the procedure shown below 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Enable the clock source in the clock generator if it is stopped refer to Clock Generator in the Power Supply Reset and Clocks chapter 3 Set the following WDT2CLK register bits WDT2CLK CLKSRC 1 0 bits Clock source s...

Page 121: ...st be reset periodically via software while WDT2 is running 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Write 1 to the WDT2CTL WDTCNTRST bit Reset WDT2 counter 3 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection A location should be provided for periodically processing this routine Process this routine within the tWDT cycle After resett...

Page 122: ...after clearing SLEEP mode reset WDT2 before executing the slp instruction WDT2 should also be stopped as required us ing the WDT2CTL WDTRUN 3 0 bits 9 4 Control Registers WDT2 Clock Control Register Register name Bit Bit name Initial Reset R W Remarks WDT2CLK 15 9 0x00 R 8 DBRUN 0 H0 R WP 7 6 0x0 R 5 4 CLKDIV 1 0 0x0 H0 R WP 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R WP Bits 15 9 Reserved Bit 8 DBRUN This ...

Page 123: ...TATNMI This bit indicates that a counter compare match and NMI have occurred 1 R NMI counter compare match occurred 0 R NMI not occurred When the NMI generation function of WDT2 is used read this bit in the NMI handler routine to con firm that WDT2 was the source of the NMI The WDT2CTL STATNMI bit set to 1 is cleared to 0 by writing 1 to the WDT2CTL WDTCNTRST bit Bits 7 5 Reserved Bit 4 WDTCNTRST ...

Page 124: ...L Seiko Epson Corporation 9 5 Rev 2 00 Bits 9 0 CMP 9 0 These bits set the NMI reset generation cycle The value set in this register is compared with the 10 bit counter value while WDT2 is running and an NMI or reset is generated when they are matched ...

Page 125: ...HZ 8 Hz RTC 8HZ 4 Hz RTC 4HZ 2 Hz RTC 2HZ 1 Hz RTC 1HZ Clock generator CPU core RTCTRMBSY RTCHLD RTC24H RTCADJ Stopwatch count control circuit Interrupt control circuit SWRST SWRUN SW1IE SW10IE SW100IE ALARMIE SW1IF SW10IF SW100IF ALARMIF RTCRST RTCRUN RTCWK 2 0 RTCYH 3 0 RTCYL 3 0 RTCMOH RTCMOL 3 0 RTCDH 1 0 RTCDL 3 0 RTCAP RTCHH 1 0 RTCHL 3 0 RTCMIH 2 0 RTCMIL 3 0 RTCSH 2 0 RTCSL 3 0 RTCAPA RTCH...

Page 126: ...oretical regulation can be specified within the range from 64 to 63 and it should be written to the RTCACTLH RTCTRM 6 0 bits as a two s complement number Use Eq 10 1 to calculate the cor rection value m RTCTRM 6 0 256 n However RTCTRM 6 0 is an integer after rounding off to 64 to 63 Eq 10 1 106 Where n Theoretical regulation execution cycle time second time interval to write the correct value to t...

Page 127: ...30 second correction using a time signal to adjust the time For more information on the 30 second correction refer to Real Time Clock Counter Operations 6 Write 1 to the real time clock counter interrupt flags in the RTCAINTF register to clear them 7 Write 1 to the interrupt enable bits in the RTCAINTE register to enable real time clock counter interrupts Time read 1 Check to see if the RTCACTLL R...

Page 128: ...or clears the second counter with the minute counter left unchanged if the second counter represents 0 to 29 seconds 1 second correction If a second count up timing occurred while the RTCACTLL RTCHLD bit 1 count hold state the real time clock counter counts up by 1 second performs 1 second correction after the counting has resumed by writ ing 0 to the RTCACTLL RTCHLD bit Note If two or more second...

Page 129: ...Writing 1 1 second RTCAINTF T1SECIF Second counter count up Writing 1 1 2 second RTCAINTF T1_2SECIF See Figure 10 5 1 Writing 1 1 4 second RTCAINTF T1_4SECIF See Figure 10 5 1 Writing 1 1 8 second RTCAINTF T1_8SECIF See Figure 10 5 1 Writing 1 1 32 second RTCAINTF T1_32SECIF See Figure 10 5 1 Writing 1 Stopwatch 1 Hz RTCAINTF SW1IF 1 10 second counter overﬂow Writing 1 Stopwatch 10 Hz RTCAINTF SW1...

Page 130: ...the count up operation of the real time clock counter 1 R W Halt real time clock counter count up operation 0 R W Normal operation Writing 1 to this bit halts the count up operation of the real time clock counter this makes it possible to read the counter value correctly without changing the counter Write 0 to this bit to resume count up operation immediately after the counter has been read Depend...

Page 131: ...d Writing 1 to this bit again resumes counting from the value retained RTCA Control Register High Byte Register name Bit Bit name Initial Reset R W Remarks RTCACTLH 7 RTCTRMBSY 0 H0 R 6 0 RTCTRM 6 0 0x00 H0 W Read as 0x00 Bit 7 RTCTRMBSY This bit indicates whether the theoretical regulation is currently executed or not 1 R Theoretical regulation is executing 0 R Theoretical regulation has finished...

Page 132: ... R W 7 0 R 6 4 RTCMIHA 2 0 0x0 H0 R W 3 0 RTCMILA 3 0 0x0 H0 R W Bit 15 Reserved Bit 14 RTCAPA This bit sets A M or P M of the alarm time in 12H mode RTCACTLL RTC24H bit 0 1 R W P M 0 R W A M This setting is ineffective in 24H mode RTCACTLL RTC24H bit 1 Bits 13 12 RTCHHA 1 0 Bits 11 8 RTCHLA 3 0 The RTCAALM2 RTCHHA 1 0 bits and the RTCAALM2 RTCHLA 3 0 bits set the 10 hour digit and 1 hour digit of...

Page 133: ...rt control 0 R W Idle stop control When the stopwatch counter stops counting by writing 0 to this bit the counter retains the value when it stopped Writing 1 to this bit again resumes counting from the value retained Note The stopwatch counter stops in sync with the stopwatch clock after 0 is written to the RT CASWCTL SWRUN bit Therefore the counter value may be incremented 1 from the value at wri...

Page 134: ...r Register name Bit Bit name Initial Reset R W Remarks RTCAHUR 15 0 R 14 RTCAP 0 H0 R W 13 12 RTCHH 1 0 0x1 H0 R W 11 8 RTCHL 3 0 0x2 H0 R W 7 0 R 6 4 RTCMIH 2 0 0x0 H0 R W 3 0 RTCMIL 3 0 0x0 H0 R W Bit 15 Reserved Bit 14 RTCAP This bit is used to set and read A M or P M data in 12H mode RTCACTLL RTC24H bit 0 1 R W P M 0 R W A M In 24H mode RTCACTLL RTC24H bit 1 this bit is fixed at 0 and writing ...

Page 135: ...ithin the range from 1 to 12 Notes Be sure to avoid writing to the RTCMON RTCMOH RTCMOL 3 0 bits while the RTCCTL RTCBSY bit 1 Be sure to avoid setting the RTCMON RTCMOH RTCMOL 3 0 bits to 0x00 Bits 7 6 Reserved Bits 5 4 RTCDH 1 0 Bits 3 0 RTCDL 3 0 The RTCAMON RTCDH 1 0 bits and the RTCAMON RTCDL 3 0 bits are used to set and read the 10 day digit and the 1 day digit of the day counter respectivel...

Page 136: ...TCBSY bit 1 RTCA Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks RTCAINTF 15 RTCTRMIF 0 H0 R W Cleared by writing 1 14 SW1IF 0 H0 R W 13 SW10IF 0 H0 R W 12 SW100IF 0 H0 R W 11 9 0x0 R 8 ALARMIF 0 H0 R W Cleared by writing 1 7 T1DAYIF 0 H0 R W 6 T1HURIF 0 H0 R W 5 T1MINIF 0 H0 R W 4 T1SECIF 0 H0 R W 3 T1_2SECIF 0 H0 R W 2 T1_4SECIF 0 H0 R W 1 T1_8SECIF 0 H0 R W 0 T1_32S...

Page 137: ...F T1_4SECIF bit 1 4 second interrupt RTCAINTF T1_8SECIF bit 1 8 second interrupt RTCAINTF T1_32SECIF bit 1 32 second interrupt RTCA Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks RTCAINTE 15 RTCTRMIE 0 H0 R W 14 SW1IE 0 H0 R W 13 SW10IE 0 H0 R W 12 SW100IE 0 H0 R W 11 9 0x0 R 8 ALARMIE 0 H0 R W 7 T1DAYIE 0 H0 R W 6 T1HURIE 0 H0 R W 5 T1MINIE 0 H0 R W 4 T1SECIE 0 H0 ...

Page 138: ...ts 1 R W Enable interrupts 0 R W Disable interrupts The following shows the correspondence between the bit and interrupt RTCAINTE ALARMIE bit Alarm interrupt RTCAINTE T1DAYIE bit 1 day interrupt RTCAINTE T1HURIE bit 1 hour interrupt RTCAINTE T1MINIE bit 1 minute interrupt RTCAINTE T1SECIE bit 1 second interrupt RTCAINTE T1_2SECIE bit 1 2 second interrupt RTCAINTE T1_4SECIE bit 1 4 second interrupt...

Page 139: ... Three detection cycles are selectable Low power supply voltage detection count function to generate an inter rupt reset when low power supply voltage is successively detected the number of times specified Continuous operation is also possible Figure 11 1 1 shows the configuration of SVD3 Table 11 1 1 SVD3 Configuration of S1C31D50 D51 Item 48 pin package 64 pin package 80 pin package 100 pin pack...

Page 140: ...3 operating clock CLK_SVD3 must be supplied to SVD3 from the clock generator The CLK_SVD3 supply should be controlled as in the procedure shown below 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Enable the clock source in the clock generator if it is stopped refer to Clock Generator in the Power Supply Reset and Clocks chapter 3 Set the following SVD3CLK register bits SV...

Page 141: ...e interrupt Write 1 to the SVD3INTF SVDIF bit Clear interrupt flag Set the SVD3INTE SVDIE bit to 1 Enable SVD3 interrupt 5 Set the SVD3CTL MODEN bit to 1 Enable SVD3 detection 6 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection Terminating detection Follow the procedure shown below to stop SVD3 operation 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system p...

Page 142: ...reset can be generated when SVD3 has successively detected low power supply voltage the number of times speci fied by the SVD3CTL SVDSC 1 0 bits 1 When the SVD3CTL SVDMD 1 0 bits 0x0 continuous operation mode VSVD VSVD VDD SVD3CTL MODEN SVD3 operating status SVD3INTF SVDDT Low power supply voltage detection interrupt DET 2 When the SVD3CTL SVDMD 1 0 bits 0x0 intermittent operation mode VSVD Level ...

Page 143: ... state is can celed After that SVD3 resumes operating in the operation mode set previously via the initialization routine During reset state the SVD3 control bits are set as shown in Table 11 5 2 1 Table 11 5 2 1 SVD3 Control Bits During Reset State Control register Control bit Setting SVD3CLK DBRUN Reset to the initial values CLKDIV 2 0 CLKSRC 1 0 SVD3CTL VDSEL The set value is retained SVDSC 1 0...

Page 144: ...13 SVDSC 1 0 These bits set the condition to generate an interrupt reset number of successive low voltage detec tions in intermittent operation mode SVD3CTL SVDMD 1 0 bits 0x1 to 0x3 Table 11 6 2 Interrupt Reset Generating Condition in Intermittent Operation Mode SVD3CTL SVDSC 1 0 bits Interrupt reset generating condition 0x3 Low power supply voltage is successively detected eight times 0x2 Low po...

Page 145: ...top detection operations After this bit has been altered wait until the value written is read out from this bit without subsequent operations being performed Notes Writing 0 to the SVD3CTL MODEN bit resets the SVD3 hardware However the register val ues set and the interrupt flag are not cleared The SVD3CTL MODEN bit is actually set to 0 after this processing has finished If 1 is written to the SVD...

Page 146: ... after 1 is written to the SVD3CTL MODEN bit SVD3 Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks SVD3INTE 15 8 0x00 R 7 1 0x00 R 0 SVDIE 0 H0 R W Bits 15 1 Reserved Bit 0 SVDIE This bit enables low power supply voltage detection interrupts 1 R W Enable interrupts 0 R W Disable interrupts Notes If the SVD3CTL SVDRE 3 0 bits are set to 0xa no low power supply voltage ...

Page 147: ...terface Ch 0 master clock Ch 2 Quad synchronous serial interface Ch 0 master clock Ch 5 Synchronous serial interface Ch 2 master clock Ch 6 Synchronous serial interface Ch 1 master clock Ch 7 12 bit A D converter trigger signal T16 Ch n To CPU core To peripheral circuit Underflow PRESET Timer control circuit Interrupt control circuit PRUN TRMD CLKSRC 1 0 CLKDIV 3 0 Clock generator UFIE UFIF DBRUN ...

Page 148: ...uring debugging should be controlled using the T16_nCLK DBRUN bit The CLK_T16_n supply to T16 Ch n is suspended when the CPU enters debug state if the T16_nCLK DBRUN bit 0 After the CPU returns to normal operation the CLK_T16_n supply resumes Although T16 Ch n stops operat ing when the CLK_T16_n supply is suspended the counter and registers retain the status before the debug state was entered If t...

Page 149: ...ng clock frequency Hz 12 4 3 Operations in Repeat Mode T16 Ch n enters repeat mode by setting the T16_nMOD TRMD bit to 0 In repeat mode the count operation starts by writing 1 to the T16_nCTL PRUN bit and continues until 0 is written A counter underflow presets the T16_nTR register value to the counter so underflow occurs periodically Select this mode to generate periodic underflow interrupts or w...

Page 150: ...g Set condition Clear condition Underﬂow T16_nINTF UFIF When the counter underﬂows Writing 1 T16 provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the CPU core only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more infor mation on interrupt control refer to the Interrupt chapter 12 6 Control Reg...

Page 151: ...ot be selected as the clock source Note 2 When the T16_nCLK CLKSRC 1 0 bits are set to 0x3 EXCLm is selected for the channel with an event counter function or EXOSC is selected for other channels T16 Ch n Mode Register Register name Bit Bit name Initial Reset R W Remarks T16_nMOD 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W Bits 15 1 Reserved Bit 0 TRMD This bit selects the T16 operation mode 1 R W One ...

Page 152: ...perating clock 0 R W Disable Stop supplying operating clock T16 Ch n Reload Data Register Register name Bit Bit name Initial Reset R W Remarks T16_nTR 15 0 TR 15 0 0xffff H0 R W Bits 15 0 TR 15 0 These bits are used to set the initial value to be preset to the counter The value set to this register will be preset to the counter when 1 is written to the T16_nCTL PRESET bit or when the counter under...

Page 153: ...it Bit name Initial Reset R W Remarks T16_nINTE 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W Bits 15 1 Reserved Bit 0 UFIE This bit enables T16 Ch n underflow interrupts 1 R W Enable interrupts 0 R W Disable interrupts Note To prevent generating unnecessary interrupts the corresponding interrupt flag should be cleared before enabling interrupts ...

Page 154: ...A transfer request when a receive buffer one byte full or a transmit buffer empty occurs Input pin can be pulled up with an internal resistor The output pin is configurable as an open drain output Provides the carrier modulation output function Figure 13 1 1 shows the UART3 configuration Table 13 1 1 UART3 Channel Configuration of S1C31D50 D51 Item 48 pin package 64 pin package 80 pin package 100 ...

Page 155: ...Pin Open Drain Output Function The USOUTn pin supports the open drain output function Default configuration is a push pull output and it is switched to an open drain output by setting the UART3_nMOD OUTMD bit to 1 13 2 5 Input Output Signal Inverting Function The UART3 can invert the signal polarities of the USINn pin input and the USOUTn pin output by setting the UART3_nMOD INVRX bit and the UART...

Page 156: ...ART3_nBR BRT 7 0 and UART3_nBR FMD 3 0 bit settings Use the follow ing equations to calculate the setting values for obtaining the desired transfer rate CLK_UART3 CLK_UART3 bps BRT BRDIV FMD 1 Eq 13 1 BRT 1 bps FMD BRDIV Where bps Transfer rate bit s CLK_UART3 UART3 operating clock frequency Hz BRDIV Baud rate division ratio 1 16 or 1 4 Selected by the UART3_nMOD BRDIV bit BRT UART3_nBR BRT 7 0 se...

Page 157: ...sable USOUTn pin open drain output UART3_nMOD IRMD bit Enable disable IrDA interface UART3_nMOD CHLN bit Set data length 7 or 8 bits UART3_nMOD PREN bit Enable disable parity function UART3_nMOD PRMD bit Select parity mode even or odd UART3_nMOD STPB bit Set stop bit length 1 or 2 bits UART3_nMOD CAREN bit Enable disable carrier modulation function UART3_nMOD PECAR bit Select carrier modulation pe...

Page 158: ...hift reg ister data bits are then output successively from the LSB Following output of MSB the parity bit if parity is enabled and the stop bit are output Even if transmit data is being output from the USOUTn pin the next transmit data can be written to the UART3_nTXD register after making sure the UART3_nINTF TBEIF bit is set to 1 If no transmit data remains in the UART3_nTXD register after the s...

Page 159: ...2 show a timing chart and flowcharts respectively Data receiving procedure read by one byte 1 Wait for a UART3 interrupt when using the interrupt 2 Check to see if the UART3_nINTF RB1FIF bit is set to 1 receive buffer one byte full 3 Read the received data from the UART3_nRXD register 4 Repeat Steps 1 to 3 or 2 and 3 until the end of data reception Data receiving procedure read by two bytes 1 Wait...

Page 160: ...e UART3_nRXD reg ister to the specified memory via DMA Ch x when the UART3_nINTF RB1FIF bit is set to 1 receive buffer one byte full This automates the procedure read by one byte described above The transfer source destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance For more information on DMA refer to the ...

Page 161: ...e receive shift register Demodulator input USINn Demodulator output shift register input T2 Figure 13 5 4 3 IrDA Receive Signal Waveform Notes Set the baud rate division ratio to 1 16 when using the IrDA interface function The low pulse width T2 of the IrDA signal input must be CLK_UART3_n 3 cycles or longer 13 5 5 Carrier Modulation The UART3 has a carrier modulation function Writing 1 to the UAR...

Page 162: ...d an error is transferred to the re ceive data buffer Note however that the set timing depends on the buffer status at that point When the receive data buffer is empty The interrupt flag will be set when the data that encountered an error is transferred to the re ceive data buffer When the receive data buffer has a one byte free space The interrupt flag will be set when the first data byte already...

Page 163: ... An interrupt request is sent to the CPU core only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt chapter 13 8 DMA Transfer Requests The UART3 has a function to generate DMA transfer requests from the causes shown in Table 13 8 1 Table 13 8 1 DMA Transfer Request Causes of UART3 Cause t...

Page 164: ...rved Bits 1 0 CLKSRC 1 0 These bits select the clock source of the UART3 Table 13 9 1 Clock Source and Division Ratio Settings UART3_nCLK CLKDIV 1 0 bits UART3_nCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSC OSC1 OSC3 EXOSC 0x3 1 8 1 1 1 8 1 1 0x2 1 4 1 4 0x1 1 2 1 2 0x0 1 1 1 1 Note The oscillation circuits external input that are not supported in this IC cannot be selected as the clock source Note The...

Page 165: ... function 0 R W Disable input inverting function Bit 8 INVTX This bit enables the USOUTn output inverting function 1 R W Enable output inverting function 0 R W Disable output inverting function Bit 7 Reserved Bit 6 PUEN This bit enables pull up of the USINn pin 1 R W Enable pull up 0 R W Disable pull up Bit 5 OUTMD This bit sets the USOUTn pin output mode 1 R W Open drain output 0 R W Push pull ou...

Page 166: ... when the UART3_ nMOD BRDIV bit 1 UART3 Ch n Control Register Register name Bit Bit name Initial Reset R W Remarks UART3_nCTL 15 8 0x00 R 7 2 0x00 R 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W Bits 15 2 Reserved Bit 1 SFTRST This bit issues software reset to the UART3 1 W Issue software reset 0 W Ineffective 1 R Software reset is executing 0 R Software reset has finished During normal operation Setting thi...

Page 167: ...ts The receive data buffer consists of a 2 byte FIFO and older received data is read first UART3 Ch n Status and Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks UART3_nINTF 15 10 0x00 R 9 RBSY 0 H0 S0 R 8 TBSY 0 H0 S0 R 7 0 R 6 TENDIF 0 H0 S0 R W Cleared by writing 1 5 FEIF 0 H0 S0 R W Cleared by writing 1 or reading the UART3_nRXD register 4 PEIF 0 H0 S0 R W 3 OEIF 0 ...

Page 168: ...ART3_nINTF TBEIF bit Transmit buffer empty interrupt UART3 Ch n Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks UART3_nINTE 15 8 0x00 R 7 0 R 6 TENDIE 0 H0 R W 5 FEIE 0 H0 R W 4 PEIE 0 H0 R W 3 OEIE 0 H0 R W 2 RB2FIE 0 H0 R W 1 RB1FIE 0 H0 R W 0 TBEIE 0 H0 R W Bits 15 7 Reserved Bit 6 TENDIE Bit 5 FEIE Bit 4 PEIE Bit 3 OEIE Bit 2 RB2FIE Bit 1 RB1FIE Bit 0 TBEIE These...

Page 169: ...h n Receive Buffer One Byte Full DMA Request Enable Register Register name Bit Bit name Initial Reset R W Remarks UART3_n RB1FDMAEN 15 0 RB1FDMAEN 15 0 0x0000 H0 R W Bits 15 0 RB1FDMAEN 15 0 These bits enable the UART3 to issue a DMA transfer request to the corresponding DMA controller channel Ch 0 Ch 15 when a receive buffer one byte full state has occurred 1 R W Enable DMA transfer request 0 R W...

Page 170: ...rated with the external input clock SPICLKn only Slave mode is capable of being operated in SLEEP mode allowing wake up by an SPIA interrupt Input pins can be pulled up down with an internal resistor Figure 14 1 1 shows the SPIA configuration Table 14 1 1 SPIA Channel Configuration of S1C31D50 D51 Item 48 pin package 64 pin package 80 pin package 100 pin package Number of channels 3 channels Ch 0 ...

Page 171: ...ons the SPIA input output function must be assigned to the port before activating SPIA For more information refer to the I O Ports chapter 14 2 2 External Connections SPIA operates in master mode or slave mode Figures 14 2 2 1 and 14 2 2 2 show connection diagrams between SPIA in each mode and external SPI devices Px1 Px2 Px3 SDIn SDOn SPICLKn SPISS SDO SDI SPICLK SPISS SDO SDI SPICLK SPISS SDO SD...

Page 172: ...LKn and SPISSn pins in slave mode have a pull up or pull down function as shown in Table 14 2 4 1 This function is enabled by setting the SPIA_nMOD PUEN bit to 1 Table 14 2 4 1 Pull Up or Pull Down of Input Pins Pin Master mode Slave mode SDIn Pull up Pull up SPICLKn SPIA_nMOD CPOL bit 1 Pull up SPIA_nMOD CPOL bit 0 Pull down SPISSn Pull up 14 3 Clock Settings 14 3 1 SPIA Operating Clock Operating...

Page 173: ... The CLK_T16_m supply to SPIA Ch n is suspended when the CPU enters debug state if the T16_mCLK DBRUN bit 0 After the CPU returns to normal operation the CLK_T16_m supply resumes Although SPIA Ch n stops operating when the CLK_T16_m supply is suspended the output pins and registers retain the status before the de bug state was entered If the T16_mCLK DBRUN bit 1 the CLK_T16_m supply is not suspend...

Page 174: ...lock by controlling the 16 bit timer and supply it to SPIA Ch n 2 Configure the following SPIA_nMOD register bits SPIA_nMOD PUEN bit Enable input pin pull up down SPIA_nMOD NOCLKDIV bit Select master mode operating clock SPIA_nMOD LSBFST bit Select MSB first LSB first SPIA_nMOD CPHA bit Select clock phase SPIA_nMOD CPOL bit Select clock polarity SPIA_nMOD MST bit Select master slave mode 3 Assign ...

Page 175: ...nsferred to the shift register and the SPIA_ nINTF TBEIF bit is set to 1 If the SPIA_nINTE TBEIE bit 1 transmit buffer empty interrupt enabled a transmit buffer empty interrupt occurs at the same time The SPICLKn pin outputs clocks of the number of the bits specified by the SPIA_nMOD CHLN 3 0 bits and the transmit data bits are output in sequence from the SDOn pin in sync with these clocks Even if...

Page 176: ...emory to the SPIA_ nTXD register via DMA Ch x when the SPIA_nINTF TBEIF bit is set to 1 transmit buffer empty This automates the procedure from Step 2 to Step 5 described above The transfer source destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance so that transmit data will be transferred to the SPIA_nTXD ...

Page 177: ...when transmit data may be dummy data if data transmission is not required is written to the SPIA_nTXD register The SPICLKn pin outputs clocks of the number of the bits specified by the SPIA_nMOD CHLN 3 0 bits The transmit data bits are output in sequence from the SDOn pin in sync with these clocks and the receive data bits input from the SDIn pin are shifted into the shift register When the last c...

Page 178: ...ls should be used to write dummy data to the SPIA_nTXD reg ister as a reception start trigger and to read the received data from the SPIA_nRXD register By setting the SPIA_nTBEDMAEN TBEDMAENx1 bit to 1 DMA transfer request enabled a DMA transfer request is sent to the DMA controller and dummy data is transferred from the specified memory to the SPIA_ nTXD register via DMA Ch x1 when the SPIA_nINTF...

Page 179: ... data Note Transmit data must be written to the SPIA_nTXD register after the SPIA_nINTF TBEIF bit is set to 1 by the time the sending SPIA_nTXD register data written is completed If no transmit data is written during this period the data bits input from the SDIn pin are shifted and output from the SDOn pin without being modified Data receiving procedure 1 Wait for a receive buffer full interrupt S...

Page 180: ...IF SPIA_nINTF RBFIF Software operations 1 2 3 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Data W SPIA_nTXD Data W SPIA_nTXD Data W SPIA_nTXD SPIA_nRXD Data R SPIA_nRXD Data R Figure 14 5 5 1 Example of Data Transfer Operations in Slave Mode SPIA_nMOD CHLN 3 0 bits 0x7 Data reception End Read receive data from the SPIA_nRXD register NO YES Receive data remained Wait for an interrupt request SPI...

Page 181: ...nINTF OEIF When the receive data buffer is full when the re ceived data has not been read at the point that receiving data to the shift register has completed Writing 1 SPIA provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the CPU core only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more info...

Page 182: ...t is sent to the pertinent channel of the DMA con troller only when the DMA transfer request flag of which DMA transfer has been enabled by the DMA transfer request enable bit is set The DMA transfer request flag also serves as an interrupt flag therefore both the DMA transfer request and the interrupt cannot be enabled at the same time After a DMA transfer has completed disable the DMA transfer t...

Page 183: ...r mode or slave mode 1 R W Master mode 0 R W Slave mode Note The SPIA_nMOD register settings can be altered only when the SPIA_nCTL MODEN bit 0 SPIA Ch n Control Register Register name Bit Bit name Initial Reset R W Remarks SPIA_nCTL 15 8 0x00 R 7 2 0x00 R 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W Bits 15 2 Reserved Bit 1 SFTRST This bit issues software reset to SPIA 1 W Issue software reset 0 W Ineffect...

Page 184: ...Remarks SPIA_nRXD 15 0 RXD 15 0 0x0000 H0 R Bits 15 0 RXD 15 0 The receive data buffer can be read through these bits Received data can be read when the SPIA_ nINTF RBFIF bit 1 regardless of whether data is being input from the SDIn pin or not Note that the upper bits that exceed the data bit length configured by the SPIA_nMOD CHLN 3 0 bits become 0 SPIA Ch n Interrupt Flag Register Register name ...

Page 185: ...ffer full interrupt SPIA_nINTE TBEIE bit Transmit buffer empty interrupt SPIA Ch n Transmit Buffer Empty DMA Request Enable Register Register name Bit Bit name Initial Reset R W Remarks SPIA_nTBEDMAEN 15 0 TBEDMAEN 15 0 0x0000 H0 R W Bits 15 0 TBEDMAEN 15 0 These bits enable the SPIA to issue a DMA transfer request to the corresponding DMA channel Ch 0 Ch 15 when a transmit buffer empty state has ...

Page 186: ... only Slave mode is capable of being operated in SLEEP mode allowing wake up by a QSPI interrupt Input pins can be pulled up down with an internal resistor Low CPU overhead memory mapped access mode that can access the external Flash memory with XIP eXecute In Place mode in the same manner as the embedded system memory Memory mapped access size 8 16 and 32 bit access 1M byte external Flash memory ...

Page 187: ...ist of QSPI Pins Pin name I O Initial status Function QSDIOn 3 0 I or O I Hi Z QSPI Ch n data input output pin QSPICLKn I or O I Hi Z QSPI Ch n external clock input output pin QSPISSn I or O I Hi Z QSPI Ch n slave select signal input output pin Indicates the status when the pin is configured for the QSPI If the port is shared with the QSPI pin and other functions the QSPI input output function mus...

Page 188: ...PICK SPISS SDO SDI SPICK SPISS SDO SDI SPICK External single I O SPI slave devices QSPISSn Px1 Px2 QSDIOn1 QSDIOn0 QSPICLKn S1C31 QSPI register access master mode Figure 15 2 2 2 Connections between QSPI in Register Access Master Mode and External Single I O SPI Legacy SPI Slave Devices SPISS SDIO1 SDIO0 SPICK SPISS SDIO1 SDIO0 SPICK SPISS SDIO1 SDIO0 SPICK External dual I O SPI slave devices QSPI...

Page 189: ...3 QSDIOn2 QSDIOn1 QSDIOn0 QSPICLKn S1C31 QSPI register access master mode Figure 15 2 2 4 Connections between QSPI in Register Access Master Mode and External QSPI Slave Devices QSPISSn QSDIOn1 QSDIOn0 QSPICLKn SPISS0 SPISS1 SPISS2 SDO SDI SPICK S1C31 QSPI slave mode SPISS SDI SDO SPICK SPISS SDI SDO SPICK External single I O SPI slave devices External single I O SPI master device Figure 15 2 2 5 ...

Page 190: ...xternal duale I O SPI master device Figure 15 2 2 6 Connections between QSPI in Slave Mode and External Dual I O SPI Master Device QSPISSn QSDIOn3 QSDIOn2 QSDIOn1 QSDIOn0 QSPICLKn QSPISS0 QSPISS1 QSPISS2 QSDIO3 QSDIO2 QSDIO1 QSDIO0 QSPICLK S1C31 QSPI slave mode QSPISS QSDIO3 QSDIO2 QSDIO1 QSDIO0 QSPICLK QSPISS QSDIO3 QSDIO2 QSDIO1 QSDIO0 QSPICLK External QSPI slave devices External QSPI master dev...

Page 191: ...is pin is used to output the slave select signal in mas ter mode In memory mapped access mode this pin is controlled by the internal state machine In register ac cess mode this pin is controlled by a register bit When connecting more than one external slave device general purpose I O ports can be used to output the extra slave select signals Applying a low level to the QSPISSn pin enables the QSPI...

Page 192: ... during SLEEP mode so the QSPI can receive data and can generate receive buffer full interrupts 15 3 2 Clock Supply During Debugging In master mode the operating clock supply during debugging should be controlled using the T16_mCLK DBRUN bit The CLK_T16_m supply to QSPI Ch n is suspended when the CPU enters debug state if the T16_mCLK DBRUN bit 0 After the CPU returns to normal operation the CLK_T...

Page 193: ...QSPI_nTXD register Loading Dr 7 0 to the QSPI_nRXD register Figure 15 4 1 Data Format Selection for Single Transfer Mode Using the QSPI_nMOD LSBFST Bit QSPI_nMOD TMOD 1 0 bits 0x0 QSPI_nMOD CHLN 3 0 bits 0x7 QSPI_nMOD CPOL bit 0 QSPI_nMOD CPHA bit 0 Cycle No QSPICLKn QSDIOn1 QSDIOn0 QSDIOn1 QSDIOn0 QSDIOn1 QSDIOn0 QSDIOn1 QSDIOn0 1 QSPI_nMOD LSBFST bit 0 1 2 3 4 5 6 7 8 Dw15 Dw1 Dr1 Dw13 Dw3 Dr3 D...

Page 194: ...ransmit data are always output from the QSDIOn0 pin and receive data are always input to the QSDIOn1 pin the QSDIOn 3 2 pins are not used The operations are backward compatible with legacy SPI e g synchronous serial interface of this MCU In dual transfer mode transmit data are output from the QSDIOn 1 0 pins when the transfer direction is set to out put QSPI_nCTL DIR bit 0 Receive data are input f...

Page 195: ...us to the pre vious read address assert the slave signal again after negating it once After that just send an address cycle to spec ify the new read start address and a dummy cycle including an XIP activation continuation confirmation bit s as the command cycle is not needed in this XIP session The Flash memory performs read operations the same as the read command previously executed to execute a ...

Page 196: ...ode the QSPI automatically executes a new address and dummy cycles When mem ory mapped access mode is disabled by setting a register the QSPI executes an address cycle and a dummy cycle including a mode byte that specifies to terminate XIP mode Memory mapped access mode supports 8 16 and 32 bit read accesses The 32 bit access is mainly used to read data in a large memory block sequentially In this...

Page 197: ...he QSPI_nCTL DIR bit to 0 when QSPI Ch n is set to dual or quad transfer mode This setting is not necessary in single transfer mode 2 Assert the slave select signal for the external slave device to be accessed by controlling the QSPI_nCTL MSTSSO bit or the general purpose output port used for an extra slave select signal output if necessary 3 Check to see if the QSPI_nINTF TBEIF bit is set to 1 tr...

Page 198: ...ansmit data to the QSPI_nTXD register YES NO Not necessary in single transfer mode NO YES Transmit data remained QSPI_nINTF TBEIF 1 Wait for an interrupt request QSPI_nINTF TBEIF 1 Figure 15 5 4 2 Data Transmission Flowchart in Master Mode Data transmission using DMA By setting the QSPI_nTBEDMAEN TBEDMAENx bit to 1 DMA transfer request enabled a DMA transfer request is sent to the DMA controller a...

Page 199: ...he general purpose output port if necessary Note To perform continuous data reception without stopping QSPICLKn Steps 8 and 6 operations must be completed within the QSPICLKn cycles equivalent to Data bit length 1 after Step 7 Data receiving operations In single transfer mode QSPI_nMOD TMOD 1 0 bits 0 QSPI Ch n operates similar to legacy SPI devices The data receiving operation starts simultaneous...

Page 200: ...r an interrupt request QSPI_nINTF RBFIF 1 Execute this sequence within the QSPICLKn cycles equivalent to Data bit length 1 from an interrupt request Assert the slave select signal output from the QSPISSn pin QSPI_nCTL MSTSSO 0 or a general purpose port Assert the slave select signal output from the QSPISSn pin QSPI_nCTL MSTSSO 0 or a general purpose port Negate the slave select signal output from ...

Page 201: ... basic transfer The following shows an example of the control procedure including the DMA controller operations 1 Configure the primary data structure for the DMA channel Ch x used for writing dummy bytes to the QSPI_nTXD register as shown in Table 15 5 5 1 2 Configure the primary data structure for the DMA channel Ch y used for reading data from the QSPI_ nRXD register as shown in Table 15 5 5 2 ...

Page 202: ...again after setting the QSPI_nM MACFG2 MMAEN bit to 0 once Data receiving operations 32 bit read In memory mapped access mode the internal state machine detects the address in the memory mapped access area from which data is read If it is the first read operation after the QSPI has entered memory mapped access mode the state machine generates an address cycle and a dummy cycle including the XIP ac...

Page 203: ...cycle dummy cycle and data cycle are executed The beginning and the end of each address dummy or data cycle take a couple of HCLK clocks for handshak ing n 2 2 0 HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA fifo_read_level QSPICLKn QSDIOn 3 0 Address cycle high order 8 16 bits Address cycle low order 16 bits Dummy cycle QSPI_nMOD register CPHA bit 1 0 CPOL bit 1 0 0 1 0 1 n HCLK HSEL HADDR HTRANS HS...

Page 204: ... Rev 2 00 n n 4 n 8 n n 4 n 8 1 1 2 0 0 2 2 HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA fifo_read_level QSPICLKn QSDIOn 3 0 Data cycle for n 8 QSPI_nMOD register CPHA bit 1 0 CPOL bit 1 0 Data cycle prefetching Figure 15 5 6 2 Data Receiving Operation in Memory Mapped Access Mode 32 bit Sequential Read ...

Page 205: ...TCSH QSPI_nMOD register CPHA bit 1 0 CPOL bit 1 0 0 1 0 n HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA fifo_read_level QSPISSn QSPICLKn QSDIOn 3 0 Address cycle low order 16 bits Data cycle for n Data cycle for n 8 QSPI_nMOD register CPHA bit 1 0 CPOL bit 1 0 Dummy cycle Address cycle high order 8 16 bits Address cycle low order 16 bits Figure 15 5 6 3 Data Receiving Operation in Memory Mapped Acces...

Page 206: ... not prefetched into the FIFO n 2 0 1 HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA QSPICLKn QSDIOn 3 0 Address cycle high order 8 16 bits Address cycle low order 16 bits Dummy cycle QSPI_nMOD register CPHA bit 1 0 CPOL bit 1 0 n HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA QSPICLKn QSDIOn 3 0 Dummy cycle QSPI_nMOD register CPHA bit 1 0 CPOL bit 1 0 Data cycle Figure 15 5 6 4 Data Receiving Operation i...

Page 207: ...ation S1C31D50 D51 TECHNICAL MANUAL Rev 2 00 n n 2 0 1 HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA QSPICLKn QSDIOn 3 0 Data cycle QSPI_nMOD register CPHA bit 1 0 CPOL bit 1 0 Figure 15 5 6 5 Data Receiving Operation in Memory Mapped Access Mode 8 16 bit Sequential Read ...

Page 208: ...active period TCSH QSPI_nMOD register CPHA bit 1 0 CPOL bit 1 0 n HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA QSPISSn QSPICLKn QSDIOn 3 0 Address cycle low order 16 bits Data cycle QSPI_nMOD register CPHA bit 1 0 CPOL bit 1 0 Dummy cycle Address cycle high order 8 16 bits Address cycle low order 16 bits Figure 15 5 6 6 Data Receiving Operation in Memory Mapped Access Mode 8 16 bit Non Sequential Re...

Page 209: ... from the external Flash memory to the internal memory is al lowed only for the 32 bit sequential read using the internal FIFO A non sequential read and 8 16 bit reads can not issue a DMA transfer request as they cannot use the FIFO By setting the QSPI_nFRLDMAEN FRLDMAENx bit to 1 DMA transfer request enabled a DMA transfer request is sent to the DMA controller and the external Flash memory data i...

Page 210: ...re 7 Enable pending DMA interrupts in the CPU core 8 Enable the QSPI to issue DMA transfer requests to the DMA channel using the QSPI_nFRLDMAEN FRLDMAENx bit 9 Issue a software DMA transfer request to the DMA channel by setting the DMA controller register This operation is required to kickstart the first data fetching 10 Wait for a DMA interrupt 11 Disable DMA requests to be sent to the DMA channe...

Page 211: ...s a slave device only when the slave select signal input from the external QSPI master to the QSPISSn pin is set to the active low level If QSPISSn high the software transfer control the QSPICLKn pin input and the QSDIOn pins input are all ineffective If the QSPISSn signal goes high dur ing data transfer the transfer bit counter is cleared and data in the shift register is discarded Slave mode sta...

Page 212: ...e QSPI_nINTF TBEIF bit 1 after data of the specified bit length defined by the QSPI_ nMOD CHLN 3 0 bits has been sent Writing 1 Receive buffer full QSPI_nINTF RBFIF When data of the specified bit length is received and the received data is transferred from the shift register to the received data buffer Reading of the QSPI_nRXD register Transmit buffer empty QSPI_nINTF TBEIF When transmit data writ...

Page 213: ...d QSPI_nINTF TENDIF Bit Set Timings when QSPI_nMOD CHDL 3 0 bits QSPI_nMOD CHLN 3 0 bits 0x3 15 7 DMA Transfer Requests The QSPI has a function to generate DMA transfer requests from the causes shown in Table 15 7 1 Table 15 7 1 DMA Transfer Request Causes of QSPI Cause to request DMA transfer DMA transfer request flag Set condition Clear condition Receive buffer full Receive buffer full flag QSPI...

Page 214: ...Mode Register Register name Bit Bit name Initial Reset R W Remarks QSPI_nMOD 15 12 CHDL 3 0 0x7 H0 R W 11 8 CHLN 3 0 0x7 H0 R W 7 6 TMOD 1 0 0x0 H0 R W 5 PUEN 0 H0 R W 4 NOCLKDIV 0 H0 R W 3 LSBFST 0 H0 R W 2 CPHA 0 H0 R W 1 CPOL 0 H0 R W 0 MST 0 H0 R W Bits 15 12 CHDL 3 0 These bits set the number of clocks to drive the serial output data lines This setting is required to out put the XIP confirmat...

Page 215: ...s according to the QSPI_nMOD DIR bit setting The QSDIOn 3 2 pins are not used 0x0 Single transfer mode The QSDIOn0 and QSDIOn1 pins are configured as an output pin and an input pin respectively The QSDIOn 3 2 pins are not used Bit 5 PUEN This bit enables pull up down of the pins that are configured as an input or are not used 1 R W Enable pull up down 0 R W Disable pull up down For more informatio...

Page 216: ... W QSPISSn low The device is selected In memory mapped access mode the QSPISSn pin is automatically controlled by the internal state machine Reading this bit allows monitoring of the current QSPISSn pin output status at any time Bit 1 SFTRST This bit issues software reset to QSPI 1 W Issue software reset 0 W Ineffective 1 R Software reset is executing 0 R Software reset has finished During normal ...

Page 217: ...egister Register name Bit Bit name Initial Reset R W Remarks QSPI_nRXD 15 0 RXD 15 0 0x0000 H0 R Bits 15 0 RXD 15 0 The receive data buffer can be read through these bits Received data can be read when the QSPI_ nINTF RBFIF bit 1 regardless of whether data is being input from the QSDIOn pin or not Note that the upper bits that exceed the data bit length configured by the QSPI_nMOD CHLN 3 0 bits be...

Page 218: ...0 H0 R W 0 TBEIE 0 H0 R W Bits 15 4 Reserved Bit 3 OEIE Bit 2 TENDIE Bit 1 RBFIE Bit 0 TBEIE These bits enable QSPI interrupts 1 R W Enable interrupts 0 R W Disable interrupts The following shows the correspondence between the bit and interrupt QSPI_nINTE OEIE bit Overrun error interrupt QSPI_nINTE TENDIE bit End of transmission interrupt QSPI_nINTE RBFIE bit Receive buffer full interrupt QSPI_nIN...

Page 219: ...dy 1 R W Enable DMA transfer request 0 R W Disable DMA transfer request Each bit corresponds to a DMA controller channel The high order bits for the unimplemented chan nels are ineffective QSPI Ch n Memory Mapped Access Configuration Register 1 Register name Bit Bit name Initial Reset R W Remarks QSPI_nMMACFG1 15 8 0x00 R 7 4 0x0 R 3 0 TCSH 3 0 0x0 H0 R W Bits 15 4 Reserved Bits 3 0 TCSH 3 0 When ...

Page 220: ...ure the QSPI_nMMACFG2 MMAEN 0 when altering the QSPI_nRMADRH RMADR 31 20 bits C31 system memory Memory mapped access area Offset N N QSPI_nRMADRH RMADR 31 20 setting value 0x000fffff 0x00000000 0x N fffff 0x N 00000 External flash memory RMADR N RMADR 0 Figure 15 8 1 External Flash Memory Remapping Bits 3 0 Reserved QSPI Ch n Memory Mapped Access Configuration Register 2 Register name Bit Bit name...

Page 221: ...ped access mode Table 15 8 6 Dummy Cycle Length Settings QSPI_nMMACFG2 DUMLN 3 0 bits Dummy cycle length 0xf 16 clocks 0xe 15 clocks 0xd 14 clocks 0xc 13 clocks 0xb 12 clocks 0xa 11 clocks 0x9 10 clocks 0x8 9 clocks 0x7 8 clocks 0x6 7 clocks 0x5 6 clocks 0x4 5 clocks 0x3 4 clocks 0x2 3 clocks 0x1 2 clocks 0x0 Setting prohibited Bits 7 6 DATTMOD 1 0 These bits select the transfer mode for the data ...

Page 222: ... four byte address according to the QSPI_ nMMACFG2 ADRCYC bit setting with all address bits set to 1 The dummy cycle is output accord ing to the QSPI_nMMACFG2 DUMLN 3 0 and QSPI_nMMACFG2 DUMDL 3 0 bit settings with a mode byte for terminating the XIP session of the external Flash memory that has been configured using the QSPI_nMB XIPEXT 7 0 bits Note Slave mode does not support memory mapped acces...

Page 223: ...fer full transmit buffer empty and other interrupts Can issue a DMA transfer request when a receive buffer full or a transmit buffer empty occurs Figure 16 1 1 shows the I2C configuration Table 16 1 1 I2C Channel Configuration of S1C31D50 D51 Item 48 pin package 64 pin package 80 pin package 100 pin package Number of channels 3 channels Ch 0 to Ch 2 I2C Ch n Interrupt control circuit BYTEENDIE GCI...

Page 224: ...L lines must be pulled up with an external resistor When the I2C is set into master mode one or more slave devices that have a unique address may be connected to the I2C bus When the I2C is set into slave mode one or more master and slave devices that have a unique address may be connected to the I2C bus SCLn VDD SDAn S1C31 Serial data SDA Serial clock SCL I2C bus External I2C device External I2C ...

Page 225: ... mode the CLK_I2Cn supply during debugging should be controlled using the I2C_nCLK DBRUN bit The CLK_I2Cn supply to the I2C Ch n is suspended when the CPU enters debug state if the I2C_nCLK DBRUN bit 0 After the CPU returns to normal operation the CLK_I2Cn supply resumes Although the I2C Ch n stops operating when the CLK_I2Cn supply is suspended the output pin and registers retain the status befor...

Page 226: ... 1 Configure the operating clock and the baud rate generator using the I2C_nCLK and I2C_nBR registers 2 Assign the I2C Ch n input output function to the ports Refer to the I O Ports chapter 3 Set the following bits when using the interrupt Write 1 to the interrupt flags in the I2C_nINTF register Clear interrupt flags Set the interrupt enable bits in the I2C_nINTE register to 1 Enable interrupts 4 ...

Page 227: ...TART condition The I2C Ch n starts generating a START condition when the I2C_nCTL TXSTART bit is set to 1 When the generating operation has completed the I2C Ch n clears the I2C_nCTL TXSTART bit to 0 and sets both the I2C_nINTF STARTIF and I2C_nINTF TBEIF bits to 1 Sending slave address and data If the I2C_nINTF TBEIF bit 1 a slave address or data can be written to the I2C_nTXD register The I2C Ch...

Page 228: ...the external slave Standby state SCL low TXSTART 1 TXSTOP 1 TXSTOP 0 STOPIF 1 P A TXSTART 1 Sr A S TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 1 TXSTOP 1 TXSTOP 0 STOPIF 1 P A TXSTART 1 Sr A TBEIF 1 TBEIF 1 NACKIF 1 NACKIF 1 NACKIF 1 Figure 16 4 2 1 Example of Data Sending Operations in Master Mode Data transmission End Write slave address and WRITE 0 to the I2C_nTXD register W...

Page 229: ...RT condition by setting the I2C_nCTL TXSTART bit to 1 2 Wait for a transmit buffer empty interrupt I2C_nINTF TBEIF bit 1 or a START condition interrupt I2C_ nINTF STARTIF bit 1 Clear the I2C_nINTF STARTIF bit by writing 1 after the interrupt has occurred 3 Write the 7 bit slave address to the I2C_nTXD TXD 7 1 bits and 1 that represents READ as the data trans fer direction to the I2C_nTXD TXD0 bit ...

Page 230: ...CL to low and enters standby state until data is read out from the I2C_ nRXD register This reading triggers the I2C Ch n to start subsequent data reception Generating a STOP or repeated START condition It is the same as the data transmission in master mode S S P A TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 0 STARTIF 1 TBEIF 1 NACKIF 1 TXSTART 1 TXSTOP 1 RXD 7 0 Data N TXSTART ...

Page 231: ... I2C_nRBFDMAEN RBFDMAENx bit to 1 DMA transfer request enabled a DMA transfer request is sent to the DMA controller and the received data is transferred from the I2C_nRXD register to the specified memory via DMA Ch x when the I2C_nINTF RBFIF bit is set to 1 receive buffer full This automates the data receiving procedure Steps 5 7 and 9 described above The transfer source destination and control da...

Page 232: ... by setting the I2C_nCTL TXSTART bit to 1 2 Wait for a transmit buffer empty interrupt I2C_nINTF TBEIF bit 1 or a START condition interrupt I2C_ nINTF STARTIF bit 1 Clear the I2C_nINTF STARTIF bit by writing 1 after the interrupt has occurred 3 Write the first address to the I2C_nTXD TXD 7 1 bits and 0 that represents WRITE as the data transfer di rection to the I2C_nTXD TXD0 bit 4 Wait for a tran...

Page 233: ...ng procedure in slave mode and the I2C Ch n operations are shown below Figures 16 4 5 1 and 16 4 5 2 show an operation example and a flowchart respectively Data sending procedure 1 Wait for a START condition interrupt I2C_nINTF STARTIF bit 1 Clear the I2C_nINTF STARTIF bit by writing 1 after the interrupt has occurred 2 Check to see if the I2C_nINTF TR bit 1 transmission mode Start a data receivin...

Page 234: ...n during data transmission If the I2C_nINTF TBEIF bit is still set to 1 when the data transmission from the shift register has completed the I2C Ch n pulls down SCL to low sets the I2C bus into clock stretching state until transmit data is written to the I2C_nTXD register If the next transmit data already exists in the I2C_nTXD register or data has been written after the above the I2C Ch n sends t...

Page 235: ...INTF STOPIF bit 1 or a START condition interrupt I2C_ nINTF STARTIF bit 1 i Go to Step 10 when a STOP condition interrupt has occurred ii Go to Step 3 when a START condition interrupt has occurred 10 Clear the I2C_nINTF STOPIF bit and then terminate data receiving operations Data receiving operations START condition detection and slave address check It is the same as the data transmission in slave...

Page 236: ...data transmission in slave mode S P Sr A STARTIF 1 BSY 0 STOPIF 1 Saddr W A Data 1 A Data 2 A Data N A RXD 7 0 Data 1 RXD 7 0 Data N 1 RXD 7 0 Data N RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 P Sr A Data N TXNACK 1 RXD 7 0 Data N 1 RXD 7 0 Data N RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 I2C bus Clock stretching by I2C Software bit operations Operations by the external master S STA...

Page 237: ...ng mode A 1stAddr W A 2ndAddr A 1stAddr W A 2ndAddr At start of data transmission At start of data reception S STARTIF 1 STARTIF 1 A Data 1 A Data 2 I2C bus Clock stretching by I2C I2C bus Clock stretching by I2C Software bit operations Operations by the external master S START condition Sr Repeated START condition P STOP condition A ACK A NACK 1stAddr W 1st address W 0 1stAddr R 1st address R 1 2...

Page 238: ...d The table below lists the hardware error detection conditions and the notification method Table 16 4 9 1 Hardware Error Detection Function No Error detecting period timing I2C bus line monitored and error condition Notification method 1 While the I2C Ch n controls SDA to high for sending address data or a NACK SDA low I2C_nINTF ERRIF 1 2 Master mode only When 1 is written to the I2C_nCTL TX STAR...

Page 239: ...START condition is issued Slave mode When an address match is detected including general call Writing 1 software reset Error detection I2C_nINTF ERRIF Refer to Error Detection Writing 1 software reset Receive buﬀer full I2C_nINTF RBFIF When received data is loaded to the receive data buﬀer Reading received data to empty the receive data buﬀer software reset Transmit buﬀer empty I2C_nINTF TBEIF Mas...

Page 240: ... when an ACK is received from the slave Slave mode When transmit data written to the transmit data buﬀer is transferred to the shift register or when an address match is detected with R W bit set to 1 Writing transmit data The I2C provides DMA transfer request enable bits corresponding to each DMA transfer request flag shown above for the number of DMA channels A DMA transfer request is sent to th...

Page 241: ...on circuits external input that are not supported in this IC cannot be selected as the clock source Note The I2C_nCLK register settings can be altered only when the I2C_nCTL MODEN bit 0 I2C Ch n Mode Register Register name Bit Bit name Initial Reset R W Remarks I2C_nMOD 15 8 0x00 R 7 3 0x00 R 2 OADR10 0 H0 R W 1 GCEN 0 H0 R W 0 0 R Bits 15 3 Reserved Bit 2 OADR10 This bit sets the number of own ad...

Page 242: ...nly when the I2C_nCTL MODEN bit 0 I2C Ch n Control Register Register name Bit Bit name Initial Reset R W Remarks I2C_nCTL 15 8 0x00 R 7 6 0x0 R 5 MST 0 H0 R W 4 TXNACK 0 H0 S0 R W 3 TXSTOP 0 H0 S0 R W 2 TXSTART 0 H0 S0 R W 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W Bits 15 6 Reserved Bit 5 MST This bit selects the I2C Ch n operating mode 1 R W Master mode 0 R W Slave mode Bit 4 TXNACK This bit issues a re...

Page 243: ... I2C operations The operating clock is supplied 0 R W Disable I2C operations The operating clock is stopped Note If the I2C_nCTL MODEN bit is altered from 1 to 0 while sending receiving data the data being sent received cannot be guaranteed When setting the I2C_nCTL MODEN bit to 1 again after that be sure to write 1 to the I2C_nCTL SFTRST bit as well I2C Ch n Transmit Data Register Register name B...

Page 244: ...egister Bits 15 13 Reserved Bit 12 SDALOW This bit indicates that SDA is set to low level 1 R SDA Low level 0 R SDA High level Bit 11 SCLLOW This bit indicates that SCL is set to low level 1 R SCL Low level 0 R SCL High level Bit 10 BSY This bit indicates that the I2C bus is placed into busy status 1 R I2C bus busy 0 R I2C bus free Bit 9 TR This bit indicates whether the I2C is set in transmission...

Page 245: ... I2C_nINTE 15 8 0x00 R 7 BYTEENDIE 0 H0 R W 6 GCIE 0 H0 R W 5 NACKIE 0 H0 R W 4 STOPIE 0 H0 R W 3 STARTIE 0 H0 R W 2 ERRIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W Bits 15 8 Reserved Bit 7 BYTEENDIE Bit 6 GCIE Bit 5 NACKIE Bit 4 STOPIE Bit 3 STARTIE Bit 2 ERRIE Bit 1 RBFIE Bit 0 TBEIE These bits enable I2C interrupts 1 R W Enable interrupts 0 R W Disable interrupts The following shows the corres...

Page 246: ...sable DMA transfer request Each bit corresponds to a DMA controller channel The high order bits for the unimplemented chan nels are ineffective I2C Ch n Receive Buffer Full DMA Request Enable Register Register name Bit Bit name Initial Reset R W Remarks I2C_nRBFDMAEN 15 0 RBFDMAEN 15 0 0x0000 H0 R W Bits 15 0 RBFDMAEN 15 0 These bits enable the I2C to issue a DMA transfer request to the correspond...

Page 247: ...e interrupt or DMA request signals and a PWM waveform Can be used as an interval timer PWM waveform generator and external event counter The capture circuit captures counter values using external software trigger signals and generates interrupts or DMA requests Can be used to measure external event periods cycles Figure 17 1 1 shows the T16B configuration Table 17 1 1 T16B Channel Configuration of...

Page 248: ... 1 TOUT00 TOUT control circuit 0 TOUTMT TOUTO TOUTMD 2 0 TOUTINV TOUTMT TOUTO TOUTMD 2 0 TOUTINV CAPI1 UP_DOWN BSY MATCH signal MATCH signal ZERO MAX signal CAP02 03 TOUT02 03 CAP04 05 TOUT04 05 CAPn0 1 TOUTn0 1 CAPn2 3 TOUTn2 3 CAPn4 5 TOUTn4 5 To CPU core To DMA controller MZDMAENx CCmDMAENx Interrupt control circuit DMA request control circuit CAPOWmIE CMPCAPmIE CNTMAXIE CNTZEROIE CAPOWmIF CMPC...

Page 249: ...se before enter ing SLEEP mode After the CPU returns to normal mode CLK_T16Bn is supplied and the T16B operation re sumes 17 3 3 Clock Supply During Debugging The CLK_T16Bn supply during debugging should be controlled using the T16B_nCLK DBRUN bit The CLK_T16Bn supply to T16B Ch n is suspended when the CPU enters debug state if the T16B_nCLK DBRUN bit 0 After the CPU returns to normal operation th...

Page 250: ...lowing bits when using the interrupt Write 1 to the interrupt flags in the T16B_nINTF register Clear interrupt flags Set the interrupt enable bits in the T16B_nINTE register to 1 Enable interrupts 7 Configure the DMA controller and set the following T16B control bits when using DMA transfer Write 1 to the DMA transfer request enable bits in the T16B_nMZDMAEN and T16B_nCCmDMAEN registers Enable DMA...

Page 251: ...intervals and checking a specific lapse of time Up down and up down mode configures the counter as an up counter down counter and up down counter re spectively MAX counter data register The MAX counter data register T16B_nMC MC 15 0 bits is used to set the maximum value of the counter hereafter referred to as MAX value This setting limits the count range to 0x0000 MAX value and determines the coun...

Page 252: ...ed to 0x0000 and continues counting up to the new MAX value In one shot up count mode the counter returns to 0x0000 if it exceeds the MAX value and stops automatically at that point Counter 0xffff 0x0000 1 Repeat up count mode Count cycle Time MAX value MAX value Software operation Hardware operation RUN 1 RUN 1 RUN 1 RUN 1 MODEN 1 PRESET 1 PRESET 1 RUN 0 Counter 0xffff 0x0000 2 One shot up count ...

Page 253: ... down counter and counts as 0x0000 or current value the MAX value 0x0000 In repeat up down count mode the counter repeats counting up from 0x0000 to the MAX value and counting down from the MAX value to 0x0000 until the T16B_nCTL RUN bit is set to 0 If the MAX value is altered to a value larger than the current counter value during count up operation the counter keeps counting up to the new MAX va...

Page 254: ...ems four or six systems of comparator capture circuits and each system can be set to comparator mode or capture mode individually Set the T16B_nCCCTLm CCMD bit to 0 to set the comparator capture circuit m to comparator mode or 1 to set it to capture mode Operations in comparator mode The comparator mode compares the counter value and the value set via software It generates an interrupt and toggles...

Page 255: ...T16B_nMC register RUN 1 CMPCAPmIF 1 CNTMAXIF 1 CMPCAPmIF 1 CNTZEROIF 1 CMPCAPmIF 1 CNTMAXIF 1 PRESET 1 3 Repeat up down count mode Compare period during counting down Compare period during counting up Note that the T16B_nINTF CMPCAPmIF CNTMAXIF CNTZEROIF bit clearing operations via software are omitted from the figure Figure 17 4 3 1 Operation Examples in Comparator Mode The time from counter 0x00...

Page 256: ...he timing to load the comparison value to the compare buffer can be configured using the T16B_nCCCTLm CBUFMD 2 0 bits for synchronization with the count operation Counter 0xffff 0x0000 1 1 T16B_nCCCTLm CBUFMD 2 0 bits 0x0 1 Repeat up count mode Time RUN 1 Data W MC 15 0 Data W CC 15 0 Data W CC 15 0 Data W CC 15 0 MODEN 1 Count cycle Compare buffer value MAX value T16B_nMC register CMPCAPmIF 1 CMP...

Page 257: ...egister 0xffff 0x0000 1 4 T16B_nCCCTLm CBUFMD 2 0 bits 0x3 Count cycle RUN 1 Data W CC 15 0 Data W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTMAXIF 1 CNTMAXIF 1 CNTMAXIF 1 Data W MC 15 0 Data W CC 15 0 PRESET 1 Compare period Counter Time Compare buffer value MAX value T16B_nMC register 0xffff 0x0000 1 5 T16B_nCCCTLm CBUFMD 2 0 bits 0x4 Count cycle RUN 1 Compare period Data...

Page 258: ...n Hardware operation 2 2 T16B_nCCCTLm CBUFMD 2 0 bits 0x1 0xffff 0x0000 RUN 1 Data W CC 15 0 Data W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTZEROIF 1 CNTZEROIF 1 CNTZEROIF 1 Data W MC 15 0 Data W CC 15 0 PRESET 1 Counter Time Compare buffer value MAX value T16B_nMC register Count cycle Compare period 2 3 T16B_nCCCTLm CBUFMD 2 0 bits 0x2 0xffff 0x0000 RUN 1 Data W CC 15 0 ...

Page 259: ... W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTZEROIF 1 CNTZEROIF 1 Data W MC 15 0 Data W CC 15 0 PRESET 1 Counter Time Compare buffer value MAX value T16B_nMC register Count cycle Compare period CMPCAPmIF 1 CMPCAPmIF 1 0xffff 0x0000 RUN 1 Data W MC 15 0 Data W CC 15 0 PRESET 1 Data W CC 15 0 Data W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTMAXIF 1 C...

Page 260: ...mpare period during counting down Compare period during counting up 3 4 T16B_nCCCTLm CBUFMD 2 0 bits 0x3 CNTZEROIF 1 0xffff 0x0000 RUN 1 Data W MC 15 0 Data W CC 15 0 Data W CC 15 0 Data W CC 15 0 MODEN 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CMPCAPmIF 1 CNTMAXIF 1 CNTZEROIF 1 CNTMAXIF 1 Counter Time Count cycle Compare buffer value MAX value T16B_nMC register Compare period during counting down Com...

Page 261: ...e Configuration Example T16B Compare Period and Count Cycle Settings Item Setting example End pointer Transfer source Memory address in which the last setting data is stored Transfer destination T16B_nCCRm or T16B_nMC register address Control data dst_inc 0x3 no increment dst_size 0x1 haflword src_inc 0x1 2 src_size 0x1 halfword R_power 0x0 arbitrated for every transfer n_minus_1 Number of transfe...

Page 262: ...invalid data reading by capturing counter data simultaneously with the counter being counted up down Set the T16B_nCCCTLm SCS bit to 1 to set the capture circuit to synchronous capture mode This mode captures counter data by synchronizing the capture signal with the counter clock On the other hand asynchronous capture mode can capture counter data by detecting a trigger pulse even if the pulse is ...

Page 263: ...nt src_size 0x1 halfword R_power 0x0 arbitrated for every transfer n_minus_1 Number of transfer data cycle_ctrl 0x1 basic transfer 17 4 4 TOUT Output Control Comparator mode can generate TOUT signals using the comparator MATCH and counter MAX ZERO signals The generated signals can be output to outside the IC Figure 17 4 4 1 shows the TOUT output circuits circuits 0 and 1 TOUT output control 0 Comp...

Page 264: ...etting to 1 Figures 17 4 4 2 and 17 4 4 3 show the TOUT output waveforms 1 0 2 3 4 5 0 1 2 3 4 5 0 1 2 3 RUN PRESET Count clock T16B_nTC TC 15 0 MATCH signal MAX signal T16B_nCCCTLm TOUTO TOUT output Software control mode 0x0 Set mode 0x1 Toggle reset mode 0x2 Set reset mode 0x3 Toggle mode 0x4 Reset mode 0x5 Toggle set mode 0x6 Reset set mode 0x7 MAX value 5 Compare buffer value 2 T16B_nCCCTLm TO...

Page 265: ...value 2 T16B_nCCCTLm TOUTINV bit 0 2 Repeat down count mode indicates the T16B_nCCCTLm TOUTMD 2 0 bit setting value RUN PRESET Count clock T16B_nTC TC 15 0 MATCH signal MAX signal T16B_nCCCTLm TOUTO TOUT output Software control mode 0x0 Set mode 0x1 Toggle reset mode 0x2 Set reset mode 0x3 Toggle mode 0x4 Reset mode 0x5 Toggle set mode 0x6 Reset set mode 0x7 MAX value 5 Compare buffer value 2 T16B...

Page 266: ...Software control mode 0x0 TOUTn0 TOUTn1 Set mode 0x1 TOUTn0 TOUTn1 Toggle reset mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggle set mode 0x6 TOUTn0 TOUTn1 Reset set mode 0x7 TOUTn0 TOUTn1 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16B_nCCCTLm TOUTINV bit 0 1 Repeat up count mode indicates the T16B_nCCCTLm...

Page 267: ...TOUTn1 Set mode 0x1 TOUTn0 TOUTn1 Toggle reset mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggle set mode 0x6 TOUTn0 TOUTn1 Reset set mode 0x7 TOUTn0 TOUTn1 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16B_nCCCTLm TOUTINV bit 0 2 Repeat down count mode indicates the T16B_nCCCTLm TOUTMD 2 0 bit setting value 4...

Page 268: ... mode 0x2 TOUTn0 TOUTn1 Set reset mode 0x3 TOUTn0 TOUTn1 Toggle mode 0x4 TOUTn0 TOUTn1 Reset mode 0x5 TOUTn0 TOUTn1 Toggle set mode 0x6 TOUTn0 TOUTn1 Reset set mode 0x7 TOUTn0 TOUTn1 1 0 2 3 4 5 4 3 2 1 0 1 2 3 4 5 MAX value 5 Compare buffer 0 value 2 Compare buffer 1 value 3 T16B_nCCCTLm TOUTINV bit 0 3 Repeat up down count mode indicates the T16B_nCCCTLm TOUTMD 2 0 bit setting value Figure 17 4 ...

Page 269: ...pture flag T16B_nINTF CMPCAPmIF When the counter value becomes equal to the com pare buﬀer value in comparator mode When the counter value is loaded to the T16B_nCCRm register by a capture trigger input in capture mode When the DMA transfer request is ac cepted Counter MAX zero Counter MAX flag T16B_nINTF CNTMAXIF Counter zero flag T16B_nINTF CNTZEROIF When the counter reaches the MAX value in up ...

Page 270: ... 1 2 1 2 0x0 1 1 1 1 1 1 Note The oscillator circuits external inputs that are not supported in this IC cannot be selected as the clock source T16B Ch n Counter Control Register Register name Bit Bit name Initial Reset R W Remarks T16B_nCTL 15 9 0x00 R 8 MAXBSY 0 H0 R 7 6 0x0 R 5 4 CNTMD 1 0 0x0 H0 R W 3 ONEST 0 H0 R W 2 RUN 0 H0 R W 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W Bits 15 9 Reserved Bit 8 MAXB...

Page 271: ...as been set to the T16B_nMC register is preset to the counter However the T16B_nCTL MODEN bit must be set to 1 in conjunction with this bit or it must be set in advance Bit 0 MODEN This bit enables the T16B Ch n operations 1 R W Enable Start supplying operating clock 0 R W Disable Stop supplying operating clock Note The counter reset operation using the T16B_nCTL PRESET bit and the counting start ...

Page 272: ...dicate the signal level currently input to the CAPnm pin 1 R Input signal High level 0 R Input signal Low level The following shows the correspondence between the bit and the CAPnm pin T16B_nCS CAPI5 bit CAPn5 pin T16B_nCS CAPI4 bit CAPn4 pin T16B_nCS CAPI3 bit CAPn3 pin T16B_nCS CAPI2 bit CAPn2 pin T16B_nCS CAPI1 bit CAPn1 pin T16B_nCS CAPI0 bit CAPn0 pin Note The configuration of the T16B_nCS CA...

Page 273: ...nterrupt occurred 1 W Clear flag 0 W Ineffective The following shows the correspondence between the bit and interrupt T16B_nINTF CAPOW5IF bit Capture 5 overwrite interrupt T16B_nINTF CMPCAP5IF bit Compare capture 5 interrupt T16B_nINTF CAPOW4IF bit Capture 4 overwrite interrupt T16B_nINTF CMPCAP4IF bit Compare capture 4 interrupt T16B_nINTF CAPOW3IF bit Capture 3 overwrite interrupt T16B_nINTF CMP...

Page 274: ...terrupt T16B_nINTE CAPOW5IE bit Capture 5 overwrite interrupt T16B_nINTE CMPCAP5IE bit Compare capture 5 interrupt T16B_nINTE CAPOW4IE bit Capture 4 overwrite interrupt T16B_nINTE CMPCAP4IE bit Compare capture 4 interrupt T16B_nINTE CAPOW3IE bit Capture 3 overwrite interrupt T16B_nINTE CMPCAP3IE bit Compare capture 3 interrupt T16B_nINTE CAPOW2IE bit Capture 2 overwrite interrupt T16B_nINTE CMPCAP...

Page 275: ...comparison value set previously Also the counter is reset to 0x0000 simultaneously Down mode When the counter becomes equal to the comparison value set previously Also the counter is reset to the MAX value simultaneously Up down mode When the counter becomes equal to the comparison value set previously Also the counter is reset to 0x0000 simultaneously 0x3 Up mode When the counter reverts to 0x000...

Page 276: ...ode and is ineffective in capture mode Bits 4 2 TOUTMD 2 0 These bits configure how the TOUTnm signal waveform is changed by the comparator MATCH and counter MAX ZERO signals The T16B_nCCCTLm TOUTMD 2 0 bits are control bits for comparator mode and are ineffective in capture mode Table 17 7 5 TOUT Generation Mode T16B_nCCCTLm TOUTMD 2 0 bits TOUT generation mode and operations T16B_nCCCTLm TOUTMT ...

Page 277: ...signal is inverted by the MATCHm signal and it be comes inactive by the MATCHm 1 signal TOUTnm 1 The signal is inverted by the MATCHm 1 signal and it be comes inactive by the MATCHm signal 0x1 Set mode 0 All count modes TOUTnm The signal becomes active by the MATCH signal 1 All count modes TOUTnm The signal becomes active by the MATCHm or MATCHm 1 signal TOUTnm 1 The signal becomes active by the M...

Page 278: ...able DMA transfer request Each bit corresponds to a DMA controller channel The high order bits for the unimplemented chan nels are ineffective T16B Ch n Compare Capture m DMA Request Enable Register Register name Bit Bit name Initial Reset R W Remarks T16B_nCCmDMAEN 15 0 CCmDMAEN 15 0 0x0000 H0 R W Bits 15 0 CCmDMAEN 15 0 These bits enable T16B to issue a DMA transfer request to the corresponding ...

Page 279: ... 1 shows the REMC3 configuration Table 18 1 1 REMC3 Channel Configuration of S1C31D50 D51 Item 48 pin package 64 pin package 80 pin package 100 pin package Number of channels 1 transmitter channel REMC3 Carrier signal generator Data signal generator DBCNT 15 0 CLKSRC 1 0 CLKDIV 3 0 Clock generator DBRUN MODEN DBLENBSY CLK_REMC3 REMO Interrupt control circuit CRPER 7 0 CRDTY 7 0 CARREN PRESET PRUN ...

Page 280: ...ode the REMC3 operating clock CLK_REMC3 must be configured so that it will keep supplying by writing 0 to the CLGOSC xxxxSLPC bit for the CLK_REMC3 clock source If the CLGOSC xxxxSLPC bit for the CLK_REMC3 clock source is 1 the CLK_REMC3 clock source is deacti vated during SLEEP mode and REMC3 stops with the register settings maintained at those before entering SLEEP mode After the CPU returns to ...

Page 281: ...ster bits Set the REMC3DBCTL PRESET bit to 1 Reset internal counters Set the REMC3DBCTL PRUN bit to 1 Start counting Continuous data transmission control The following shows a procedure to send data continuously after starting data transmission after Step 3 above 1 Set the duty and cycle for the subsequent data to the REMC3APLEN APLEN 15 0 and REMC3DBLEN DBLEN 15 0 bits respectively before a compa...

Page 282: ...and duty ratio can be calculated by the equations shown below fCLK_REMC3 CRDTY 1 Carrier frequency Duty ratio Eq 18 1 CRPER 1 CRPER 1 Where fCLK_REMC3 CLK_REMC3 frequency Hz CRPER REMC3CARR CRPER 7 0 bit setting value 1 255 CRDTY REMC3CARR CRDTY 7 0 bit setting value 0 254 REMC3CARR CRDTY 7 0 bits REMC3CARR CRPER 7 0 bits The 8 bit counter for carrier generation is reset by the REMC3DBCTL PRESET b...

Page 283: ...EMC3APLEN APLEN 15 0 bits REMC3DBLEN DBLEN 15 0 bits The 16 bit counter for data signal generation is reset by the REMC3DBCTL PRESET bit and is started stopped by the REMC3DBCTL PRUN bit When the counter value is matched with the REMC3APLEN APLEN 15 0 bits compare AP the data signal waveform is inverted When the counter value is matched with the REMC3DBLEN DBLEN 15 0 bits compare DB the data signa...

Page 284: ...N buffer and REMC3DBLEN buffer and the 16 bit counter value is compared with the compare buffers The comparison values are loaded into the compare buffers when the 16 bit counter is matched with the REMC3D BLEN buffer when the count for the data length has completed Therefore the next transmit data can be set dur ing the current data transmission When the compare buffers are enabled the buffer sta...

Page 285: ...3DBLEN DBLEN 15 0 REMC3CARR CRPER 7 0 REMC3CARR CRDTY 7 0 Figure 18 6 2 Example of Generated Drive Waveform The REMO and CLPLS signals are output from the respective pins while the REMC3DBCTL PRUN bit 1 The difference between the setting values of the REMC3DBLEN DBLEN 15 0 bits and REMC3APLEN APLEN 15 0 bits becomes the CLPLS pulse width high period 18 7 Control Registers REMC3 Clock Control Regis...

Page 286: ...the REMC3DBCTL MODEN bit 0 REMC3 Data Bit Counter Control Register Register name Bit Bit name Initial Reset R W Remarks REMC3DBCTL 15 10 0x00 R 9 PRESET 0 H0 S0 R W Cleared by writing 1 to the REMC3DBCTL REMCRST bit 8 PRUN 0 H0 S0 R W 7 5 0x0 R 4 REMOINV 0 H0 R W 3 BUFEN 0 H0 R W 2 TRMD 0 H0 R W 1 REMCRST 0 H0 W 0 MODEN 0 H0 R W Bits 15 10 Reserved Bit 9 PRESET This bit resets the internal counter...

Page 287: ...fer to REMO Output Waveform Data signal Bit 1 REMCRST This bit issues software reset to the REMC3 1 W Issue software reset 0 W Ineffective 1 R Software reset is executing 0 R Software reset has finished During normal operation Setting this bit resets the REMC3 internal counters and interrupt flags This bit is automatically cleared after the reset processing has finished Note After the data signal ...

Page 288: ...n the counter exceeds the REMC3DBLEN DBLEN 15 0 bit setting value See Figure 18 4 3 3 Before this register can be rewritten the REMC3DBCTL MODEN bit must be set to 1 REMC3 Status and Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks REMC3INTF 15 11 0x00 R 10 DBCNTRUN 0 H0 S0 R Cleared by writing 1 to the REMC3DBCTL REMCRST bit 9 DBLENBSY 0 H0 R Effective when the REMC3DB...

Page 289: ...nce between the bit and interrupt REMC3INTE DBIE bit Compare DB interrupt REMC3INTE APIE bit Compare AP interrupt REMC3 Carrier Waveform Register Register name Bit Bit name Initial Reset R W Remarks REMC3CARR 15 8 CRDTY 7 0 0x00 H0 R W 7 0 CRPER 7 0 0x00 H0 R W Bits 15 8 CRDTY 7 0 These bits set the high level period of the carrier signal The carrier signal is set to high level from the 8 bit coun...

Page 290: ...erts the REMO output polarity 1 R W Inverted 0 R W Non inverted For more information see Figure 18 4 3 1 Bits 7 1 Reserved Bit 0 CARREN This bit enables carrier modulation 1 R W Enable carrier modulation 0 R W Disable carrier modulation output data signal only Note When carrier modulation is disabled the REMC3DBCTL REMOINV bit should be set to 0 ...

Page 291: ...ration of S1C31D50 D51 Item 48 pin package 64 pin package 80 pin package 100 pin package Number of channels 1 channel Ch 0 Number of analog signal inputs per channel Ch 0 5inputs ADIN00 04 Ch 0 7 inputs ADIN00 06 Ch 0 8 inputs ADIN00 07 Ch 0 8 inputs ADIN00 07 16 bit timer used as conversion clock and trigger sources Ch 0 16 bit timer Ch 7 VREFA pin reference voltage input External input ADC12A Ch...

Page 292: ...C converter Sensor 3 3 V Figure 19 2 2 1 Connections between ADC12A and External Devices 19 3 Clock Settings 19 3 1 ADC12A Operating Clock The 16 bit timer Ch k operating clock CLK_T16_k is also used as the ADC12A operating clock For more informa tion on the CLK_T16_k settings and clock supply in SLEEP and DEBUG modes refer to Clock Settings in the 16 bit Timers chapter Note When the CLK_T16_k sup...

Page 293: ... Select conversion start trigger source ADC12A_nTRG CNVMD bit Set conversion mode ADC12A_nTRG STMD bit Set data storing mode ADC12A_nTRG STAAIN 2 0 bits Set analog input pin to be A D converted first ADC12A_nTRG ENDAIN 2 0 bits Set analog input pin to be A D converted last 5 Set the ADC12A_nCFG VRANGE 1 0 bits Set operating voltage range according to VDD 6 Set the following bits when using the int...

Page 294: ...rupt i If the ADC12A_nINTF ADmCIF bit 1 analog input signal m A D conversion completion interrupt clear the ADC12A_nINTF ADmCIF bit and then go to Step 3 ii If the ADC12A_nINTF OVIF bit 1 A D conversion result overwrite error interrupt clear the ADC12A_ nINTF OVIF bit and terminate as an error or retry A D conversion 3 Read the A D conversion result of the analog input m ADC12A_nADD ADD 15 0 bits ...

Page 295: ...n3 0x4 ADINn4 ADINn2 conversion result ADINn3 conversion result 0x5 ADINn5 ADINn4 conversion result Invalid trigger Overwrite 3 Continuous conversion mode ADC12A_nTRG CNVMD bit 1 A D conversion for ADINn3 4 ADC12A_nTRG STAAIN 2 0 bits 0x3 ADC12A_nTRG ENDAIN 2 0 bits 0x4 Software trigger ADC12A_nTRG CNVTRG 1 0 bits 0x0 ADC12A_nCTL ADST ADC12A_nCTL BSYSTAT ADC12A_nCTL ADSTAT 2 0 A D conversion opera...

Page 296: ...The ADC12A provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the CPU core only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt chapter 19 6 DMA Transfer Requests The ADC12A has a function to generate DMA transfer requests from the causes ...

Page 297: ...12A_nTRG CNVMD 0 If A D conversion is stopped after the maximum analog input pin number different in each model has been completed these bits indicate ADINn0 Bit 11 Reserved Bit 10 BSYSTAT This bit indicates whether the ADC12A is executing A D conversion or not 1 R W A D converting 0 R W Idle Bits 9 2 Reserved Bit 1 ADST This bit starts A D conversion or enables to accept triggers 1 R W Start samp...

Page 298: ...o be A D converted last See Table 19 7 1 for the relationship between analog input pins and bit setting values Note The analog input pin range to perform A D conversion must be set as ADC12A_nTRG ENDAIN 2 0 bits ADC12A_nTRG STAAIN 2 0 bits Bits 10 8 STAAIN 2 0 These bits set the analog input pin to be A D converted first See Table 19 7 1 for the relationship between analog input pins and bit setti...

Page 299: ... cycles ADC12A Ch n Configuration Register Register name Bit Bit name Initial Reset R W Remarks ADC12A_nCFG 15 8 0x00 R 7 2 0x00 R 1 0 VRANGE 1 0 0x0 H0 R W Note Make sure that the ADC12A_nCTL BSYSTAT bit is set to 0 before altering the ADC12A_nCFG reg ister Bits 15 2 Reserved Bits 1 0 VRANGE 1 0 These bits set the A D converter operating voltage range Table 19 7 4 A D Converter Operating Voltage ...

Page 300: ...he correspondence between the bit and interrupt ADC12A_nINTF OVIF bit A D conversion result overwrite error interrupt ADC12A_nINTF ADmCIF bit Analog input signal m A D conversion completion interrupt ADC12A Ch n Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks ADC12A_nINTE 15 9 0x00 R 8 OVIE 0 H0 R W 7 AD7CIE 0 H0 R W 6 AD6CIE 0 H0 R W 5 AD5CIE 0 H0 R W 4 AD4CIE 0 H0 ...

Page 301: ...A transfer request to the corresponding DMA controller channel Ch 0 Ch 15 when the A D conversion for each analog input has completed 1 R W Enable DMA transfer request 0 R W Disable DMA transfer request Each bit corresponds to a DMA controller channel The high order bits for the unimplemented chan nels are ineffective ADC12A Ch n Result Register Register name Bit Bit name Initial Reset R W Remarks...

Page 302: ... or a humidity sensor and a few passive elements resistor and capacitor Allows measurement counting by inputting external clocks Provides an output and continuous oscillation function for monitoring the oscillation frequency Can generate reference oscillation completion sensor A and B oscillation completion measurement counter overflow error and time base counter overflow error interrupts Figure 2...

Page 303: ...rt before activating the RFC For more information refer to the I O Ports chapter Note The RFINn pin goes to VSS level when the port is switched Be aware that large current may flow if the pin is biased by an external circuit 20 2 2 External Connections The figures below show connection examples between the RFC and external sensors For the oscillation mode and external clock input mode refer to Ope...

Page 304: ... 2 Clock Supply in SLEEP Mode When using RFC during SLEEP mode the RFC operating clock TCCLK must be configured so that it will keep supplying by writing 0 to the CLGOSC xxxxSLPC bit for the TCCLK clock source 20 3 3 Clock Supply in DEBUG Mode The TCCLK supply during DEBUG mode should be controlled using the RFC_nCLK DBRUN bit The TCCLK supply to the RFC is suspended when the CPU enters DEBUG mode...

Page 305: ...itt input threshold voltage VT and Low level Schmitt input thresh old voltage VT in the Electrical Characteristics chapter This function is enabled by setting the RFC_nCTL EVTEN bit to 1 The measurement procedure is the same as when the internal oscillation circuit is used 20 4 3 RFC Counters The RFC incorporates two counters shown below Measurement counter MC The measurement counter is a 24 bit p...

Page 306: ...it and then go to Step 6 ii If the RFC_nINTF OVTCIF bit 1 time base counter overflow error clear the RFC_nINTF OVTCIF bit and terminate measurement as an error or retry after altering the measurement counter initial value 6 Clear the RFC_nINTF ESENAIF RFC_nINTF ESENBIF and RFC_nINTF OVMCIF bits by writing 1 7 Set the RFC_nTRG SSENA bit sensor A or the RFC_nTRG SSENB bit sensor B corresponding to t...

Page 307: ...t this point Max count value 0xffffff Min count value 0x000000 Max count value 0xffffff Min count value 0x000000 Overflow normal termination EREFIF 1 SREF 0 Overflow error termination OVMCIF 1 SSENx 0 Count value m1 Count value m2 Varies depending on the environment Calculate the sensor detecting value from the measurement counter value m1 and m2 Overflow error termination OVTCIF 1 SREF 0 Underflo...

Page 308: ...D VSS VDD VSS RFC_nCTL CONEN Writing 1 Writing 0 Figure 20 4 5 1 CR Oscillation Clock RFCLK Waveform 20 5 Interrupts The RFC has a function to generate the interrupts shown in Table 20 5 1 Table 20 5 1 RFC Interrupt Function Interrupt Interrupt flag Set condition Clear condition Reference oscillation completion RFC_nINTF EREFIF When reference oscillation has been completed normally due to a measur...

Page 309: ...of the RFC Table 20 6 1 Clock Source and Division Ratio Settings RFC_nCLK CLKDIV 1 0 bits RFC_nCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSC OSC1 OSC3 EXOSC 0x3 1 8 1 1 1 8 1 1 0x2 1 4 1 4 0x1 1 2 1 2 0x0 1 1 1 1 Note The oscillation circuits external input that are not supported in this IC cannot be selected as the clock source Note The RFC_nCLK register settings can be altered only when the RFC_nCTL ...

Page 310: ...ensor measurements 0x0 DC oscillation mode for resistive sensor measurements Bits 3 1 Reserved Bit 0 MODEN This bit enables the RFC operations 1 R W Enable RFC operations The operating clock is supplied 0 R W Disable RFC operations The operating clock is stopped Note If the RFC_nCTL MODEN bit is altered from 1 to 0 during R F conversion the counter value being converted cannot be guaranteed R F co...

Page 311: ... Or Register name Bit Bit name Initial Reset R W Remarks RFC_nMCL RFC_nMCH 31 24 0x00 R 23 0 MC 23 0 0x000000 H0 R W Bits 31 24 Reserved Bits 23 0 MC 23 0 Measurement counter data can be read and written through these bits Note The measurement counter must be set from the low order value RFC_nMCL MC 15 0 bits first when data is set using a 16 bit access instruction The counter may not be set to th...

Page 312: ...pt RFC_nINTF ESENBIF bit Sensor B oscillation completion interrupt RFC_nINTF ESENAIF bit Sensor A oscillation completion interrupt RFC_nINTF EREFIF bit Reference oscillation completion interrupt RFC Ch n Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks RFC_nINTE 15 8 0x00 R 7 5 0x0 R 4 OVTCIE 0 H0 R W 3 OVMCIE 0 H0 R W 2 ESENBIE 0 H0 R W 1 ESENAIE 0 H0 R W 0 EREFIE 0 ...

Page 313: ...ted See Table 21 1 1 Sequential playing of multiple sound files External QSPI Flash supported for storing sound data Either SDAC or T16B Ch 0 TOUT can be selected as the sound output circuit via software See Table 21 1 1 Note T16B Ch 0 cannot be used while the S1C31D51 is outputting sound through the T16B Ch 0 TOUT Do not use T16B Ch 0 to generate interrupts refer to Section 17 5 and DMA transfer ...

Page 314: ...y check circuit Sound decoder Sound signal generator HWPIE HWP0TRG HWP1IF HWP0IF CPU core Embedded Flash memory RAM Quad synchronous serial interface External Flash memory SDACOUT_P SDACOUT_N Internal data bus Sound signal generator T16B Ch 0 TOUT00 TOUT01 ID 7 0 Figure 21 1 1 HWP Configuration Notes In addition to the control registers in the MCU peripheral circuit area the HWP has HWP in ternal ...

Page 315: ...und signal output Indicates the status when the pin is configured for T16B Ch 0 Notes When using T16B Ch 0 for sound output the T16B Ch 0 output functions must be assigned to the ports T16B Ch 0 cannot be used while the S1C31D51 is outputting sound through the T16B Ch 0 TOUT 21 2 2 External Connections Figures 21 2 2 1 and 21 2 2 2 show external circuit examples to input the SDAC sound signals to ...

Page 316: ...r in the Power Supply Reset and Clocks chapter The memory check function allows the HWP to use SYSCLK at any arbitrary frequency 21 3 2 Clock Supply in SLEEP Mode The HWP and SDAC stop operating in SLEEP mode as the SYSCLK stops Do not put the IC into SLEEP mode while the HWP is operating 21 3 3 Clock Supply in DEBUG Mode The sound play and memory check functions can operate even in DEBUG mode as ...

Page 317: ...g HWP operation sound play function 9 Set the SDACMOD PWMOUTEN bit to 1 Enable sound output 10 Enable the external amplifier using a general purpose output port if necessary Set a wait time according to the amplifier specifications after being enabled 11 Set the HWPCTL HWPEN bit to 1 Enable HWP 12 Wait until the HWPINTF HWP0IF bit is set to 1 and the STATE_n STATE 15 0 bits are set to 0x0001 sp_st...

Page 318: ...und play function register bits Set the FUNCTION ID 7 0 bits to 0x02 Select sound play function INTMASK TO_MUTE bit Set mute interrupt mask INTMASK TO_PAUSE bit Set pause interrupt mask INTMASK TO_PLAY bit Set playback start interrupt mask INTMASK TO_IDLE bit Set idle state interrupt mask ROMADDR ADDRESS 31 0 bits Set sound ROM data start address ROMSIZE SIZE 31 0 bits Set sound ROM data size KEYC...

Page 319: ...uance of the Sound Start command After the Sound Start command is issued the HWP transits to sp_state_play state to start playback output 4 sp_state_play This is the state in which the HWP is performing playback output This state allows issuance of the Sound Stop Pause or Mute command When the sound data ends or the Sound Stop command is issued the HWP stops playback output and returns to sp_state...

Page 320: ...the COMMAND_n COMMAND 7 0 bits Select command 5 Write 1 to the HWPCMDTRG HWP0TRG bit Trigger to issue command 6 Wait until the HWPINTF HWP0IF bit is set to 1 interrupt Occurrence of state transition 7 Confirm that the STATE_n STATE 15 0 bits transit destination state if necessary Playback start stop Single channel playback output start procedure The following shows a Ch n playback output start pro...

Page 321: ...PINTF HWP0IF bit Clear interrupt flag Ch 0 voice output start procedure 8 Confirm that the STATE_0 STATE 15 0 bits 0x0001 sp_state_idle 9 Confirm that the STATUS READY bit 1 Command acceptable 10 Configure the following sound play register bits Set the COMMAND_0 COMMAND 7 0 bits to 0x01 Select Sound Start command SENTENCE_0 SENTENCE_NO 15 0 bits Specify sentence number VOLUME_0 VOLUME 15 0 bits Sp...

Page 322: ...hing fade out process for the playback output signal is carried out to suppress the occurrence of noise Command execution Mute Pause Stop Immediately command Time Smoothing process Sound level Figure 21 4 1 2 Smoothing Process when Playback Output is Suspended Mute after Current Phrase command The sound is muted after ending the phrase that is being output when the command is issued Command execut...

Page 323: ... of state transition The HWP pauses the playback output from this point 6 Confirm that the STATE_n STATE 15 0 bits 0x0003 sp_state_pause as necessary 7 Write 0 to the HWPINTF HWP0IF bit Clear interrupt flag Two pause commands are available Setting the COMMAND_n COMMAND 7 0 bits to 0x04 selects the Pause Immediately command setting to 0x05 selects the Pause after Current Phrase command Pause Immedi...

Page 324: ...e phrase that is being output when the command is issued See Figure 21 4 1 3 In the pause or mute state the playback is terminated by releasing the pause or mute state immediately re gardless of which of the Sound Stop commands is issued Sound play error When an error occurs during processing of the sound play function the HWPINTF HWP1IF bit is set to 1 an interrupt can be generated The error cont...

Page 325: ...HWPINTF HWP1IF bit 1 Once the memory check function register bits have been set in Step 3 it is not necessary to set again until they need to be altered When altering these register bits perform the above processing from Step 2 Memory check state transition Figure 21 4 2 1 shows the memory check state transition diagram FUNCTION ID 7 0 bits 0x03 memory check HWPCTL HWPEN bit 1 HWPCTL HWPEN bit 0 M...

Page 326: ...ing the Flash memory check that calculates the checksum When the Flash Checksum Start command is issued in mc_state_idle state the HWP transits to this state When the check has completed or the Memory Check Stop command is issued the HWP returns to mc_state_idle state 7 mc_state_crc This is the state in which the HWP is performing the Flash memory check that calculates the CRC When the Flash CRC S...

Page 327: ...ress 10 Wait until the HWPINTF HWP0IF bit is set to 1 interrupt Occurrence of state transition The memory check is completed at this point 11 Confirm that the STATE STATE 15 0 bits 0x0001 mc_state_idle 12 Write 0 to the HWPINTF HWP0IF bit Clear interrupt flag 13 Read the STATUS PROCESSING 1 0 bits Confirm check result When the STATUS PROCESSING 1 0 bits 0x2 the check has completed without an error...

Page 328: ... is set to 1 interrupt Occurrence of state transition The memory check is completed at this point 12 Confirm that the STATE STATE 15 0 bits 0x0001 mc_state_idle 13 Write 0 to the HWPINTF HWP0IF bit Clear interrupt flag 14 Confirm that the STATUS PROCESSING 1 0 bits 0x2 check completed 15 Read the RESULT RESULT 31 0 bits Confirm check result These bits hold the checksum or CRC calculation result 16...

Page 329: ...ue a valid command When a fatal error has occurred remove the cause of error and redo the processing from initialization 21 5 Interrupts The HWP has a function to generate the interrupts shown in Table 21 5 1 Table 21 5 1 HWP Interrupt Function Interrupt Interrupt flag Set condition Clear condition Error occurrence HWPINTF HWP1IF When a sound play error see Table 21 4 1 2 or a memory check error s...

Page 330: ...Ch 0 Volume Control Register Base 0x1a VOLUME_1 Ch 1 Volume Control Register Base 0x1c REPEAT_0 Ch 0 Repeat Control Register Base 0x1e REPEAT_1 Ch 1 Repeat Control Register Base 0x20 SPEED_0 Ch 0 Playback Speed Conversion Register Base 0x40 STATE_0 Ch 0 State Monitor Register STATE State Monitor Register Base 0x42 STATE_1 Ch 1 State Monitor Register Base 0x44 ERROR Error Status Register ERROR Erro...

Page 331: ...und data ROM start address The address should be specified with a value shown below In case of internal Flash 0x00 0000 0x02 fff0 16 byte alignment In case of external QSPI Flash 0x00 0000 OFFSET 0x10 0000 OFFSET 0x20 0000 OFFSET 0xe0 0000 OFFSET 0xf0 0000 OFFSET The OFFSET is 0x04 0000 the start address of the memory mapped access area for external Flash memory refer to Figure 4 1 1 Memory Map RO...

Page 332: ... both channels Depending on the contents of the sentence to play the played voice may be difficult to hear even if gapless play is enabled Conduct sufficient evaluation when using the gapless play function Bits 7 0 COMMAND 7 0 These bits select a sound play command to be executed Table 21 6 4 Sound Play Command Selection COMMAND_n COMMAND 7 0 bits Sound play command 0xff 0x0a Setting prohibited er...

Page 333: ... bits specify the number of repeat playbacks Table 21 6 6 Setting of Number of Repeat Playbacks REPEAT_n REPEAT 15 0 bits Playback counts 0xff Repeat until Sound Stop command execution 0xfe 254 times 0x7e 253 times 0x7d 252 times 0x3 3 times 0x02 2 times 0x01 1 time no repetition 0x00 Setting prohibited Ch 0 Playback Speed Conversion Register Register name Bit Bit name Initial Reset R W Remarks SP...

Page 334: ...P is running For the errors that may oc cur in the sound play function refer to Table 21 4 1 2 Operating Status Register Register name Bit Bit name Initial Reset R W Remarks STATUS Sound Play 15 9 0x00 R 8 SOUNDOUT 0 H0 R 7 1 0x00 R 0 READY 0 H0 R Bits 15 9 Reserved Bit 8 SOUNDOUT This bit indicates whether the HWP is performing playback output or not 1 R During playback sp_state_play sp_state_mut...

Page 335: ...er Bit 1 TO_PROCESSING Bit 0 TO_IDLE These bits set whether the interrupt request when a state transition occurs during executing the memo ry check function is enabled or not 1 W Enable interrupt 0 W Mask interrupt disabled For more information on the state transition interrupts that can be masked with these bits refer to Table 21 5 2 Memory Address Register Register name Bit Bit name Initial Rese...

Page 336: ...OMMAND Memory Check 15 8 0x00 R 7 0 COMMAND 7 0 0x00 H0 W Bits 15 8 Reserved Set to 0x00 when writing data to this register Bits 7 0 COMMAND 7 0 These bits select a memory check command to be executed Table 21 6 9 Memory Check Command Selection COMMAND COMMAND 7 0 bits Memory check command 0xff Memory Check Stop 0xfe 0x06 Setting prohibited error 0x05 Flash CRC Start 0x04 Flash Checksum Start 0x03...

Page 337: ...d with an error 0x0002 Completed successfully Completed 0x0001 During checking During checking 0x0000 During standby During standby Bits 7 1 Reserved Bit 0 READY This bit indicates the HWP operating status whether a command is acceptable or not 1 R Ready Command is acceptable 0 R Busy Command is not acceptable Calculation Result Register Register name Bit Bit name Initial Reset R W Remarks RESULT ...

Page 338: ...F Bit 0 HWP0IF These bits indicate the HWP interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Setting prohibited 0 W Clear flag The following shows the correspondence between the bit and interrupt HWPINTF HWP1IF bit Error occurrence interrupt HWPINTF HWP0IF bit State transition interrupt Note Be aware that the writing value to clear the flags i...

Page 339: ...ode Bits 7 6 Reserved Bits 5 4 CLKDIV 1 0 These bits select the division ratio of the SDAC operating clock Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the clock source of SDAC Table 21 7 1 Clock Source and Division Ratio Settings SDACCLK CLKDIV 1 0 bits SDACCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 IOSC OSC1 OSC3 EXOSC 0x3 Reserved Reserved Reserved Reserved 0x2 0x1 0x0 1 1 1 1 1 1 Note The ...

Page 340: ...e bits store sound data Note This register is used by the HWP Do not write any data to this register while the HWP operation is enabled HWPCTL HWPEN bit 1 SDAC Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks SDACINTF 15 8 0x00 R 7 2 0x00 R 1 ERRIF 0 H0 R W Cleared by writing 1 0 DATREQIF 0 H0 R W Bits 15 2 Reserved Bit 1 ERRIF Bit 0 DATREQIF These bits indicate the SDA...

Page 341: ... 0 DATREQIE 0 H0 R W Bits 15 2 Reserved Bit 1 ERRIE Bit 0 DATREQIE These bits enable SDAC interrupts 1 R W Enable interrupts 0 R W Disable interrupts The following shows the correspondence between the bit and interrupt SDACINTE ERRIE bit Error occurrence interrupt SDACINTE DATREQIE bit Data request interrupt Note This register is used by the HWP Do not write any data to this register while the HWP...

Page 342: ... Flash interface power supply voltage VDDQSPI For P90 95 and QSPI When QSPI is used 3 0 3 6 V When QSPI is not used 1 8 5 5 V Flash programming voltage VPP 7 3 7 5 7 7 V OSC1 oscillator oscillation frequency fOSC1 Crystal oscillator 32 768 kHz OSC3 oscillator oscillation frequency fOSC3 Crystal ceramic oscillator 0 2 16 8 MHz EXOSC external clock frequency fEXOSC When supplied from an external osc...

Page 343: ...C1 32 768 kHz 3 OSC3 OFF SYSCLK IOSC 2 100 2 580 µA IRUN2 7 IOSC 2 MHz 2 OSC1 32 768 kHz 3 OSC3 OFF SYSCLK IOSC 520 650 µA IRUN3 7 IOSC 2 MHz 2 OSC1 32 768 kHz 3 OSC3 OFF SYSCLK IOSC PWGACTL REGSEL bit 0 mode1 310 390 µA IRUN4 7 IOSC OFF OSC1 32 768 kHz 3 OSC3 OFF SYSCLK OSC1 8 14 µA IOSC OFF OSC1 32 kHz 4 OSC3 OFF SYSCLK OSC1 10 18 µA IRUN5 7 IOSC OFF OSC1 32 768 kHz 3 OSC3 OFF SYSCLK OSC1 PWGACT...

Page 344: ...Current consumption temperature characteristic Current consumption temperature characteristic in HALT mode IOSC operation in HALT mode OSC1 operation IOSC ON OSC1 32 768 kHz OSC3 OFF Typ value IOSC OFF OSC1 32 768 kHz OSC3 OFF Typ value 50 700 600 500 400 300 200 100 0 25 0 25 50 75 100 Ta C I HALT1 3 µA 2 MHz 8 MHz 1 MHz 50 5 4 3 2 1 0 25 0 25 50 75 100 Ta C I HALT5 µA CLGOSC1 OSC1SELCR bit 1 0 C...

Page 345: ... in RUN mode OSC1 operation in RUN mode OSC3 operation IOSC OFF OSC1 32 768 kHz OSC3 OFF Typ value IOSC OFF OSC1 32 768 kHz OSC3 ON internal oscillator Typ value 0 50 14 12 10 8 6 4 2 0 25 0 25 50 75 100 Ta C I RUN4 µA CLGOSC1 OSC1SELCRビット 1 50 4 500 4 000 3 500 3 000 2 500 2 000 1 500 1 000 500 0 25 0 25 50 75 100 Ta C I RUN7 µA 8 MHz 16 MHz 4 MHz 22 4 System Reset Controller SRC Characteristics...

Page 346: ...nless otherwise specified VDD 1 8 to 5 5 V VSS 0 V Ta 40 to 85 C Item Symbol Condition Min Typ Max Unit Reset hold time 1 tRSTR 0 1 0 2 ms 1 Time until the internal reset signal is negated after the reset request is canceled 22 5 Clock Generator CLG Characteristics Oscillator circuit characteristics including resonators change depending on conditions board pattern components used etc Use these cha...

Page 347: ...C1 CGI1 2 0 bits 0x2 16 pF CLGOSC1 OSC1SELCR bit 0 CLGOSC1 CGI1 2 0 bits 0x3 18 pF CLGOSC1 OSC1SELCR bit 0 CLGOSC1 CGI1 2 0 bits 0x4 19 pF CLGOSC1 OSC1SELCR bit 0 CLGOSC1 CGI1 2 0 bits 0x5 21 pF CLGOSC1 OSC1SELCR bit 0 CLGOSC1 CGI1 2 0 bits 0x6 23 pF CLGOSC1 OSC1SELCR bit 0 CLGOSC1 CGI1 2 0 bits 0x7 24 pF Crystal oscillator internal drain capacitance CDI1C CLGOSC1 OSC1SELCR bit 0 6 pF Crystal osci...

Page 348: ...0 16 16 40 MHz 40 to 85 C 15 44 16 16 56 MHz CLGOSC3 OSC3MD bit 0 CLGOSC3 OSC3FQ 1 0 bits 0x1 40 to 85 C 7 7 8 3 8 9 MHz CLGOSC3 OSC3MD bit 0 CLGOSC3 OSC3FQ 1 0 bits 0x0 40 to 85 C 3 8 4 2 4 6 MHz CLGOSC3 OSC3MD bit 0 CLGOSC3 OSC3FQ 1 0 bits 0x3 1 15 84 16 16 16 MHz 1 Corrected value immediately after the auto trimming operation has completed OSC3 internal oscillation frequency temperature charact...

Page 349: ...OM data programmed 22 7 Input Output Port PPORT Characteristics Unless otherwise specified VDD 1 8 to 5 5 V VSS 0 V Ta 40 to 85 C Item Symbol Condition Min Typ Max Unit High level Schmitt input threshold voltage VT 0 5 VDD 0 8 VDD V Low level Schmitt input threshold voltage VT 0 2 VDD 0 5 VDD V Schmitt input hysteresis voltage DVT 180 mV High level output current IOH VOH 0 9 VDD 0 5 mA Low level o...

Page 350: ...1 041 1 119 kW SVD3CTL SVDC 4 0 bits 0x1b 982 1 063 1 145 kW SVD3CTL SVDC 4 0 bits 0x1c 1 001 1 086 1 171 kW SVD3CTL SVDC 4 0 bits 0x1d 1 022 1 110 1 198 kW SVD3CTL SVDC 4 0 bits 0x1e 1 054 1 129 1 204 kW SVD3CTL SVDC 4 0 bits 0x1f 1 072 1 154 1 237 kW EXSVDn detection voltage VSVD_EXT SVD3CTL SVDC 4 0 bits 0x00 1 17 1 2 1 23 V SVD3CTL SVDC 4 0 bits 0x01 1 27 1 3 1 33 V SVD3CTL SVDC 4 0 bits 0x02 ...

Page 351: ...CTL SVDC 4 0 bits 0x16 3 90 4 0 4 10 V SVD3CTL SVDC 4 0 bits 0x17 4 00 4 1 4 20 V SVD3CTL SVDC 4 0 bits 0x18 4 10 4 2 4 31 V SVD3CTL SVDC 4 0 bits 0x19 4 19 4 3 4 41 V SVD3CTL SVDC 4 0 bits 0x1a 4 39 4 5 4 61 V SVD3CTL SVDC 4 0 bits 0x1b 4 49 4 6 4 72 V SVD3CTL SVDC 4 0 bits 0x1c 4 58 4 7 4 82 V SVD3CTL SVDC 4 0 bits 0x1d 4 68 4 8 4 92 V SVD3CTL SVDC 4 0 bits 0x1e 4 78 4 9 5 02 V SVD3CTL SVDC 4 0 ...

Page 352: ... UBRT2 IrDA mode 150 115 200 bps 22 10 Synchronous Serial Interface SPIA Characteristics Master mode Unless otherwise specified VSS 0 V Ta 40 to 85 C Item Symbol Condition VDD VD1 output Min Typ Max 単位 SPICLK0 cycle time tSCYC 1 8 to 5 5 V mode0 250 ns 1 8 to 3 6 V mode1 1 000 ns SPICLK0 High pulse width tSCKH 1 8 to 5 5 V mode0 100 ns 1 8 to 3 6 V mode1 400 ns SPICLK0 Low pulse width tSCKL 1 8 to...

Page 353: ...DI0 hold time tSDH 1 8 to 5 5 V mode0 20 ns 1 8 to 3 6 V mode1 70 ns SDO0 output delay time tSDO CL 15 pF 1 1 8 to 5 5 V mode0 100 ns 1 8 to 3 6 V mode1 250 ns SPISS0 setup time tSSS 1 8 to 5 5 V mode0 20 ns 1 8 to 3 6 V mode1 60 ns SPISS0 High pulse width tSSH 1 8 to 5 5 V mode0 100 ns 1 8 to 3 6 V mode1 400 ns SDO0 output start time tSDD CL 15 pF 1 1 8 to 5 5 V mode0 100 ns 1 8 to 3 6 V mode1 25...

Page 354: ...L mode0 60 ns mode1 200 ns QSDIOn 3 0 setup time tSDS mode0 10 ns mode1 30 ns QSDIOn 3 0 hold time tSDH mode0 10 ns mode1 50 ns QSDIOn 3 0 output delay time tSDO CL 15 pF 1 mode0 60 ns mode1 220 ns QSPISSn setup time tSSS mode0 10 ns mode1 30 ns QSPISSn High pulse width tSSH mode0 60 ns mode1 200 ns QSDIOn 3 0 output start time tSDD CL 15 pF 1 mode0 60 ns mode1 220 ns QSDIOn 3 0 output stop time t...

Page 355: ...REFAn 3 5 LSB Full scale error FSE VDD VREFAn 3 5 LSB Analog input resistance RADIN 4 kW Analog input capacitance CADIN 30 pF A D converter circuit current IADC ADC12A_nCFG VRANGE 1 0 bits 0x3 VDD VREFA ADIN VREFA 2 fSMP 100 ksps Ta 25 C 3 6 V 400 700 µA ADC12A_nCFG VRANGE 1 0 bits 0x2 VDD VREFA ADIN VREFA 2 fSMP 100 ksps Ta 25 C 4 8 V 230 470 µA ADC12A_nCFG VRANGE 1 0 bits 0x1 VDD VREFA ADIN VREF...

Page 356: ...equency fTCCLK 4 2 MHz High level Schmitt input threshold voltage VT 0 5 VDD 0 8 VDD V Low level Schmitt input threshold voltage VT 0 2 VDD 0 5 VDD V Schmitt input hysteresis voltage DVT 120 mV R F converter operating current IRFC CREF 1 000 pF RREF RSEN 100 kW Ta 25 C VDD 3 6 V 200 350 µA 1 In this characteristic unevenness between production lots and variations in measurement board resistances a...

Page 357: ...ce sensor oscillation current temperature characteristic consumption frequency characteristic RREF RSEN 100 kW CREF 1 000 pF Typ value CREF 1 000 pF Ta 25 C Typ value 50 18 16 14 12 10 8 6 4 2 0 25 0 25 50 75 100 Ta C f RFCLK kHz VDD 3 6 V 1 8 V 0 1 1 10 100 10 000 1 000 1 800 1 600 1 400 1 200 1 000 800 600 400 200 0 fRFCLK kHz I RFC µA VDD 3 6 V 1 8 V ...

Page 358: ...amic CVPP 1 8 5 5 V 2 4 5 5 V 1 or 2 7 5 5 V 2 3 0 3 6 V RDBG2 VDD QSPI REMO VDD IR transmitter module Speaker EXSVDn SDACOUT_P SDACOUT_N External voltage External circuit A D conversion inputs CVREFA 3 4 SENB0 SENA0 REF0 RFIN0 RTMP2 RTMP1 RREF CREF VDD VD1 VDDQSPI OSC1 OSC2 OSC3 OSC4 RESET TEST VSS CVDDQSPI The potential of the substrate back of the chip is VSS 1 For Flash programming when VPP is...

Page 359: ... IR transmitter module Speaker OR EXSVDn SDACOUT_P SDACOUT_N TOUT01 TOUT00 External voltage External circuit A D conversion inputs CVREFA 3 5 6 4 SENB0 SENA0 REF0 RFIN0 RTMP2 RTMP1 RREF CREF Buzzer External circuit VDD VD1 VDDQSPI OSC1 OSC2 OSC3 OSC4 RESET TEST VSS CVDDQSPI The potential of the substrate back of the chip is VSS 1 For Flash programming when VPP is supplied externally 2 For Flash pr...

Page 360: ...CPW1 Bypass capacitor between VSS and VDD Ceramic capacitor or electrolytic capacitor CPW2 Capacitor between VSS and VD1 Ceramic capacitor CVDDQSPI Capacitor between VSS and VDDQSPI Ceramic capacitor or electrolytic capacitor RREF RFC reference resistor Thick film chip resistor RTMP1 2 Resistive sensors Temperature sensor 103AP 2 manufactured by SEMITEC Corporation Humidity sensor C15 M53R manufac...

Page 361: ... Seiko Epson Corporation 24 1 Rev 2 00 24 Package TQFP12 48PIN P TQFP048 0707 0 50 7 9 25 36 7 9 13 24 INDEX 0 17min 0 27max 12 1 48 37 1 0 1 1 2 max 1 0 3min 0 7max 0 min 10 max 0 09min 0 2max 0 5 Figure 24 1 TQFP12 48PIN Package Dimensions ...

Page 362: ...on S1C31D50 D51 TECHNICAL MANUAL Rev 2 00 QFP13 64PIN P LQFP064 1010 0 50 10 12 33 48 10 12 17 32 INDEX 0 13min 0 27max 16 1 64 49 1 4 0 1 1 7 max 1 0 3min 0 75max 0 09min 0 2max 0 5 0 min 10 max Figure 24 2 QFP13 64PIN Package Dimensions ...

Page 363: ...NUAL Seiko Epson Corporation 24 3 Rev 2 00 TQFP14 80PIN P TQFP080 1212 0 50 12 14 41 60 12 14 21 40 INDEX 0 17min 0 27max 20 1 80 61 1 0 1 1 2 max 1 0 3min 0 75max 0 min 8 max 0 09min 0 2max 0 5 Figure 24 3 TQFP14 80PIN Package Dimensions ...

Page 364: ...n S1C31D50 D51 TECHNICAL MANUAL Rev 2 00 QFP15 100PIN P LQFP100 1414 0 50 0 3min 0 75max 0 09min 0 2max 14 16 51 75 14 16 26 50 INDEX 0 17min 0 27max 25 1 100 76 1 4 0 1 1 7 max 1 0 min 10 max 0 5 Figure 24 4 QFP15 100PIN Package Dimensions ...

Page 365: ...r name Bit Bit name Initial Reset R W Remarks 0x0020 0040 CLGSCLK CLG System Clock Control Register 15 WUPMD 0 H0 R WP 14 0 R 13 12 WUPDIV 1 0 0x0 H0 R WP 11 10 0x0 R 9 8 WUPSRC 1 0 0x0 H0 R WP 7 6 0x0 R 5 4 CLKDIV 1 0 0x2 H0 R WP 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R WP 0x0020 0042 CLGOSC CLG Oscillation Control Register 15 12 0x0 R 11 EXOSCSLPC 1 H0 R W 10 OSC3SLPC 1 H0 R W 9 OSC1SLPC 1 H0 R W 8 IOS...

Page 366: ...x00 R 8 OSC3TERIE 0 H0 R W 7 0 R 6 reserved 0 H0 R W 5 OSC1STPIE 0 H0 R W 4 OSC3TEDIE 0 H0 R W 3 0 R 2 OSC3STAIE 0 H0 R W 1 OSC1STAIE 0 H0 R W 0 IOSCSTAIE 0 H0 R W 0x0020 0050 CLGFOUT CLG FOUT Control Register 15 8 0x00 R 7 0 R 6 4 FOUTDIV 2 0 0x0 H0 R W 3 2 FOUTSRC 1 0 0x0 H0 R W 1 0 R 0 FOUTEN 0 H0 R W 0x0020 0080 Cache Controller CACHE Address Register name Bit Bit name Initial Reset R W Remark...

Page 367: ... as 0x00 0x0020 00c2 RTCAALM1 RTCA Second Alarm Register 15 0 R 14 12 RTCSHA 2 0 0x0 H0 R W 11 8 RTCSLA 3 0 0x0 H0 R W 7 0 0x00 R 0x0020 00c4 RTCAALM2 RTCA Hour Minute Alarm Register 15 0 R 14 RTCAPA 0 H0 R W 13 12 RTCHHA 1 0 0x0 H0 R W 11 8 RTCHLA 3 0 0x0 H0 R W 7 0 R 6 4 RTCMIHA 2 0 0x0 H0 R W 3 0 RTCMILA 3 0 0x0 H0 R W 0x0020 00c6 RTCASWCTL RTCA Stopwatch Control Register 15 12 BCD10 3 0 0x0 H0...

Page 368: ...F 0 H0 R W 3 T1_2SECIF 0 H0 R W 2 T1_4SECIF 0 H0 R W 1 T1_8SECIF 0 H0 R W 0 T1_32SECIF 0 H0 R W 0x0020 00d2 RTCAINTE RTCA Interrupt En able Register 15 RTCTRMIE 0 H0 R W 14 SW1IE 0 H0 R W 13 SW10IE 0 H0 R W 12 SW100IE 0 H0 R W 11 9 0x0 R 8 ALARMIE 0 H0 R W 7 T1DAYIE 0 H0 R W 6 T1HURIE 0 H0 R W 5 T1MINIE 0 H0 R W 4 T1SECIE 0 H0 R W 3 T1_2SECIE 0 H0 R W 2 T1_4SECIE 0 H0 R W 1 T1_8SECIE 0 H0 R W 0 T1...

Page 369: ...W 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R W 0x0020 0162 T16_0MOD T16 Ch 0 Mode Register 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W 0x0020 0164 T16_0CTL T16 Ch 0 Control Register 15 9 0x00 R 8 PRUN 0 H0 R W 7 2 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x0020 0166 T16_0TR T16 Ch 0 Reload Data Register 15 0 TR 15 0 0xffff H0 R W 0x0020 0168 T16_0TC T16 Ch 0 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x002...

Page 370: ... H0 R 1 P0IN1 0 H0 R 0 P0IN0 0 H0 R 0x0020 0202 P0IOEN P0 Port Enable Register 15 P0IEN7 0 H0 R W 14 P0IEN6 0 H0 R W 13 P0IEN5 0 H0 R W 12 P0IEN4 0 H0 R W 11 P0IEN3 0 H0 R W 10 P0IEN2 0 H0 R W 9 P0IEN1 0 H0 R W 8 P0IEN0 0 H0 R W 7 P0OEN7 0 H0 R W 6 P0OEN6 0 H0 R W 5 P0OEN5 0 H0 R W 4 P0OEN4 0 H0 R W 3 P0OEN3 0 H0 R W 2 P0OEN2 0 H0 R W 1 P0OEN1 0 H0 R W 0 P0OEN0 0 H0 R W 0x0020 0204 P0RCTL P0 Port ...

Page 371: ...7 P0IE7 0 H0 R W 6 P0IE6 0 H0 R W 5 P0IE5 0 H0 R W 4 P0IE4 0 H0 R W 3 P0IE3 0 H0 R W 2 P0IE2 0 H0 R W 1 P0IE1 0 H0 R W 0 P0IE0 0 H0 R W 0x0020 020a P0CHATEN P0 Port Chattering Filter Enable Register 15 8 0x00 R 7 P0CHATEN7 0 H0 R W 6 P0CHATEN6 0 H0 R W 5 P0CHATEN5 0 H0 R W 4 P0CHATEN4 0 H0 R W 3 P0CHATEN3 0 H0 R W 2 P0CHATEN2 0 H0 R W 1 P0CHATEN1 0 H0 R W 0 P0CHATEN0 0 H0 R W 0x0020 020c P0MODSEL ...

Page 372: ...0 R W 12 P1IEN4 0 H0 R W 11 P1IEN3 0 H0 R W 10 P1IEN2 0 H0 R W 9 P1IEN1 0 H0 R W 8 P1IEN0 0 H0 R W 7 P1OEN7 0 H0 R W 6 P1OEN6 0 H0 R W 5 P1OEN5 0 H0 R W 4 P1OEN4 0 H0 R W 3 P1OEN3 0 H0 R W 2 P1OEN2 0 H0 R W 1 P1OEN1 0 H0 R W 0 P1OEN0 0 H0 R W 0x0020 0214 P1RCTL P1 Port Pull up down Control Register 15 P1PDPU7 0 H0 R W 14 P1PDPU6 0 H0 R W 13 P1PDPU5 0 H0 R W 12 P1PDPU4 0 H0 R W 11 P1PDPU3 0 H0 R W ...

Page 373: ...0 H0 R W 4 P1CHATEN4 0 H0 R W 3 P1CHATEN3 0 H0 R W 2 P1CHATEN2 0 H0 R W 1 P1CHATEN1 0 H0 R W 0 P1CHATEN0 0 H0 R W 0x0020 021c P1MODSEL P1 Port Mode Select Register 15 8 0x00 R 7 P1SEL7 0 H0 R W 6 P1SEL6 0 H0 R W 5 P1SEL5 0 H0 R W 4 P1SEL4 0 H0 R W 3 P1SEL3 0 H0 R W 2 P1SEL2 0 H0 R W 1 P1SEL1 0 H0 R W 0 P1SEL0 0 H0 R W 0x0020 021e P1FNCSEL P1 Port Function Select Register 15 14 P17MUX 1 0 0x0 H0 R ...

Page 374: ...6 0 H0 R W 13 P2PDPU5 0 H0 R W 12 P2PDPU4 0 H0 R W 11 P2PDPU3 0 H0 R W 10 P2PDPU2 0 H0 R W 9 P2PDPU1 0 H0 R W 8 P2PDPU0 0 H0 R W 7 P2REN7 0 H0 R W 6 P2REN6 0 H0 R W 5 P2REN5 0 H0 R W 4 P2REN4 0 H0 R W 3 P2REN3 0 H0 R W 2 P2REN2 0 H0 R W 1 P2REN1 0 H0 R W 0 P2REN0 0 H0 R W 0x0020 0226 P2INTF P2 Port Interrupt Flag Register 15 8 0x00 R 7 P2IF7 0 H0 R W Cleared by writing 1 6 P2IF6 0 H0 R W 5 P2IF5 0...

Page 375: ... Port Function Select Register 15 14 P27MUX 1 0 0x0 H0 R W 13 12 P26MUX 1 0 0x0 H0 R W 11 10 P25MUX 1 0 0x0 H0 R W 9 8 P24MUX 1 0 0x0 H0 R W 7 6 P23MUX 1 0 0x0 H0 R W 5 4 P22MUX 1 0 0x0 H0 R W 3 2 P21MUX 1 0 0x0 H0 R W 1 0 P20MUX 1 0 0x0 H0 R W 0x0020 0230 P3DAT P3 Port Data Register 15 P3OUT7 0 H0 R W 14 P3OUT6 0 H0 R W 13 P3OUT5 0 H0 R W 12 P3OUT4 0 H0 R W 11 P3OUT3 0 H0 R W 10 P3OUT2 0 H0 R W 9...

Page 376: ...F P3 Port Interrupt Flag Register 15 8 0x00 R 7 P3IF7 0 H0 R W Cleared by writing 1 6 P3IF6 0 H0 R W 5 P3IF5 0 H0 R W 4 P3IF4 0 H0 R W 3 P3IF3 0 H0 R W 2 P3IF2 0 H0 R W 1 P3IF1 0 H0 R W 0 P3IF0 0 H0 R W 0x0020 0238 P3INTCTL P3 Port Interrupt Control Register 15 P3EDGE7 0 H0 R W 14 P3EDGE6 0 H0 R W 13 P3EDGE5 0 H0 R W 12 P3EDGE4 0 H0 R W 11 P3EDGE3 0 H0 R W 10 P3EDGE2 0 H0 R W 9 P3EDGE1 0 H0 R W 8 ...

Page 377: ...MUX 1 0 0x0 H0 R W 7 6 P33MUX 1 0 0x0 H0 R W 5 4 P32MUX 1 0 0x0 H0 R W 3 2 P31MUX 1 0 0x0 H0 R W 1 0 P30MUX 1 0 0x0 H0 R W 0x0020 0240 P4DAT P4 Port Data Register 15 P4OUT7 0 H0 R W 14 P4OUT6 0 H0 R W 13 P4OUT5 0 H0 R W 12 P4OUT4 0 H0 R W 11 P4OUT3 0 H0 R W 10 P4OUT2 0 H0 R W 9 P4OUT1 0 H0 R W 8 P4OUT0 0 H0 R W 7 P4IN7 0 H0 R 6 P4IN6 0 H0 R 5 P4IN5 0 H0 R 4 P4IN4 0 H0 R 3 P4IN3 0 H0 R 2 P4IN2 0 H0...

Page 378: ...F P4 Port Interrupt Flag Register 15 8 0x00 R 7 P4IF7 0 H0 R W Cleared by writing 1 6 P4IF6 0 H0 R W 5 P4IF5 0 H0 R W 4 P4IF4 0 H0 R W 3 P4IF3 0 H0 R W 2 P4IF2 0 H0 R W 1 P4IF1 0 H0 R W 0 P4IF0 0 H0 R W 0x0020 0248 P4INTCTL P4 Port Interrupt Control Register 15 P4EDGE7 0 H0 R W 14 P4EDGE6 0 H0 R W 13 P4EDGE5 0 H0 R W 12 P4EDGE4 0 H0 R W 11 P4EDGE3 0 H0 R W 10 P4EDGE2 0 H0 R W 9 P4EDGE1 0 H0 R W 8 ...

Page 379: ...MUX 1 0 0x0 H0 R W 7 6 P43MUX 1 0 0x0 H0 R W 5 4 P42MUX 1 0 0x0 H0 R W 3 2 P41MUX 1 0 0x0 H0 R W 1 0 P40MUX 1 0 0x0 H0 R W 0x0020 0250 P5DAT P5 Port Data Register 15 P5OUT7 0 H0 R W 14 P5OUT6 0 H0 R W 13 P5OUT5 0 H0 R W 12 P5OUT4 0 H0 R W 11 P5OUT3 0 H0 R W 10 P5OUT2 0 H0 R W 9 P5OUT1 0 H0 R W 8 P5OUT0 0 H0 R W 7 P5IN7 0 H0 R 6 P5IN6 0 H0 R 5 P5IN5 0 H0 R 4 P5IN4 0 H0 R 3 P5IN3 0 H0 R 2 P5IN2 0 H0...

Page 380: ...F P5 Port Interrupt Flag Register 15 8 0x00 R 7 P5IF7 0 H0 R W Cleared by writing 1 6 P5IF6 0 H0 R W 5 P5IF5 0 H0 R W 4 P5IF4 0 H0 R W 3 P5IF3 0 H0 R W 2 P5IF2 0 H0 R W 1 P5IF1 0 H0 R W 0 P5IF0 0 H0 R W 0x0020 0258 P5INTCTL P5 Port Interrupt Control Register 15 P5EDGE7 0 H0 R W 14 P5EDGE6 0 H0 R W 13 P5EDGE5 0 H0 R W 12 P5EDGE4 0 H0 R W 11 P5EDGE3 0 H0 R W 10 P5EDGE2 0 H0 R W 9 P5EDGE1 0 H0 R W 8 ...

Page 381: ...MUX 1 0 0x0 H0 R W 7 6 P53MUX 1 0 0x0 H0 R W 5 4 P52MUX 1 0 0x0 H0 R W 3 2 P51MUX 1 0 0x0 H0 R W 1 0 P50MUX 1 0 0x0 H0 R W 0x0020 0260 P6DAT P6 Port Data Register 15 P6OUT7 0 H0 R W 14 P6OUT6 0 H0 R W 13 P6OUT5 0 H0 R W 12 P6OUT4 0 H0 R W 11 P6OUT3 0 H0 R W 10 P6OUT2 0 H0 R W 9 P6OUT1 0 H0 R W 8 P6OUT0 0 H0 R W 7 P6IN7 0 H0 R 6 P6IN6 0 H0 R 5 P6IN5 0 H0 R 4 P6IN4 0 H0 R 3 P6IN3 0 H0 R 2 P6IN2 0 H0...

Page 382: ...F P6 Port Interrupt Flag Register 15 8 0x00 R 7 P6IF7 0 H0 R W Cleared by writing 1 6 P6IF6 0 H0 R W 5 P6IF5 0 H0 R W 4 P6IF4 0 H0 R W 3 P6IF3 0 H0 R W 2 P6IF2 0 H0 R W 1 P6IF1 0 H0 R W 0 P6IF0 0 H0 R W 0x0020 0268 P6INTCTL P6 Port Interrupt Control Register 15 P6EDGE7 0 H0 R W 14 P6EDGE6 0 H0 R W 13 P6EDGE5 0 H0 R W 12 P6EDGE4 0 H0 R W 11 P6EDGE3 0 H0 R W 10 P6EDGE2 0 H0 R W 9 P6EDGE1 0 H0 R W 8 ...

Page 383: ...MUX 1 0 0x0 H0 R W 7 6 P63MUX 1 0 0x0 H0 R W 5 4 P62MUX 1 0 0x0 H0 R W 3 2 P61MUX 1 0 0x0 H0 R W 1 0 P60MUX 1 0 0x0 H0 R W 0x0020 0270 P7DAT P7 Port Data Register 15 P7OUT7 0 H0 R W 14 P7OUT6 0 H0 R W 13 P7OUT5 0 H0 R W 12 P7OUT4 0 H0 R W 11 P7OUT3 0 H0 R W 10 P7OUT2 0 H0 R W 9 P7OUT1 0 H0 R W 8 P7OUT0 0 H0 R W 7 P7IN7 0 H0 R 6 P7IN6 0 H0 R 5 P7IN5 0 H0 R 4 P7IN4 0 H0 R 3 P7IN3 0 H0 R 2 P7IN2 0 H0...

Page 384: ...F P7 Port Interrupt Flag Register 15 8 0x00 R 7 P7IF7 0 H0 R W Cleared by writing 1 6 P7IF6 0 H0 R W 5 P7IF5 0 H0 R W 4 P7IF4 0 H0 R W 3 P7IF3 0 H0 R W 2 P7IF2 0 H0 R W 1 P7IF1 0 H0 R W 0 P7IF0 0 H0 R W 0x0020 0278 P7INTCTL P7 Port Interrupt Control Register 15 P7EDGE7 0 H0 R W 14 P7EDGE6 0 H0 R W 13 P7EDGE5 0 H0 R W 12 P7EDGE4 0 H0 R W 11 P7EDGE3 0 H0 R W 10 P7EDGE2 0 H0 R W 9 P7EDGE1 0 H0 R W 8 ...

Page 385: ...MUX 1 0 0x0 H0 R W 7 6 P73MUX 1 0 0x0 H0 R W 5 4 P72MUX 1 0 0x0 H0 R W 3 2 P71MUX 1 0 0x0 H0 R W 1 0 P70MUX 1 0 0x0 H0 R W 0x0020 0280 P8DAT P8 Port Data Register 15 P8OUT7 0 H0 R W 14 P8OUT6 0 H0 R W 13 P8OUT5 0 H0 R W 12 P8OUT4 0 H0 R W 11 P8OUT3 0 H0 R W 10 P8OUT2 0 H0 R W 9 P8OUT1 0 H0 R W 8 P8OUT0 0 H0 R W 7 P8IN7 0 H0 R 6 P8IN6 0 H0 R 5 P8IN5 0 H0 R 4 P8IN4 0 H0 R 3 P8IN3 0 H0 R 2 P8IN2 0 H0...

Page 386: ...F P8 Port Interrupt Flag Register 15 8 0x00 R 7 P8IF7 0 H0 R W Cleared by writing 1 6 P8IF6 0 H0 R W 5 P8IF5 0 H0 R W 4 P8IF4 0 H0 R W 3 P8IF3 0 H0 R W 2 P8IF2 0 H0 R W 1 P8IF1 0 H0 R W 0 P8IF0 0 H0 R W 0x0020 0288 P8INTCTL P8 Port Interrupt Control Register 15 P8EDGE7 0 H0 R W 14 P8EDGE6 0 H0 R W 13 P8EDGE5 0 H0 R W 12 P8EDGE4 0 H0 R W 11 P8EDGE3 0 H0 R W 10 P8EDGE2 0 H0 R W 9 P8EDGE1 0 H0 R W 8 ...

Page 387: ... 0 0x0 H0 R W 11 10 P85MUX 1 0 0x0 H0 R W 9 8 P84MUX 1 0 0x0 H0 R W 7 6 P83MUX 1 0 0x0 H0 R W 5 4 P82MUX 1 0 0x0 H0 R W 3 2 P81MUX 1 0 0x0 H0 R W 1 0 P80MUX 1 0 0x0 H0 R W 0x0020 0290 P9DAT P9 Port Data Register 15 14 0x0 R 13 P9OUT5 0 H0 R W 12 P9OUT4 0 H0 R W 11 P9OUT3 0 H0 R W 10 P9OUT2 0 H0 R W 9 P9OUT1 0 H0 R W 8 P9OUT0 0 H0 R W 7 6 0x0 R 5 P9IN5 0 H0 R 4 P9IN4 0 H0 R 3 P9IN3 0 H0 R 2 P9IN2 0...

Page 388: ... 0 H0 R W Cleared by writing 1 4 P9IF4 0 H0 R W 3 P9IF3 0 H0 R W 2 P9IF2 0 H0 R W 1 P9IF1 0 H0 R W 0 P9IF0 0 H0 R W 0x0020 0298 P9INTCTL P9 Port Interrupt Control Register 15 14 0x0 R 13 P9EDGE5 0 H0 R W 12 P9EDGE4 0 H0 R W 11 P9EDGE3 0 H0 R W 10 P9EDGE2 0 H0 R W 9 P9EDGE1 0 H0 R W 8 P9EDGE0 0 H0 R W 7 6 0x0 R 5 P9IE5 0 H0 R W 4 P9IE4 0 H0 R W 3 P9IE3 0 H0 R W 2 P9IE2 0 H0 R W 1 P9IE1 0 H0 R W 0 P...

Page 389: ...PAOUT1 0 H0 R W 8 PAOUT0 0 H0 R W 7 0 R 6 PAIN6 0 H0 R 5 PAIN5 0 H0 R 4 PAIN4 0 H0 R 3 PAIN3 0 H0 R 2 PAIN2 0 H0 R 1 PAIN1 0 H0 R 0 PAIN0 0 H0 R 0x0020 02a2 PAIOEN Pa Port Enable Register 15 0 R 14 PAIEN6 0 H0 R W 13 PAIEN5 0 H0 R W 12 PAIEN4 0 H0 R W 11 PAIEN3 0 H0 R W 10 PAIEN2 0 H0 R W 9 PAIEN1 0 H0 R W 8 PAIEN0 0 H0 R W 7 0 R 6 PAOEN6 0 H0 R W 5 PAOEN5 0 H0 R W 4 PAOEN4 0 H0 R W 3 PAOEN3 0 H0 ...

Page 390: ...EDGE0 0 H0 R W 7 0 R 6 PAIE6 0 H0 R W 5 PAIE5 0 H0 R W 4 PAIE4 0 H0 R W 3 PAIE3 0 H0 R W 2 PAIE2 0 H0 R W 1 PAIE1 0 H0 R W 0 PAIE0 0 H0 R W 0x0020 02aa PACHATEN Pa Port Chattering Filter Enable Register 15 8 0x00 R 7 0 R 6 PACHATEN6 0 H0 R W 5 PACHATEN5 0 H0 R W 4 PACHATEN4 0 H0 R W 3 PACHATEN3 0 H0 R W 2 PACHATEN2 0 H0 R W 1 PACHATEN1 0 H0 R W 0 PACHATEN0 0 H0 R W 0x0020 02ac PAMODSEL Pa Port Mod...

Page 391: ...0 H0 R W 7 6 0x0 R 5 PDOEN5 0 H0 R W 4 PDOEN4 0 H0 R W 3 PDOEN3 0 H0 R W 2 PDOEN2 0 H0 R W 1 PDOEN1 0 H0 R W 0 PDOEN0 0 H0 R W 0x0020 02d4 PDRCTL Pd Port Pull up down Control Register 15 14 0x0 R 13 PDPDPU5 0 H0 R W 12 PDPDPU4 0 H0 R W 11 PDPDPU3 0 H0 R W 10 PDPDPU2 0 H0 R W 9 PDPDPU1 0 H0 R W 8 PDPDPU0 0 H0 R W 7 6 0x0 R 5 PDREN5 0 H0 R W 4 PDREN4 0 H0 R W 3 PDREN3 0 H0 R W 2 PDREN2 0 H0 R W 1 PD...

Page 392: ...niversal Port Multiplexer Setting Register 15 13 P03PPFNC 2 0 0x0 H0 R W 12 11 P03PERICH 1 0 0x0 H0 R W 10 8 P03PERISEL 2 0 0x0 H0 R W 7 5 P02PPFNC 2 0 0x0 H0 R W 4 3 P02PERICH 1 0 0x0 H0 R W 2 0 P02PERISEL 2 0 0x0 H0 R W 0x0020 0304 UPMUXP0MUX2 P04 05 Universal Port Multiplexer Setting Register 15 13 P05PPFNC 2 0 0x0 H0 R W 12 11 P05PERICH 1 0 0x0 H0 R W 10 8 P05PERISEL 2 0 0x0 H0 R W 7 5 P04PPFN...

Page 393: ...P22PPFNC 2 0 0x0 H0 R W 4 3 P22PERICH 1 0 0x0 H0 R W 2 0 P22PERISEL 2 0 0x0 H0 R W 0x0020 0314 UPMUXP2MUX2 P24 25 Universal Port Multiplexer Setting Register 15 13 P25PPFNC 2 0 0x0 H0 R W 12 11 P25PERICH 1 0 0x0 H0 R W 10 8 P25PERISEL 2 0 0x0 H0 R W 7 5 P24PPFNC 2 0 0x0 H0 R W 4 3 P24PERICH 1 0 0x0 H0 R W 2 0 P24PERISEL 2 0 0x0 H0 R W 0x0020 0316 UPMUXP2MUX3 P26 27 Universal Port Multiplexer Setti...

Page 394: ... W 10 BRDIV 0 H0 R W 9 INVRX 0 H0 R W 8 INVTX 0 H0 R W 7 0 R 6 PUEN 0 H0 R W 5 OUTMD 0 H0 R W 4 IRMD 0 H0 R W 3 CHLN 0 H0 R W 2 PREN 0 H0 R W 1 PRMD 0 H0 R W 0 STPB 0 H0 R W 0x0020 0384 UART3_0BR UART3 Ch 0 Baud Rate Register 15 12 0x0 R 11 8 FMD 3 0 0x0 H0 R W 7 0 BRT 7 0 0x00 H0 R W 0x0020 0386 UART3_0CTL UART3 Ch 0 Control Register 15 8 0x00 R 7 2 0x00 R 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W 0x002...

Page 395: ...AWF UART3 Ch 0 Carrier Waveform Register 15 8 0x00 R 7 0 CRPER 7 0 0x00 H0 R W 0x0020 03a0 0x0020 03ac 16 bit Timer T16 Ch 1 Address Register name Bit Bit name Initial Reset R W Remarks 0x0020 03a0 T16_1CLK T16 Ch 1 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R W 7 4 CLKDIV 3 0 0x0 H0 R W 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R W 0x0020 03a2 T16_1MOD T16 Ch 1 Mode Register 15 8 0x00 R 7 1 0x00 R 0 T...

Page 396: ...7 BSY 0 H0 R 6 4 0x0 R 3 OEIF 0 H0 S0 R W Cleared by writing 1 2 TENDIF 0 H0 S0 R W 1 RBFIF 0 H0 S0 R Cleared by reading the SPIA_0RXD register 0 TBEIF 1 H0 S0 R Cleared by writing to the SPIA_0TXD register 0x0020 03ba SPIA_0INTE SPIA Ch 0 Interrupt Enable Register 15 8 0x00 R 7 4 0x0 R 3 OEIE 0 H0 R W 2 TENDIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W 0x0020 03bc SPIA_0TBEDMAEN SPIA Ch 0 Transmi...

Page 397: ...XD 7 0 0x00 H0 R 0x0020 03d0 I2C_0INTF I2C Ch 0 Status and Interrupt Flag Register 15 13 0x0 R 12 SDALOW 0 H0 R 11 SCLLOW 0 H0 R 10 BSY 0 H0 S0 R 9 TR 0 H0 R 8 0 R 7 BYTEENDIF 0 H0 S0 R W Cleared by writing 1 6 GCIF 0 H0 S0 R W 5 NACKIF 0 H0 S0 R W 4 STOPIF 0 H0 S0 R W 3 STARTIF 0 H0 S0 R W 2 ERRIF 0 H0 S0 R W 1 RBFIF 0 H0 S0 R Cleared by reading the I2C_0RXD register 0 TBEIF 0 H0 S0 R Cleared by ...

Page 398: ...Register 15 0 TC 15 0 0x0000 H0 R 0x0020 0408 T16B_0CS T16B Ch 0 Counter Status Register 15 8 0x00 R 7 6 0x0 R 5 CAPI3 0 H0 R 4 CAPI2 0 H0 R 3 CAPI1 0 H0 R 2 CAPI0 0 H0 R 1 UP_DOWN 1 H0 R 0 BSY 0 H0 R 0x0020 040a T16B_0INTF T16B Ch 0 Interrupt Flag Register 15 10 0x00 R 9 CAPOW3IF 0 H0 R W Cleared by writing 1 8 CMPCAP3IF 0 H0 R W 7 CAPOW2IF 0 H0 R W 6 CMPCAP2IF 0 H0 R W 5 CAPOW1IF 0 H0 R W 4 CMPC...

Page 399: ... Control Register 15 SCS 0 H0 R W 14 12 CBUFMD 2 0 0x0 H0 R W 11 10 CAPIS 1 0 0x0 H0 R W 9 8 CAPTRG 1 0 0x0 H0 R W 7 0 R 6 TOUTMT 0 H0 R W 5 TOUTO 0 H0 R W 4 2 TOUTMD 2 0 0x0 H0 R W 1 TOUTINV 0 H0 R W 0 CCMD 0 H0 R W 0x0020 041a T16B_0CCR1 T16B Ch 0 Compare Capture 1 Data Register 15 0 CC 15 0 0x0000 H0 R W 0x0020 041c T16B_0CC1DMAEN T16B Ch 0 Compare Capture 1 DMA Request Enable Register 15 8 0x0...

Page 400: ...ter 15 8 0x00 R 7 4 0x0 R 3 0 CC3DMAEN 3 0 0x0 H0 R W 0x0020 0440 0x0020 046c 16 bit PWM Timer T16B Ch 1 Address Register name Bit Bit name Initial Reset R W Remarks 0x0020 0440 T16B_1CLK T16B Ch 1 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R W 7 4 CLKDIV 3 0 0x0 H0 R W 3 0 R 2 0 CLKSRC 2 0 0x0 H0 R W 0x0020 0442 T16B_1CTL T16B Ch 1 Counter Control Register 15 9 0x00 R 8 MAXBSY 0 H0 R 7 6 0x0...

Page 401: ... T16B_1MZDMAEN T16B Ch 1 Counter Max Zero DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 MZDMAEN 3 0 0x0 H0 R W 0x0020 0450 T16B_1CCCTL0 T16B Ch 1 Compare Capture 0 Control Register 15 SCS 0 H0 R W 14 12 CBUFMD 2 0 0x0 H0 R W 11 10 CAPIS 1 0 0x0 H0 R W 9 8 CAPTRG 1 0 0x0 H0 R W 7 0 R 6 TOUTMT 0 H0 R W 5 TOUTO 0 H0 R W 4 2 TOUTMD 2 0 0x0 H0 R W 1 TOUTINV 0 H0 R W 0 CCMD 0 H0 R W 0x0020 0452 ...

Page 402: ...0x0 R 3 0 CC2DMAEN 3 0 0x0 H0 R W 0x0020 0468 T16B_1CCCTL3 T16B Ch 1 Compare Capture 3 Control Register 15 SCS 0 H0 R W 14 12 CBUFMD 2 0 0x0 H0 R W 11 10 CAPIS 1 0 0x0 H0 R W 9 8 CAPTRG 1 0 0x0 H0 R W 7 0 R 6 TOUTMT 0 H0 R W 5 TOUTO 0 H0 R W 4 2 TOUTMD 2 0 0x0 H0 R W 1 TOUTINV 0 H0 R W 0 CCMD 0 H0 R W 0x0020 046a T16B_1CCR3 T16B Ch 1 Compare Capture 3 Data Register 15 0 CC 15 0 0x0000 H0 R W 0x002...

Page 403: ...8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W 0x0020 04a4 T16_4CTL T16 Ch 4 Control Register 15 9 0x00 R 8 PRUN 0 H0 R W 7 2 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x0020 04a6 T16_4TR T16 Ch 4 Reload Data Register 15 0 TR 15 0 0xffff H0 R W 0x0020 04a8 T16_4TC T16 Ch 4 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x0020 04aa T16_4INTF T16 Ch 4 Interrupt Flag Register 15 8 0x00 R 7 1 0x00 R 0 UFIF 0 H0 ...

Page 404: ... MST 0 H0 R W 0x0020 04d2 SPIA_2CTL SPIA Ch 2 Control Register 15 8 0x00 R 7 2 0x00 R 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W 0x0020 04d4 SPIA_2TXD SPIA Ch 2 Transmit Data Register 15 0 TXD 15 0 0x0000 H0 R W 0x0020 04d6 SPIA_2RXD SPIA Ch 2 Receive Data Register 15 0 RXD 15 0 0x0000 H0 R 0x0020 04d8 SPIA_2INTF SPIA Ch 2 Interrupt Flag Register 15 8 0x00 R 7 BSY 0 H0 R 6 4 0x0 R 3 OEIF 0 H0 S0 R W Clear...

Page 405: ...7 0 0x00 H0 R W 0x0020 0606 UART3_1CTL UART3 Ch 1 Control Register 15 8 0x00 R 7 2 0x00 R 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W 0x0020 0608 UART3_1TXD UART3 Ch 1 Trans mit Data Register 15 8 0x00 R 7 0 TXD 7 0 0x00 H0 R W 0x0020 060a UART3_1RXD UART3 Ch 1 Receive Data Register 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R 0x0020 060c UART3_1INTF UART3 Ch 1 Status and Interrupt Flag Register 15 10 0x00 R 9 RBSY 0...

Page 406: ...itial Reset R W Remarks 0x0020 0620 UART3_2CLK UART3 Ch 2 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R W 7 6 0x0 R 5 4 CLKDIV 1 0 0x0 H0 R W 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R W 0x0020 0622 UART3_2MOD UART3 Ch 2 Mode Register 15 13 0x00 R 12 PECAR 0 H0 R W 11 CAREN 0 H0 R W 10 BRDIV 0 H0 R W 9 INVRX 0 H0 R W 8 INVTX 0 H0 R W 7 0 R 6 PUEN 0 H0 R W 5 OUTMD 0 H0 R W 4 IRMD 0 H0 R W 3 CHLN 0 H0 R ...

Page 407: ...W 0 TBEIE 0 H0 R W 0x0020 0630 UART3_2 TBEDMAEN UART3 Ch 2 Transmit Buffer Empty DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 TBEDMAEN 3 0 0x0 H0 R W 0x0020 0632 UART3_2 RB1FDMAEN UART3 Ch 2 Receive Buffer One Byte Full DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 RB1FDMAEN 3 0 0x0 H0 R W 0x0020 0634 UART3_2CAWF UART3 Ch 2 Carrier Waveform Register 15 8 0x00 R 7 0 CRPER 7 0 0x00 ...

Page 408: ...IA Ch 1 Control Register 15 8 0x00 R 7 2 0x00 R 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W 0x0020 0674 SPIA_1TXD SPIA Ch 1 Transmit Data Register 15 0 TXD 15 0 0x0000 H0 R W 0x0020 0676 SPIA_1RXD SPIA Ch 1 Receive Data Register 15 0 RXD 15 0 0x0000 H0 R 0x0020 0678 SPIA_1INTF SPIA Ch 1 Interrupt Flag Register 15 8 0x00 R 7 BSY 0 H0 R 6 4 0x0 R 3 OEIF 0 H0 S0 R W Cleared by writing 1 2 TENDIF 0 H0 S0 R W 1...

Page 409: ...ta Register 15 0 TC 15 0 0xffff H0 R 0x0020 068a T16_2INTF T16 Ch 2 Interrupt Flag Register 15 8 0x00 R 7 1 0x00 R 0 UFIF 0 H0 R W Cleared by writing 1 0x0020 068c T16_2INTE T16 Ch 2 Interrupt Enable Register 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W 0x0020 0690 0x0020 06a8 Quad Synchronous Serial Interface QSPI Ch 0 Address Register name Bit Bit name Initial Reset R W Remarks 0x0020 0690 QSPI_0MOD Q...

Page 410: ... Register 15 8 0x00 R 7 4 0x0 R 3 0 RBFDMAEN 3 0 0x0 H0 R W 0x0020 06a0 QSPI_0FRLDMAEN QSPI Ch 0 FIFO Data Ready DMA Request Enable Register 15 8 0x00 R 7 4 0x0 R 3 0 FRLDMAEN 3 0 0x0 H0 R W 0x0020 06a2 QSPI_0MMACFG1 QSPI Ch 0 Memory Mapped Access Con figuration Register 1 15 8 0x00 R 7 4 0x0 R 3 0 TCSH 3 0 0x0 H0 R W 0x0020 06a4 QSPI_0RMADRH QSPI Ch 0 Remap ping Start Address High Register 15 4 R...

Page 411: ...1RXD I2C Ch 1 Receive Data Register 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R 0x0020 06d0 I2C_1INTF I2C Ch 1 Status and Interrupt Flag Register 15 13 0x0 R 12 SDALOW 0 H0 R 11 SCLLOW 0 H0 R 10 BSY 0 H0 S0 R 9 TR 0 H0 R 8 0 R 7 BYTEENDIF 0 H0 S0 R W Cleared by writing 1 6 GCIF 0 H0 S0 R W 5 NACKIF 0 H0 S0 R W 4 STOPIF 0 H0 S0 R W 3 STARTIF 0 H0 S0 R W 2 ERRIF 0 H0 S0 R W 1 RBFIF 0 H0 S0 R Cleared by readin...

Page 412: ... 7 6 0x0 R 5 MST 0 H0 R W 4 TXNACK 0 H0 S0 R W 3 TXSTOP 0 H0 S0 R W 2 TXSTART 0 H0 S0 R W 1 SFTRST 0 H0 R W 0 MODEN 0 H0 R W 0x0020 06ec I2C_2TXD I2C Ch 2 Transmit Data Register 15 8 0x00 R 7 0 TXD 7 0 0x00 H0 R W 0x0020 06ee I2C_2RXD I2C Ch 2 Receive Data Register 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R 0x0020 06f0 I2C_2INTF I2C Ch 2 Status and Interrupt Flag Register 15 13 0x0 R 12 SDALOW 0 H0 R 11 SC...

Page 413: ...D 0 H0 R W 1 REMCRST 0 H0 W 0 MODEN 0 H0 R W 0x0020 0724 REMC3DBCNT REMC3 Data Bit Counter Register 15 0 DBCNT 15 0 0x0000 H0 S0 R Cleared by writing 1 to the REMC3DBCTL REMCRST bit 0x0020 0726 REMC3APLEN REMC3 Data Bit Active Pulse Length Register 15 0 APLEN 15 0 0x0000 H0 R W Writing enabled when REMC3DBCTL MODEN bit 1 0x0020 0728 REMC3DBLEN REMC3 Data Bit Length Register 15 0 DBLEN 15 0 0x0000 ...

Page 414: ... R 0 UFIF 0 H0 R W Cleared by writing 1 0x0020 078c T16_7INTE T16 Ch 7 Interrupt Enable Register 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W 0x0020 07a0 0x0020 07bc 12 bit A D Converter ADC12A Ch 0 Address Register name Bit Bit name Initial Reset R W Remarks 0x0020 07a2 ADC12A_0CTL ADC12A Ch 0 Control Register 15 0 R 14 12 ADSTAT 2 0 0x0 H0 R 11 0 R 10 BSYSTAT 0 H0 R 9 8 0x0 R 7 2 0x00 R 1 ADST 0 H0 R ...

Page 415: ...Register 3 15 8 0x00 R 7 4 0x0 R 3 0 ADCDMAEN 3 0 0x0 H0 R W 0x0020 07b4 ADC12A_0DMAEN4 ADC12A Ch 0 DMA Request Enable Register 4 15 8 0x00 R 7 4 0x0 R 3 0 ADCDMAEN 3 0 0x0 H0 R W 0x0020 07b6 ADC12A_0DMAEN5 ADC12A Ch 0 DMA Request Enable Register 5 15 8 0x00 R 7 4 0x0 R 3 0 ADCDMAEN 3 0 0x0 H0 R W 0x0020 07b8 ADC12A_0DMAEN6 ADC12A Ch 0 DMA Request Enable Register 6 15 8 0x00 R 7 4 0x0 R 3 0 ADCDMA...

Page 416: ...writing 1 3 OVMCIF 0 H0 R W 2 ESENBIF 0 H0 R W 1 ESENAIF 0 H0 R W 0 EREFIF 0 H0 R W 0x0020 0850 RFC_0INTE RFC Ch 0 Interrupt Enable Register 15 8 0x00 R 7 5 0x0 R 4 OVTCIE 0 H0 R W 3 OVMCIE 0 H0 R W 2 ESENBIE 0 H0 R W 1 ESENAIE 0 H0 R W 0 EREFIE 0 H0 R W 0x0020 0860 0x0020 086a Sound DAC SDAC Address Register name Bit Bit name Initial Reset R W Remarks 0x0020 0860 SDACCLK SDAC Clock Control Regist...

Page 417: ...00 DMACSTAT DMAC Status Register 31 24 0x00 R 23 21 0x0 R 20 16 CHNLS 4 0 H0 R Number of channels implemented 1 15 8 0x00 R 7 4 STATE 3 0 0x0 H0 R 3 1 0x0 R 0 MSTENSTAT 0 H0 R 0x0020 1004 DMACCFG DMAC Configuration Register 31 24 0x00 R 23 16 0x00 R 15 8 0x00 R 7 1 0x00 R 0 MSTEN W 0x0020 1008 DMACCPTR DMAC Control Data Base Pointer Register 31 7 CPTR 31 7 0x000 0000 H0 R W 6 0 CPTR 6 0 0x00 H0 R ...

Page 418: ... R 23 16 R 15 8 R 7 4 R 3 0 PRCLR 3 0 W 0x0020 104c DMACERRIF DMAC Error Interrupt Flag Register 31 24 0x00 R 23 16 0x00 R 15 8 0x00 R 7 1 0x00 R 0 ERRIF 0 H0 R W Cleared by writing 1 0x0020 2000 DMACENDIF DMAC Transfer Completion Interrupt Flag Register 31 24 0x00 R 23 16 0x00 R 15 8 0x00 R 7 4 0x0 R 3 0 ENDIF 3 0 0x0 H0 R W Cleared by writing 1 0x0020 2008 DMACENDIESET DMAC Transfer Completion I...

Page 419: ... REGMODE 1 0 bits to 0x3 economy mode or 0x0 automatic mode before placing the CPU into SLEEP mode CLGOSC IOSCSLPC OSC1SLPC OSC3SLPC EXOSCSLPC bits of the clock generator Setting the CLGOSC IOSCSLPC OSC1SLPC OSC3SLPC or EXOSCSLPC bit of the clock generator to 0 disables the oscillator circuit stop control when the CPU enters SLEEP mode To stop the oscillator circuits during SLEEP mode set these bi...

Page 420: ...consumption Using lower OSC3 external gate and drain capacitances decreases current consumption Using a resonator with lower CL value decreases current consumption However these configurations may reduce the oscillation margin and increase the frequency error therefore be sure to perform matching evaluation using the actual printed circuit board B 2 Other Power Saving Methods Supply voltage detect...

Page 421: ... where possible At minimum shield the area at least 5 mm around the above pins and wiring Even after implementing these precautions avoid configuring digital signal lines in parallel as described in 2 above Avoid crossing even on discrete layers except for lines carrying signals with low switching frequencies 4 After implementing these precautions check the FOUT pin output clock waveform by runnin...

Page 422: ... used the OSC1 and OSC2 pins should be left open If the OSC3 crystal ceramic oscillator circuit or EXOSC input circuit is not used the pin should be configured as a general purpose I O port The control registers should be fixed at the initial status disabled Miscellaneous Minor variations over time may result in electrical damage arising from disturbances in the form of voltages exceeding the abso...

Page 423: ...sideration For the recommended patterns on the circuit board see Mounting Precautions in Appendix Noise Measures for Interrupt Input Pins This product is able to generate a port input interrupt when the input signal changes The interrupt is generated when an input signal edge is detected therefore an interrupt may occur if the signal changes due to extraneous noise To prevent occurrence of unexpec...

Page 424: ...1 3 2 1 The I O and initial state of the SDACOUT_P P50 and SDACOUT_N P51 pins were corrected P2 16 AP A 1 Modified the CLG System Clock Control Register table The CLGSCLK CLKDIV 1 0 bit initial value was corrected P5 1 Modified Table 5 2 1 The port numbers described in the port interrupts were corrected P7 23 Modified Table 7 7 5 2 The VREFA0 pin function was added to P40 P7 33 Modified Table 7 7 ...

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Epson Buzzer S1C31D51, Technical Manual

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