15 Quad Synchronous Serial Interface (QSPI)
S1C31D50/D51 TECHNICAL MANUAL
Seiko Epson Corporation
15-3
(Rev. 2.00)
#QSPISSn
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
QSPICLKn
#QSPISS
QSDIO3
QSDIO2
QSDIO1
QSDIO0
QSPICLK
S1C31 QSPI
(memory mapped
access mode)
External QSPI
slave device
Figure 15.2.2.1 Connections between QSPI in Memory Mapped Access Mode
and an External QSPI Slave Device
#SPISS
SDO
SDI
SPICK
#SPISS
SDO
SDI
SPICK
#SPISS
SDO
SDI
SPICK
External single-I/O
SPI slave devices
#QSPISSn
Px1
Px2
QSDIOn1
QSDIOn0
QSPICLKn
S1C31 QSPI
(register access
master mode)
Figure 15.2.2.2 Connections between QSPI in Register Access Master Mode
and External Single-I/O SPI (Legacy SPI) Slave Devices
#SPISS
SDIO1
SDIO0
SPICK
#SPISS
SDIO1
SDIO0
SPICK
#SPISS
SDIO1
SDIO0
SPICK
External dual-I/O
SPI slave devices
#QSPISSn
Px1
Px2
QSDIOn1
QSDIOn0
QSPICLKn
S1C31 QSPI
(register access
master mode)
Figure 15.2.2.3 Connections between QSPI in Register Access Master Mode
and External Dual-I/O SPI Slave Devices