Emerson COM Express Carrier, Design Manual

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Page 64 of 103 COM Express Carrier Type 2
Design Guide
11.3.2 PCI Bus Slot Example
Figure 22 PCI Slot 5 V, 32-bit / 33 MHz Schematic
11.4 Layout Consideration
The PCI bus should be routed with 55 ohm, single-ended signals. The bus may be referenced to ground
(preferred), or to a well-bypassed power plane, or a combination of the two. Point-to-point (daisy
chain) routing is preferred, although stubs up to 1.5 in may be acceptable. Length-matching is not
required. See Section 20.4.1 'PCI Trace Routing Guidelines' for a summary of trace routing parameters
and guidelines.
The PCI clock should be routed carefully. The COM Express specification allows 1.6 ns +/- 0.1 ns for the
propagation delay of the PCI clock from the module pin to the destination pin of the PCI device. Using a
typical propagation delay value of 180 ps/in, this works out to 8.88 inches of carrier board trace for a
device-down application. For device-up situations, the PCI Local Bus specification allows 2.5 inches of
clock trace on the slot card. This is deducted from the 8.88 inches, yielding 6.38 inches.
PCI clock signals should be routed as a single ended trace with a trace impedance of 55 ohms. To
reduce EMI, a single ground referenced internal layer is recommended. The clock traces should be