COM Express Carrier Type 2
Page 69 of 103
Design Guide
Pull-up resistors are required on the keyboard and mouse data and clock lines, if used.
Place series resistor near CEX connector or use buffer for more than two LPC loads.
Connect to VCC_5V0 if the system does not provide standby power.
12.3
Layout Consideration
12.3.1
General Signals
LPC signals are similar to PCI signals and may be treated similarly. Route the LPC bus as 55 ohm,single-
ended signals. The bus may be referenced to ground (preferred), or to a well-bypassed power plane or
a combination of the two. Point-to-point (daisy-chain) routing is preferred, although stubs up to 1.5
inches may be acceptable. Length-matching is not required. See Section 20.4.3 'LPC Trace Routing
Guidelines' for further information.
12.3.2
Bus Clock Routing
The LPC bus clock is similar to the PCI bus clock and should be treated similarly. The COM Express
specification allows 1.6 ns ±0.1 ns for the propagation delay of the LPC clock from the module pin to
the LPC device destination pin. Using a typical propagation delay value of 180 ps/in, this works out to
8.88 inches of carrier board trace for a device-down application. For device-up situations, 2.5 inches of
clock trace are assumed to be on the LPC slot card (by analogy to the PCI specification). This is
deducted from the 8.88 inches, yielding 6.38 inches. On a carrier board with a small form factor,
serpentine clock traces may be required to meet the clock length requirement. Route the LPC clock as
a single-ended, 55 ohm trace, with generous clearance to other traces and to itself. A continuous
ground-plane reference is recommended. Routing the clock on a single ground referenced internal
layer is preferred to reduce EMI.
The COM Express specification brings a single LPC clock out of the module. If there are multiple LPC
targets on the carrier board design, then a zero delay clock buffer is recommended. The buffer
recommendation is the same as the one shown for the PCI clock above. This provides a separate copy
of the LPC clock to each target. The overall delay from the module LPC clock pin to the target LPC
device clock pin should be 1.6 ns.
Summary of Contents for COM Express Carrier
Page 1: ...COM Express Carrier Type 2 Design Guide October 2009 Confidential and Proprietary ...
Page 17: ...COM Express Carrier Type 2 Page 17 of 103 Design Guide Figure 1 COM Express Type 2 Connector ...
Page 36: ...Page 36 of 103 COM Express Carrier Type 2 Design Guide Table 5 SDVO Layout Requirement ...
