Emerson COM Express Carrier Design Manual Download Page 29

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COM Express Carrier Type 2

Page 29 of 103

Design Guide

PCIe Graphics (PCIe 16—31) and SDVO

The COM Express PCIe Graphics (PEG) port is comprised of COM Express PCIe lanes 16—32. The primary

use of this set of signals is to interface to off-module graphics controllers or cards.

The COM Express Specification also allows these pins to be shared with a set of module-generated
SDVO lines.

If the PEG interface is not used for an external graphics card or SDVO, it may be possible to use these

PCIe lanes for other carrier board PCIe devices. The details of this usage are module and module

chipset dependent. Operation in an x1 link is also supported. Wider links (x2, x4, x8, x16) are chipset

dependent. For more details, see the corresponding COM Express module user’s manual.

The COM Express Specification defines a fill order for this set of PCIe lanes. Larger link widths go to the

lower lanes. For more details, see the COM Express Specification.

These PCIE lanes support polarity inversion and lane reversal to make it convenient for routing.

To activate the lane reversal mode for the PEG port, the COM Express Specification defines an active

low signal PEG_LANE_RV#, which can be found on the module’s connector at row D, pin D54. This pin
is strapped low on the carrier board to invoke lane reversal mode.

Check the specified module if it supports SDVO lane reversal.

Table 4 PEG Signal Description

Signal Pin

Description

I/O

Comment

PEG_RX0-

C52

C53

PEG Channel 0, Receive

Input Differential Pair

I PCIE

Shared with:

SDVO_
SDVO_TVCLKIN-

PEG_TX0-

D52

D53

PEG Channel 0, Transmit

Output Differentail Pair

O PCIE

Shared with:

SD
SDVOB_RED-

PEG_RX1-

C55

C56

PEG Channel 1, Receive

Input Differential Pair

I PCIE

Shared with:

SD
SDVOB_INT-

PEG_TX1-

D55

D56

PEG Channel 1, Transmit

Output Differential Pair

O PCIE

Shared with:

SD
SDVOB_GRN-

PEG_RX2-

C58

C59

PEG Channel 2, Receive

Input Differential Pair

I PCIE

Shared with:

SDVOB_F
SDVOB_ FLDSTALL-

D58

PEG Channel 2, Transmit

O PCIE

Shared with:

Summary of Contents for COM Express Carrier

Page 1: ...COM Express Carrier Type 2 Design Guide October 2009 Confidential and Proprietary ...

Page 2: ...al Proprietary and is subject to Emerson standards for controlling proprietary material Use of this material is restricted to Emerson employees with a need to know and others with a need to know that are subject to a confidentiality agreement Information must be kept out of view of persons not having a need to know When printed information is not in use it must be stored in a locked cabinet desk o...

Page 3: ...d Alignment 16 3 PCI Express Lanes 0 5 18 3 1 Introduction 18 3 2 COM Express PCIe Signals Definition 18 3 3 PCIE Feature Support 20 3 3 1 Polarity Inversion 20 3 3 2 Lane Reversal 20 3 4 PCIE Schematic Example 20 3 4 1 PCIE Reference Clock 20 3 4 2 PCIE Signals AC Couple 22 3 4 3 X1 Slot Example 23 3 4 4 x4 Slot 24 3 4 5 Express Card Example 24 3 4 6 PCI Express Mini Card 26 3 5 PCI Express Signa...

Page 4: ...aphic Card 33 4 2 2 SDVO to DVI Inverter 34 4 3 Routing Consideration 35 5 LAN 37 5 1 LAN Signals Definition 37 5 2 Emerson LAN LED Definition 38 5 3 Example Schematic 38 5 4 Layout Consideration 38 6 USB Ports 39 6 1 USB Carrier Signals Definition 39 6 2 Reference Schematic 40 6 3 Layout Consideration 40 7 SATA 41 7 1 SATA Signals Definition 42 7 2 Reference Schematic 43 7 3 Layout Consideration ...

Page 5: ...nals Definition 51 9 2 Reference Schematic 51 9 3 Layout Consideration 51 10 IDE and Compact Flash 53 10 1 IDE Signals Definition 53 10 2 Reference Schematic 54 10 2 1 40 pin IDE Header 54 10 2 2 44 pin IDE Header 55 10 2 3 5 pin Compact Flash Header 56 10 3 Layout Consideration 57 11 PCI 58 11 1 PCI Signals Definition 58 11 2 PCI Resource Assignment 62 11 3 Reference Schematic 62 11 3 1 Device Do...

Page 6: ...s 69 12 3 2 Bus Clock Routing 69 13 AC 97 and HD Audio 70 13 1 Signals Definition 70 13 2 Reference Schematic 71 13 3 Layout Consideration 72 14 TV OUT 74 14 1 TV Out Signals Definition 74 14 2 Reference Schematic 75 14 3 Layout Consideration 75 15 SM bus and I2 C 76 15 1 Signals Definition 76 15 2 I2 C Address Allocation Consideration 76 15 3 Layout Consideration 77 16 Miscellaneous Signals 78 16...

Page 7: ...als 85 18 Power and Reset 86 18 1 VCC12V 86 18 2 VCC5V_STB 86 18 3 VCC_RTC 86 18 4 Copper Trace Size and Current Capacity 86 18 5 Reset Signals Definitions 87 19 BIOS Consideration 88 19 1 Legacy versus Legacy Free 88 19 2 Carrier Super I O Support 88 20 Mechanical Consideration 89 20 1 Form Factor 89 20 2 Heat Spreader 90 21 Layout Guidelines 91 21 1 PCB Stack ups 91 ...

Page 8: ...xpress 1 1 Trace Routing Guidelines 96 21 3 2 USB Trace Routing Guidelines 97 21 3 3 PEG 1 1 Trace Routing Guidelines 97 21 3 4 SDVO Trace Routing Guidelines 98 21 3 5 LAN Trace Routing Guidelines 99 21 3 6 Serial ATA Trace Routing Guidelines 100 21 3 7 LVDS Trace Routing Guidelines 101 21 4 Routing Rules for Single Ended Interfaces 101 21 4 1 PCI Trace Routing Guidelines 102 21 4 2 IDE Trace Rout...

Page 9: ...isplay Terms and Definitions 49 Table 13 IDE Signals Description 53 Table 14 PCI Signals Definition 58 Table 15 PCI Bus Interrupt Routing 62 Table 16 LPC Interface Signal 66 Table 17 Audio Codec Description of Signals 70 Table 18 TV Out Definition of Signals 74 Table 19 COM Express SMBus and I2 C Signal Groups 76 Table 20 Miscellaneous Signals 78 Table 21 Module Type Detection 79 Table 22 System S...

Page 10: ...able 30 SDVO Trace Routing Guidelines 98 Table 31 LAN Trace Routing Guidelines 99 Table 32 Serial ATA Trace Routing Guidelines 100 Table 33 LVDS Trace Routing Guidelines 101 Table 34 PCI Trace Routing Guidelines 102 Table 35 IDE Trace Routing Guidelines 103 Table 36 LPC Trace Routing Guidelines 103 ...

Page 11: ...gure 12 10 100 1000 Mbps LAN Example 38 Figure 13 USB Ports Reference Schematic 40 Figure 14 SATA Connector 41 Figure 14 SATA Connector Diagram 43 Figure 16 LVDS Reference Schematic 50 Figure 17 VGA Reference Schematic 51 Figure 18 40 pin IDE Example 55 Figure 19 44 pin IDE Example 56 Figure 20 50 pin CompactFlash Header Example 57 Figure 21 PCI Clock Buffer Circuitry 63 Figure 22 PCI Device Down ...

Page 12: ...try and Serial Schottky Diode 83 Figure 34 GPIO Loop Back Schematic 84 Figure 35 Mechanical Comparison of Available Com Express Form Factors 89 Figure 36 Heat Spreader Used on COMX ATOM 420 COM Express Module 90 Figure 37 Four Layer Stack Up 91 Figure 38 Six Layer Stack Up 91 Figure 39 Eight Layer Stack Up 92 Figure 40 Microstrip Cross Section 93 Figure 41 Stripline Cross Section 93 Figure 42 Layo...

Page 13: ...sed system 1 2 Intended Audience The intended audience of this document are COM Express carrier board designers It is strongly recommended to use the latest COM Express Specification and the module vendor s product manuals with this document 1 3 Acronyms and Abbreviations Item Description AC 97 Audio Coder Decoder 1997 An Intel defined format to digitally encode and decode audio signals ATX Advanc...

Page 14: ...VDS Low Voltage Differential Signaling Many modern high speed interfaces such as PCIe and SATA are LVDS interfaces However the term LVDS commonly refers to a serialized differential interface which is used for flat panel interfacing In this document and in the COM Express Specification LVDS refers primarily to a flat panel interface MAC Media Access Controller The digital hardware control section ...

Page 15: ...is sandwiched between two reference planes If the stripline trace is equidistant between the two reference planes it is said to be symmetric or balanced If the stripline trace is closer to on of the planes it is said to be asymmetric or unbalanced TMDS Transition Minimized Differential Signaling A low voltage differential signaling scheme for flat panel displays that is an alternative to flat pane...

Page 16: ...yco 3 1827253 6 220 pos 0 5 mm Plug Connector pair 5 mm Tyco 3 1827233 6 220 pos 0 5 mm Plug with hold carrier Single connector 8 mm Tyco 3 6318491 6 220 pos 0 5 mm Plug Connector pair 8 mm Tyco 3 5353652 6 220 pos 0 5 mm Plug with hold carrier For the carrier board connector figure see Figure 6 4 in the COM Express specification The following section details the COM Express signals group 2 2 Conn...

Page 17: ...COM Express Carrier Type 2 Page 17 of 103 Design Guide Figure 1 COM Express Type 2 Connector ...

Page 18: ... the PCI Express Card Electromechanical Specification and the PCI Express Mini Card Electromechanical Specification 3 2 COM Express PCIe Signals Definition The general purpose PCI Express interface of the COM Express Type 2 module on the COM Express A B connector consists of up to six lanes each with a receive and transmit differential signal pair designated from PCIE_RX0 and to PCIE_RX5 and and c...

Page 19: ...E PCIE_TX4 PCIE_TX4 A55 A56 PCIe channel 4 Transmit Output differential pair O PCIE PCIE_RX5 PCIE_RX5 B52 B53 PCIe channel 5 Receive Input differential pair I PCIE PCIE_TX5 PCIE_TX5 A52 A53 PCIe channel 4 Transmit Output differential pair O PCIE PCI_CLK_REF PCIE_CLK_REF A88 A89 PCIe reference clock for all COM Express PCIe lanes and for PEG lanes O PCIE COM Express only allocates a single ref cloc...

Page 20: ...ccording to the PCI Express Card Electromechanical Specification all PCIe devices must support polarity inversion on each PCIe lane independent of the other lanes This means that you can route the module s PCIE_TX0 signal to the corresponding pin on the slot or target device and the PCIE_TX0 signal to the corresponding pin If this makes the layout cleaner with fewer layer transitions and better di...

Page 21: ...be routed as directly as possible from source to destination Figure 2 PCI Express Clock Reference Schematic The following notes apply to this figure Nets that tie directly to the COM Express connector are indicated with the CEX flag in the off page connection symbol Each clock pair is routed point to point to each connector or end device using differential signal routing rules Each clock output pa...

Page 22: ...for the target device PCIe TX lines COM Express module PCIe RX lines are down on the carrier board close to the target device TX pins Trace length allowed for PCIe signals on the carrier board is longer for the Device Down case than for Device Up Device Up Coupling caps for the target device PCIe TX lines COM Express module PCIe RX lines are up on the slot card Trace length allowed for PCIe signal...

Page 23: ...romechanical Specification to allow hot plugged PCIe cards However most systems do not implement the support circuits needed to complete hot plug capability If used the scheme works as follows PRSNT1 pin A1 is pulled low on the carrier board through R14 On the slot card PRSNT1 is routed to PRSNT2 _0 pin B17 The state of slot pin B17 may be read back by the BIOS or system software if routed to an i...

Page 24: ...t swappable peripheral cards designed primarily for mobile computing The card s electrical interface is through either an x1 PCIe link or a USB 2 0 link Per the ExpressCard Source Specification the host interface should support both the PCIe and USB links The ExpressCard device may utilize one or the other or both interfaces There are several form factors defined 34 mm x 75 mm 54 mm x 75 mm 34mm x...

Page 25: ... 6 shows an ExpressCard implementation The example shows COM Express PCIe lane 2 and USB port 1 used but other assignments may be made depending on module capabilities and the system configuration Nets PCIE_TX2 and PCIE_TX2 are sourced from the COM Express module These lines drive the PCIe receivers on the ExpressCard No coupling capacitors are required on the carrier board These lines are capacit...

Page 26: ...p at COM Express module pin B66 WAKE0 WAKE0 is pulled up on the module to facilitate the wire ORed interconnect from other WAKE0 sources SMB_CK and SMB_DAT are sourced from COM Express module pins B13 and B14 respectively The SMBus supports client alerting wireless RF management and sideband management Support for the SMBus is optional on the carrier board and the ExpressCard 3 4 6 PCI Express Min...

Page 27: ...als are high speed differential pairs with a nominal 100 differential impedance Route them as differential pairs preferably referenced to a continuous GND plane with minimum via transitions PCIe pairs need to be length matched within a given pair intra pair but the different pairs do not need to be closely matched inter pair The following items should be observed when routing PCIe signals on the c...

Page 28: ...acing from differential pair to plane edge minimum 40 mils but if the space allowed is bigger so much the better For the differential pair trace width and spacing refer the stack up structure and impedance table from PCB vendor Maximum number of vias is six on each differential signal TX and TX signals should maintain symmetry when changing layers No tight bend use two 45 bends instead of 90 routi...

Page 29: ... Specification These PCIE lanes support polarity inversion and lane reversal to make it convenient for routing To activate the lane reversal mode for the PEG port the COM Express Specification defines an active low signal PEG_LANE_RV which can be found on the module s connector at row D pin D54 This pin is strapped low on the carrier board to invoke lane reversal mode Check the specified module if...

Page 30: ... PEG_TX5 PEG_TX5 D68 D69 PEG Channel 5 Transmit Output Differential Pair O PCIE Shared with SDVOC_GRN SDVOC_GRN PEG_RX6 PEG_RX6 C71 C72 PEG Channel 6 Receive Input Differential Pair I PCIE PEG_TX6 PEG_TX6 D71 D72 PEG Channel 6 Transmit Output Differential Pair O PCIE Shared with SDVOC_BLU SDVOC_BLU PEG_RX7 PEG_RX7 C74 C75 PEG Channel 7 Receive Input Differential Pair I PCIE PEG_TX7 PEG_TX7 D74 D75...

Page 31: ...4 C98 C99 PEG Channel 14 Receive Input Differential Pair I PCIE PEG_TX14 PEG_TX14 D98 D99 PEG Channel 14 Transmit Output Differential Pair O PCIE PEG_RX15 PEG_RX15 C101 C102 PEG Channel 15 Receive Input Differential Pair I PCIE PEG_TX15 PEG_TX15 D101 D102 PEG Channel 15 Transmit Output Differential Pair O PCIE SDVO_12C_CLK D73 I2C based control signal clock for SDVO device O 2 5V CMOS SDVO enabled...

Page 32: ...ts that COM Express signals SDVO_I2C_CLK and SDVO_I2C_DATA are pulled high to 2 5V and if the PEG_ENABLE line is left floating This combination leaves the module s internal graphics engine enabled but converts the output format to SDVO The SDVO_I2C_CLK and SDVO_I2C_DATA lines are pulled to 2 5V on an ADD2 card For a device down SDVO converter the SDVO_I2C_CLK and SDVO_I2C_DATA lines have to be pul...

Page 33: ...COM Express Carrier Type 2 Page 33 of 103 Design Guide 4 2 Schematic Examples 4 2 1 x16 PCIE Graphic Card Figure 8 x1 x4 x8 x16 Slot ...

Page 34: ...Page 34 of 103 COM Express Carrier Type 2 Design Guide 4 2 2 SDVO to DVI Inverter Figure 9 SDVO to DVI Transmitter Example Part 1 ...

Page 35: ...f the differential signals must be kept as close to the same as possible The maximum length difference must not exceed 100 mils for any of the pairs relative to each other Spacing between the differential pair traces should be more than two times the trace width to reduce trace to trace couplings For example having wider gaps between differential pair DVI traces will minimize noise coupling It is ...

Page 36: ...Page 36 of 103 COM Express Carrier Type 2 Design Guide Table 5 SDVO Layout Requirement ...

Page 37: ...OM Express nodule on an exception basis The magnetic circuit should be implemented on the carrier board 5 1 LAN Signals Definition The LAN interface of the COM Express module consists of four pairs of low voltage differential pair signals designated from GBE0_MDI0 and to GBE0_MDI3 and plus additional control signals for link activity indicators These signals can be used to connect to a 10 100 1000...

Page 38: ... the details 5 3 Example Schematic Figure 1110 100 1000 Mbps LAN Example 5 4 Layout Consideration The four differential pairs from GBE0_MDI0 and to GBE0_MDI3 and are required to meet a specific waveform template and associated signal integrity requirements defined in the IEEE 802 3 2005 specification In order to meet these requirements the routing rules in Section 21 3 5 LAN Trace Routing Guidelin...

Page 39: ...ecification also encodes single ended state information in the differential pair making EMI filtering somewhat challenging Carriers that are internal to the carrier do not need EMI filters A USB port can be powered from the carrier main power or from the carrier suspend power Main Power is used for USB devices that are accessed when the system is powered on Suspend Power VCC_5V_SBY is used for dev...

Page 40: ...th a 90 ohm differential impedance and a 45 ohm single ended impedance Ideally a USB pair is routed on a single layer adjacent to a ground plane USB pairs should not cross plane splits Keep layer transitions to a minimum Reference USB pairs to a power plane if necessary The power plane should be well bypassed Section 21 3 2 USB Trace Routing Guidelines summarizes the USB routing rules ...

Page 41: ...A 150 The COM Express Specification addresses both in the section on insertion losses SATA devices can be internal to the system or external The eSATA specification defines the connector used for external SATA devices The eSATA interface must be designed to prevent damage from ESD comply with EMI limits and withstand more insertion removals cycles than standard SATA A specific eSATA connector was ...

Page 42: ...Page 42 of 103 COM Express Carrier Type 2 Design Guide 7 1 SATA Signals Definition Table 8 SATA Signal Definition Table 9 SATA Connector Pinout Table 10 SATA Power Connector Pinout ...

Page 43: ...types are available that deliver power and data to the SATA drive This may be over a combined power data cable or in a direct configuration in which the SATA drive mates directly to the 22 pin plug on the carrier board Please refer to the SATA Specification Appendix G for pinout information ESD clamp diodes such as Semtech Rclamp0524 are shown in the eSATA schematic This device contains low capaci...

Page 44: ...yout Consideration Route SATA signals as differential pairs with 100 ohm differential impedance and a 55 ohm single ended impedance Ideally a SATA pair is routed on a single layer adjacent to a ground plane SATA pairs should not cross plane splits Keep layer transitions to a minimum Reference SATA pairs to a power plane if necessary The power plane should be quiet and well bypassed SATA 150 routin...

Page 45: ...can be driven Each COM Express LVDS channel consists of four differential data pairs and a differential clock pair for a total of five differential pairs per channel COM Express modules and module chipsets may not use all pairs For example with 18 bit TFT displays only three of the four data pairs on the LVDS_A channel are used along with the LVDS_A clock The LVDS_B lines are not used The manner i...

Page 46: ...and signal quality Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation as common mode noise which is rejected by the receiver Twisted pair cables provide a low cost solution with good balance and flexibility They are capable of medium to long runs depending upon the application skew budget A variety of shielding options are av...

Page 47: ...prietary methods for storing flat panel timing data DisplayID defines a data structure that contains information such as display model identification information colorimetry feature support and supported timings and formats The DisplayID data allows the video controller to be configured for optimal support for the attached display without user intervention The basic data structure is a variable le...

Page 48: ...t bits to the fourth channel Six bits are added two red two green and two blue the seventh available bit slot in the fourth LVDS stream is not used A 24 bit Open LDI implementation shifts the color bits on the original three LVDS data pairs up by two such that the most significant color bits for both 18 and 24 bit panels occupy the same LVDS slots For example the most significant red color bit is ...

Page 49: ...COM Express Carrier Type 2 Page 49 of 103 Design Guide Terms Definition Table 12 LVDS Display Terms and Definitions ...

Page 50: ... ground plane LVDS pairs should not cross plane splits Keep layer transitions to a minimum Reference LVDS pairs to a power plane if necessary The power plane should be well bypassed Length matching between the two lines that make up an LVDS pair intra pair and between different LVDS pairs inter pair is required Intra pair matching is tighter than the inter pair matching All LVDS pairs should have ...

Page 51: ...rresponding signals can be found on the COM Express module connector row B 9 2 Reference Schematic Figure 16VGA Reference Schematic To prevent leakage level shift CRT DDC from 3 3 V to 5 V and enable with CB_RESET Connection between logic GND and chassis depends on the grounding architecture Connect GND with the chassis on a single point This connection is drawn on all schematic examples throughou...

Page 52: ...monitor sync signals with a tolerance of 5 V it is necessary to implement high impedance unidirectional buffers These buffers prevent potential electrical over stress of the module and avoid that VGA monitors may attempt to drive the monitor sync signals back to the module COM Express provides a dedicated I2 C bus for the VGA interface It corresponds to the VESA defined DDC interface that is used ...

Page 53: ...e module C D connectors can be used for an IDE port or a pair of LAN ports as the COM Express specification depending on the module type For module Types 2 and 4 IDE support is required LAN 1 and 2 are not available The IDE PATA signals support up to two devices in a master slave configuration Table 13 IDE Signals Description ...

Page 54: ...sfer rates such as ATA66 and ATA100 require 80 pin conductor cables where the extra 40 conductors are tied to ground to isolate the adjacent signals for better signal integrity The 80 pin cable assembly also ties pin 34 IDE_CBLID on the 40 pin header to GND If IDE_CBLID is sampled low by the module s BIOS it assumes that the proper high speed cable is present and sets up the drive parameters accor...

Page 55: ...100 require special handling as ground isolated cables like those commonly used for 3 5 in ATA devices do not exist for this interface Simulation as well as testing should be used to determine if an application specific 44 pin cable interface could support ATA66 and ATA100 speeds Items to be taken into consideration include cable length placement in the system folds and routing Because 44 conducto...

Page 56: ...OM Express carrier board If this is not done then some DMA capable CF cards may not work because they are not designed for non DMA mode For more information about this subject refer to the data sheet of the CF card or contact your CF card manufacturer CF socket pin 39 CSEL is connected to a jumper to select master or slave configuration If jumpered low the drive is configured for master mode This ...

Page 57: ... Figure 1950 pin CompactFlash Header Example 10 3Layout Consideration The IDE signals are single ended signals with a nominal impedance of 55 ohms See Section 20 4 2 IDE Trace Routing Guidelines on page xxx for more information about routing considerations ...

Page 58: ...s I O 3 3V PCI_AD1 D22 PCI bus multiplexed address and data lines I O 3 3V PCI_AD2 C25 PCI bus multiplexed address and data lines I O 3 3V PCI_AD3 D23 PCI bus multiplexed address and data lines I O 3 3V PCI_AD4 C26 PCI bus multiplexed address and data lines I O 3 3V PCI_AD5 D24 PCI bus multiplexed address and data lines I O 3 3V PCI_AD6 C27 PCI bus multiplexed address and data lines I O 3 3V PCI_A...

Page 59: ...tiplexed address and data lines I O 3 3V IDSEL for slot 0 PCI_AD21 C42 PCI bus multiplexed address and data lines I O 3 3V IDSEL for slot 1 PCI_AD22 D40 PCI bus multiplexed address and data lines I O 3 3V IDSEL for slot 2 PCI_AD23 C43 PCI bus multiplexed address and data lines I O 3 3V IDSEL for slot 3 PCI_AD24 D42 PCI bus multiplexed address and data lines I O 3 3V PCI_AD25 C45 PCI bus multiplexe...

Page 60: ...y control line active low I O 3 3V PCI_TRDY D35 PCI bus Target Ready control line active low I O 3 3V PCI_STOP D34 PCI bus STOP control line active low I O 3 3V PCI_PAR D32 PCI bus parity I O 3 3V PCI_PERR C34 Parity error an external PCI device drivers PERR by driving it low when it receives data that has a parity error I O 3 3V PCI_REQ0 C22 PCI bus master request input line active low I 3 3V PCI...

Page 61: ...PCI peripherals drive PME to low to wake up the system from low power states S1 S5 I 3V3_SBY PCI_CLKRUN D48 Bidirectional pin used to support PCI clock run protocol for mobile systems I O 3 3V PCI_IRQA C49 PCI interrupt request line A I 3 3V PCI_IRQB C50 PCI interrupt request line B I 3 3V PCI_IRQC D46 PCI interrupt request line C I 3 3V PCI_IRQD D47 PCI interrupt request line D I 3 3V PCI_CLK D50...

Page 62: ...to a separate PCI address line For PCI bus slots 1 4 COM Express specifies the PCI address lines AD 20 to AD 23 Table 15 PCI Bus Interrupt Routing Most of these PCI devices only utilize the interrupt signal INTA To distribute the interrupt source of the devices over the interrupt signals INTB INTC and INTD an interrupt cross routing scheme has to be implemented on the COM Express carrier board des...

Page 63: ...quires a rise and fall time slew rate within 1 V ns and 4 V ns The slew rate must be met across the minimum peak to peak portion of the clock waveform which is between 0 66 V and 1 98 V for 3 3 V clock signaling These parameters are very critical for EMI and must be observed during carrier board layout when implementing the PCI Bus Figure 21PCI Device Down Example Dual UART ...

Page 64: ...routing parameters and guidelines The PCI clock should be routed carefully The COM Express specification allows 1 6 ns 0 1 ns for the propagation delay of the PCI clock from the module pin to the destination pin of the PCI device Using a typical propagation delay value of 180 ps in this works out to 8 88 inches of carrier board trace for a device down application For device up situations the PCI L...

Page 65: ...COM Express Carrier Type 2 Page 65 of 103 Design Guide separated as far as possible from other signal traces ...

Page 66: ...d design COM Express also provides interface pins necessary for optional carrier board resident PS keyboard controllers 12 1LPC Signals Definition Table 16 LPC Interface Signal Implementing external LPC devices on the COM Express carrier board always requires customization of the COM Express module s BIOS in order to support basic initialization for those LPC devices Otherwise the functionality of...

Page 67: ...FGPI 0 4 are general purpose inputs that may be read by system software They should be tied to a valid logic level FWH pin 7 WP enables write protection for main block sectors when it is pulled low If pulled high hardware write protection is disabled FWH pin 8 TBL enables write protection for the top block sector when pulled low FWH pins 12 11 10 9 ID 0 3 are ID pins that allow multiple FWH parts ...

Page 68: ...A Low Use PNP High No PNP Pin 54 SOUTA Low Disable KBC High Enable KBC Pin 83 SOUTB Low 24 MHz clock High 48 MHz clock SIO Keyboard Mouse controller is disabled with the strapping shown here Pull down resistor required on unused pins of a used COM port floating pins generate interrupts If using the SIO Keyboard Mouse controller load the two logic gates shown These gates perform level shifting SIO ...

Page 69: ... from the module pin to the LPC device destination pin Using a typical propagation delay value of 180 ps in this works out to 8 88 inches of carrier board trace for a device down application For device up situations 2 5 inches of clock trace are assumed to be on the LPC slot card by analogy to the PCI specification This is deducted from the 8 88 inches yielding 6 38 inches On a carrier board with ...

Page 70: ...allocates seven pins on the A B connector to support digital AC 97 and HD interfaces to audio codecs on the carrier board The pins are available on all module types High definition HD audio uses the same digital signal interface as AC 97 audio Codecs for AC 97 and HD audio are different Table 17 Audio Codec Description of Signals ...

Page 71: ...COM Express Carrier Type 2 Page 71 of 103 Design Guide 13 2Reference Schematic Figure 25AC 97 Schematic Example Figure 26Audio Amplifier ...

Page 72: ...tal components in another Keep digital signal traces especially the clock as far as possible from the analog input and voltage reference pins Provide separate analog and digital ground planes with the digital components over the digital ground plane and the analog components including the analog power regulators over the analog ground plane The split between the planes must be a minimum of 0 05 in...

Page 73: ...he main ground plane The split between the planes must be a minimum of 0 05 in wide Any signals entering or leaving the analog area must cross the ground split in the area where the analog ground is attached to the main carrier board ground This means that no signal should cross the split gap between the ground planes because this would cause a ground loop which in turn would greatly increase EMI ...

Page 74: ...d color chroma This is also known as Y C video Component Video A video signal that consists of three components The components may be RGB or may be encoded using other component encoding schemes such as YUV YCbCr and YPbPr A COM Express module may support all some or none of these formats Within these formats there are different encoding schemes that may be used The most widely used encoding schem...

Page 75: ...lose as possible to the TV Out connector on the carrier board A second 150 ohm 1 termination resistor exists on the COM Express module itself At least 30 mils of spacing should be used for the routing between each TV DAC channel to prevent crosstalk between the TV DAC signals The maximum trace length distance of the TV DAC signals between the COM Express connector and the 150 ohm 1 termination res...

Page 76: ...he module However if the carrier board also uses suspend powered SMBus devices that are designed to operate during system states S3 S5 then these devices must be connected to the suspend powered side of the SMBus i e between the COM Express module and the bus switch Table 19 COM Express SMBus and I2 C Signal Groups SMBus and I2C Bus Function Clock Data General purpose user I2 C I2C_CK I2C_DAT LVDS...

Page 77: ...ommendation is to not connect these devices to the SMBus The maximum load of SMBus lines is limited to 3 external devices Do not connect Non Suspend powered devices to the SMBus unless a bus switch is used to prevent back feeding of voltage from the Suspend rail to other supplies Do not use the same address that the module has already used for carrier located devices ...

Page 78: ... to the carrier board If an incompatible module pinout type is detected external logic should prevent the carrier board from powering up the whole system by controlling the 12 V supply voltage The pins TYPE0 TYPE1 and TYPE2 are either left open NC or strapped to ground GND by the module to encode the pinout type according to Table 21 Module Type 1 has no encoding For more information about this su...

Page 79: ...ype 2 Detection Circuitry 16 2Power Management Signals COM Express specifies a set of signals to control the system power states such as the power on and reset conditions This enables the system designer to implement a fully ACPI compliant system supporting system states from S0 to S5 The minimum hardware requirements for an ACPI compliant system are an ATX conforming power supply and a power butt...

Page 80: ...Page 80 of 103 COM Express Carrier Type 2 Design Guide Table 22 System States S0 S5 Definitions Table 23 Power Management Signal Description ...

Page 81: ...dog Timer Event Latch Schematic 16 4Speaker The PC AT architecture provides a speaker signal that creates beeps and chirps The signal is a digital logic signal that is created from system timers within the core chipset The speaker provides feedback to the user that an error has occurred The system BIOS usually drives the speaker line with a set of beep codes to indicate hardware problems such as a...

Page 82: ..._RTC can be found on the module s connector row A pin A47 To implement the RTC battery according to the Underwriters Laboratories UL guidelines battery cells must be protected against a reverse current going to the cell This can be done by using either a series Schottky diode or a series resistor There are two implementation possibilities and the following examples explain the advantages and disad...

Page 83: ...COM Express Carrier Type 2 Page 83 of 103 Design Guide Figure 32RTC Battery Circuitry and Serial Schottky Diode 16 6GPIO Table 24 GPIO Signal Definition ...

Page 84: ...eral purpose outputs pins in Figure 33 These signals drive switch inputs such as lamps relays and sensors GPI signals from a header are shown with protection diodes The signals are connected for input to the COM Express module GPO signals from the COM Express module are shown buffered The signals are connected to the header with protection diodes ...

Page 85: ...used for system thermal management In most current system platforms thermal management is closely associated with system power management For more detailed information about the thermal management capabilities of the COM Express module refer to the user s guide of the manufacturer s module Table 25 Thermal Management Signal Description ...

Page 86: ...y powered on it can be provided by the 3 3 V standby power rail For more information see Section 16 5 RTC Battery 18 4Copper Trace Size and Current Capacity The current capacity of a PCB trace is proportional to the trace s cross sectional area the product of the trace width and thickness The trace thickness is proportional to the weight of copper used The weight of the copper is expressed in ounc...

Page 87: ...e Copper Trace Current Capability Per IPC 2221 Charts 18 5Reset Signals Definitions A number of other signals may be involved in power delivery to the module These include the suspend status outputs from the module SUS_S5 SUS_S4 SUS_S3 and SUS_STAT external power status input to the module PWR_OK a reset input signal to the module SYSRESET various reset outputs from the module including CB_RESET P...

Page 88: ...t s transition toward newer peripherals the low pin count LPC interface was created as a space efficient replacement for the Industry Standard Architecture ISA bus In addition to firmware devices such as BIOS flash low speed Super I O controllers were developed for the LPC bus to fill the gap until the momentum could build for new high speed serial based peripherals 19 2Carrier Super I O Support A...

Page 89: ...s two different sized COM Express modules The basic module 125 mm x 95 mm and the extended module 155 mm x 110 mm Based on customer demand many COM Express module vendors also offer even smaller form factors with backwards compatibility to the COM Express specification Figure 34Mechanical Comparison of Available Com Express Form Factors ...

Page 90: ...olution The application specific thermal solution may use heat sinks with fans and or heat pipes which can be attached to the heat spreader Some thermal solutions may also require that the heat spreader is attached directly to the systems chassis therefore using the whole chassis as a heat dissipater The main mechanical mounting solutions for systems based on COM Express modules have proven to be ...

Page 91: ...p This figure is an example of a four layer stack up Layers L1 and L4 are used for signal routing Layers L2 and L3 are used for solid ground and power planes respectively Microstrips on layers 1 and 4 reference ground and power planes on layers 2 and 3 respectively In some cases it may be advantageous to swap the GND and PWR planes This allows layer 4 to be GND referenced Layer 4 is clear of parts...

Page 92: ...ls These signals are referenced to layers 2 and 7 to meet the characteristic impedance target for these traces To reduce coupling to layers 4 and 5 specify thicker prepreg to increase layer separation 21 2Trace Impedance Considerations Most high speed interfaces used in a COM Express design for a carrier board are differential pairs that need a well defined and consistent differential and single e...

Page 93: ... trace are H1 and W1 See Figure 39 Figure 40 Table 27 Both H1 and W1 can be manipulated slightly by the PCB vendor The differential impedance of a trace pair depends primarily on H1 W1 and the pair pitch A PCB vendor can easily manipulate H1 and W1 but changing the pair pitch cannot generally be done at fabrication time It is more important for the PCB designer and the Project Engineer to determin...

Page 94: ...fferential pair per segment Maintain parallelism and symmetry between differential signals with the trace spacing needed to achieve the specified differential impedance Maintain maximum possible separation between the differential pairs and any high speed clocks periodic signals CMOS TTL and any connector leaving the PCB such as I O connectors control and signal headers or power connectors Route d...

Page 95: ...sting experience the minimum suggested spacing to clock signals is 50mil Use a minimum of 20mil spacing between the differential signal pairs and other signal traces for optimal signal quality This helps to prevent crosstalk Route all traces over continuous planes VCC or GND with no interruptions Avoid crossing over anti etch if at all possible Crossing over anti etch split planes increases induct...

Page 96: ...e Routing Guidelines Table 28 PCI Express 1 1 Trace Routing Guidelines Suggested trace parameters are shown Using impedance calculation software is recommended to determine trace width distance to reference planes and pair spacing applicable to your specific project and PCB materials ...

Page 97: ... Express 1 1 Trace Routing Guidelines The COM Express specification does not define different trace routing rules for PCIe Graphics PEG and PCI Express lanes Newer chipsets feature low power modes for the PEG signals To ensure compatibility it is recommended to keep the PEG signal lines as short as possible A maximum of 5 in to the carrier device down and 4 in to a carrier slot is advisable ...

Page 98: ...e Routing Guidelines Table 30 SDVO Trace Routing Guidelines Suggested trace parameters are shown Using impedance calculation software is recommended to determine trace width distance to reference planes and pair spacing applicable to your specific project and PCB materials ...

Page 99: ...uidelines Suggested trace parameters are shown Using impedance calculation software is recommended to determine trace width distance to reference planes and pair spacing applicable to your specific project and PCB materials Also observe trace geometry definitions and restrictions provided by the device vendor of the PHY ...

Page 100: ...e Routing Guidelines Table 32 Serial ATA Trace Routing Guidelines Suggested trace parameters are shown Using impedance calculation software is recommended to determine trace width distance to reference planes and pair spacing applicable to your specific project and PCB materials ...

Page 101: ...should help implement these interfaces while providing maximum COM Express carrier board performance Do not route traces under crystals crystal oscillators clock synthesizers magnetic devices or ICs that use or generate clocks Avoid tight bends When it becomes necessary to turn 90 use two 45 turns or an arc instead of making a single 90 turn Stubs on signals should be avoided because stubs will ca...

Page 102: ...g a greater loop area Route digital power and signal traces over the digital ground plane Position the bypassing and decoupling capacitors close to the IC pins with wide traces to reduce impedance 21 4 1 PCI Trace Routing Guidelines Table 34 PCI Trace Routing Guidelines Suggested trace parameters are shown Using impedance calculation software is recommended to determine trace width distance to ref...

Page 103: ...ce Routing Guidelines Suggested trace parameters are shown Using impedance calculation software is recommended to determine trace width distance to reference planes and pair spacing applicable to your specific project and PCB materials 21 4 3 LPC Trace Routing Guidelines Table 36 LPC Trace Routing Guidelines ...

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Emerson COM Express Carrier, Design Manual

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