Emerson COM Express Carrier, Design Manual

Page: 94 / 103

Page 94 of 103 COM Express Carrier Type 2
Design Guide
Table 27 Trace Parameters
21.3 Routing Rules for High-Speed Differential Interfaces
The following is a list of suggestions for designing with high-speed differential signals. This should help
implement these interfaces while providing maximum COM Express carrier board performance.

Use controlled impedance PCB traces that match the specified differential impedance.

Keep the trace lengths of the differential signal pairs as short as possible.

The differential signal pair traces should be trace-length matched and the maximum tracelength
mismatch should not exceed the specified values. Match each differential pair per segment.

Maintain parallelism and symmetry between differential signals with the trace spacing needed to
achieve the specified differential impedance.

Maintain maximum possible separation between the differential pairs and any high-speed
clocks/periodic signals (CMOS/TTL) and any connector leaving the PCB (such as, I/O connectors,
control and signal headers, or power connectors).

Route differential signals on the signal layer nearest to the ground plane using a minimum of vias
and corners. This will reduce signal reflections and impedance changes. Use GND stitching vias
when changing layers.

It is best to put CMOS/TTL and differential signals on a different layer(s), which should be isolated by
the power and ground planes.
 Avoid tight bends. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of
making a single 90° turn.