Eiki LC-XT6, Service Manual

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Electrical Adjustment
Grp / No. Item Function Range Initial Note
0 BKMOD
0: Blending Mode (NORMAL) Layered Disable
1: Blending Mode (BLANKINK)Layered Disable
2: Blending Mode (NORMAL)Layered Enable
3: Blending Mode (BLANKING)Layered Enable
0 - 3 3
1 BLD_I_SIZE_H Inner Frame Width H 0 - 255 3
2 BLD_I_SIZE_V Inner Frame Width V 0 - 255 3
3 BLD_CURVE Curve 0 - 255 0
4 RGB_GAIN PC-Standard 0 - 511 256
5 RGB_GAIN PC-Real 0 - 511 256
6 RGB_GAIN PC-Dynamic 0 - 511 256
7 RGB_GAIN AV-Standard 0 - 511 256
8 RGB_GAIN AV-Cinema 0 - 511 256
9 RGB_GAIN AV-Dynamic 0 - 511 256
10 Bld_Exp_Int PC-Standard 0 -255 118
11 Bld_Exp_Int PC-Real 0 -255 118
12 Bld_Exp_Int PC-Dynamic 0 -255 118
13 Bld_Exp_Int AV-Standard 0 -255 118
14 Bld_Exp_Int AV-Cinema 0 -255 118
15 Bld_Exp_Int AV-Dynamic 0 -255 118
16 Bld_off_mult PC-Standard 0 -255 64
17 Bld_off_mult PC-Real 0 -255 64
18 Bld_off_mult PC-Dynamic 0 -255 64
19 Bld_off_mult AV-Standard 0 -255 64
20 Bld_off_mult AV-Cinema 0 -255 64
21 Bld_off_mult AV-Dynamic 0 -255 64
22 Bld_N_DT_NO Blending: tabale type 0 - 15 15
23 MultImgColor 0 - 47 15
85 AV FPGA Dot Clock Rate
1 PC-Dot Clock Rate Slot-DIgtal 1002
2 AV-Dot Clock Rate Slot-DIgital 1002
86 MOTHER FPGA DLYCNT
0 DLYCNT (SLOT1) SLOT1 Clock Phase [DVI-Dsub] 0 - 255 7
1 DLYCNT (SLOT1) SLOT1 Clock Phase [HDCP-DVI] 0 - 255 7
2 DLYCNT (SLOT1) SLOT1 Clock Phase [Dual Fanc-SDI] 0 - 255 3
3 DLYCNT (SLOT1) SLOT1 Clock Phase [Dual Link-SDI] 0 - 255 3
4 DLYCNT (SLOT1) SLOT1 Clock Phase [AMIMON] 0 - 255 3
5 DLYCNT (SLOT1) SLOT1 Clock Phase [Reserved] 0 - 255 1
6 DLYCNT (SLOT1) SLOT1 Clock Phase [Reserved] 0 - 255 1
7 DLYCNT (SLOT1) SLOT1 Clock Phase [Reserved] 0 - 255 1
8 DLYCNT (SLOT1) SLOT1 Clock Phase [Reserved] 0 - 255 1
9 DLYCNT (SLOT1) SLOT1 Clock Phase [Reserved] 0 - 255 1
10 DLYCNT (SLOT2) SLOT2 Clock Phase [DVI-Dsub] 0 - 255 7
11 DLYCNT (SLOT2) SLOT2 Clock Phase [HDCP-DVI] 0 - 255 7
12 DLYCNT (SLOT2) SLOT2 Clock Phase [Dual Fanc-SDI] 0 - 255 3
13 DLYCNT (SLOT2) SLOT2 Clock Phase [Dual Link-SDI] 0 - 255 3
14 DLYCNT (SLOT2) SLOT2 Clock Phase [AMIMON] 0 - 255 3
15 DLYCNT (SLOT2) SLOT2 Clock Phase [Reserved] 0 - 255 1
16 DLYCNT (SLOT2) SLOT2 Clock Phase [Reserved] 0 - 255 1
17 DLYCNT (SLOT2) SLOT2 Clock Phase [Reserved] 0 - 255 1
18 DLYCNT (SLOT2) SLOT2 Clock Phase [Reserved] 0 - 255 1
19 DLYCNT (SLOT2) SLOT2 Clock Phase [Reserved] 0 - 255 1
90 SW FPGA -SETTING
1 LVDS_SJY_PHASE AV 0 - 255 126
2 RSTOFF AV 0 - 1 0
4 LVDS_AJY_PHASE Slot 0 - 255 135
5 RSTOFF Slot 0 - 1 0
6 TSEL 0 - 3 0
100 CXA7009
0 G SIG Center 0 - 63 37
1 B SIG Center 0 - 63 37
2 R SIG Center 0 - 255 37
3 G Gain Control 0 - 255 194
4 B Gain Control 0 - 255 194
5 R Gain Control 0 - 255 194
6 G Bright Control 0 - 255 0
7 B Bright Control 0 - 255 0
8 R Bright Control 0 - 255 0
9 G VCOM Control 0 - 127 100
10 B VCOM Control 0 - 127 100
11 R VCOM Control 0 - 127 100
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