80
TAS5611PHD (MAIN : IC109)
Block Diagram
62
16
15
OC_ADJ
14
RESET
13
C_STARTUP
12
INPUT_A
11
INPUT_B
10
VI_CM
9
GND
8
AGND
7
VREG
6
INPUT_C
5
INPUT_D
4
FREQ_ADJ
3
2
OSC_IO-
1
SD
23
D_
D
N
G
13
D_
D
DV
P
03
D_
D
DV
P
92
D_
T
U
O
82
D_
T
U
O
72
D_
TS
B
D_
D
DV
G
52
C_
D
DV
G
42
DN
G
32
DN
G
22
C
N
12
C
N
02
C
N
91
C
N
81
FE
R_
U
SP
71
D
DV
33
GND_D
34
GND_C
35
GND_C
36
OUT_C
37
OUT_C
38
PVDD_C
39
PVDD_C
40
BST_C
41
BST_B
42
PVDD_B
43
OUT_B
44
GND_B
45
GND_A
46
47
48
55
94
05
15
Y
DA
E
R
25
1
M
35
2
M
45
3
M
D
N
G
65
D
N
G
75
B_
D
DV
G
85
A_
D
DV
G
95
A_
TS
B
06
A_
T
U
O
16
A_
T
U
O
26
A_
D
DV
P
36
A_
D
DV
P
46
A_
D
N
G
OTW1
PI
L
C
PVDD_B
OUT_B
GND_B
2
WT
O
(TOP VIEW)
M1
M2
/RESET
/SD
/OTW2
AGND
OC_ADJ
VREG
VDD
GVDD_A
M3
GND
INPUT_D
OUT_A
GND_A
PVDD_A
BST_A
GVDD_A
PWM
ACTIVITY
DETECTOR
GVDD _C
GVDD_B
INPUT_C
OUT_B
GND_B
PVDD_B
BST_B
GVDD_B
GVDD_D
GVDD_C
OUT_C
GND_C
PVDD_C
BST_C
GVDD_D
OUT_D
GND_D
PVDD_D
BST_D
INPUT_B
INPUT_A
PVDD_X
OUT_X
GND_X
TIMING
CONTROL
CONTROL
GATE-DRIVE
TIMING
CONTROL
CONTROL
GATE-DRIVE
TIMING
CONTROL
CONTROL
GATE-DRIVE
TIMING
CONTROL
CONTROL
GATE-DRIVE
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
+
-
X
U
M
R
OT
A
R
A
P
M
O
C
G
O
L
A
N
A
+
-
+
-
+
-
CI
G
O
L
O/I
&
N
OI
T
C
E
T
O
R
P
VI_CM
STARTUP
CONTROL
POWER-UP
RESET
TEMP
SENSE
OVER-LOAD
PROTECTION
PPSC
CB3C
UVP
CURRENT
SENSE
VREG
C_STARTUP
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
OSCILLATOR
FREQ_ADJ
OSC_SYNC_IO-
X
U
M
T
U
P
NI
G
O
L
A
N
A
PSU_FF
PSU_REF
4
4
4
PVDD_X
4
GND
OSC_
/OTW1
READY
/CLIP
TAS5611
www.ti.com
SLAS681 –NOVEMBER 2009
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2009, Texas Instruments Incorporated
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TAS5611
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