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82
IS42S16400F-6TL (USB: IC4)
Block Diagram
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. C
05/29/08
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
IS42S16400F, IC42S16400F
IS45S16400F
FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• Auto refresh (CBR)
• 4096 refresh cycles every 64 ms (A1 grade) or
16ms (A2 grade)
• Random column address every clock cycle
• Programmable
CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package: 54-pin TSOP II, 54-ball FBGA
(8mm x 8mm)
• Operation Temperature Range
Commercial (0
o
C to +70
o
C)
Industrial (-40
o
C to +85
o
C)
Automotive Grade A1 (-40
o
C to +85
o
C)
Automotive Grade A2 (-40
o
C to +105
o
C)
OVERVIEW
ISSI
's 64Mb Synchronous DRAM is organized as 1,048,576
bits x 16-bit x 4-bank for improved performance. The
synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
JUNE 2008
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
VDD
DQ0
VDDQ
DQ1
DQ2
GNDQ
DQ3
DQ4
VDDQ
DQ5
DQ6
GNDQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28 GND
DQ15
GNDQ
DQ14
DQ13
VDDQ
DQ12
DQ11
GNDQ
DQ10
DQ9
VDDQ
DQ8
GND
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A11 Address Input
BA0, BA1 Bank Select Address
DQ0 to DQ15 Data I/O
CLK System Clock Input
CKE Clock Enable
CS
Chip Select
RAS Row Address Strobe Command
CAS
Column Address Strobe Command
WE
Write Enable
LDQM Lower Bye, Input/Output Mask
UDQM Upper Bye, Input/Output Mask
V
DD
Power
GND Ground
V
DDQ
Power Supply for DQ Pin
GND Q Ground for DQ Pin
NC No Connection
M1
M2
/RESET
/SD
/OTW2
AGND
OC_ADJ
VREG
VDD
GVDD_A
M3
GND
INPUT_D
OUT_A
GND_A
PVDD_A
BST_A
GVDD_A
PWM
ACTIVITY
DETECTOR
GVDD _C
GVDD_B
INPUT_C
OUT_B
GND_B
PVDD_B
BST_B
GVDD_B GVDD_D
GVDD_C
OUT_C
GND_C
PVDD_C
BST_C
GVDD_D
OUT_D
GND_D
PVDD_D
BST_D
INPUT_B
INPUT_A
PVDD_X
OUT_X
GND_X
TIMING
CONTROL
CONTROL GATE-DRIVE
TIMING
CONTROL
CONTROL GATE-DRIVE
TIMING
CONTROL
CONTROL GATE-DRIVE
TIMING
CONTROL
CONTROL GATE-DRIVE
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
+
-
X
U
M
R
OT
A
R
A
P
M
O
C
G
O
L
A
N
A
+
-
+
-
+
-
CI
G
O
L
O/I
&
N
OI
T
C
E
T
O
R
P
VI_CM
STARTUP
CONTROL
POWER-UP
RESET
TEMP
SENSE
OVER-LOAD
PROTECTION
PPSC
CB3C
UVP
CURRENT
SENSE
VREG
C_STARTUP
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
OSCILLATOR
FREQ_ADJ
OSC_SYNC_IO-
X
U
M
T
U
P
NI
G
O
L
A
N
A
PSU_FF
PSU_REF
4
4
4
PVDD_X
4
GND
OSC_
/OTW1
READY
/CLIP
TAS5611
www.ti.com SLAS681 –NOVEMBER 2009
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2009, Texas Instruments Incorporated
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