90
Terminal Function
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
ADR5/ADR1/RSV
MS/ADR0/RSV
MC/SCL/FMT
MD/SDA/DEMP
MODE
ZERO1
ZERO2/AMUTEO
AMUTEI
VCC2
AGND2
VOUTR
VOUTR+
LRCK
BCK
DIN
RST
SCKI
VDD
DGND
VCC1
VCOM
AGND1
VOUTL
VOUTL+
PCM1789
PCM1789
SBAS451–OCTOBER 2008
..............................................................................................................................................................................................
www.ti.com
PW PACKAGE
TSSOP-24
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
PULL-
5-V
NAME
PIN
I/O
DOWN
TOLERANT
DESCRIPTION
LRCK
1
I
Yes
No
Audio data word clock input
BCK
2
I
Yes
No
Audio data bit clock input
DIN
3
I
No
No
Audio data input
RST
4
I
Yes
Yes
Reset and power-down control input with active low
SCKI
5
I
No
Yes
System clock input
VDD
6
—
—
—
Digital power supply, +3.3 V
DGND
7
—
—
—
Digital ground
VCC1
8
—
—
—
Analog power supply 1, +5 V
VCOM
9
—
—
—
Voltage common decoupling
AGND1
10
—
—
—
Analog ground 1
VOUTL–
11
O
No
No
Negative analog output from DAC left channel
VOUTL+
12
O
No
No
Positive analog output from DAC left channel
VOUTR+
13
O
No
No
Positive analog output from DAC right channel
VOUTR–
14
O
No
No
Negative analog output from DAC right channel
AGND2
15
—
—
—
Analog ground 2
VCC2
16
—
—
—
Analog power supply 2, +5 V
AMUTEI
17
I
No
Yes
Analog mute control input with active low
ZERO2/AMUTEO
18
O
No
No
Zero detect flag output 2/Analog mute control output
(1)
with active low
ZERO1
19
O
No
No
Zero detect flag output 1
Control port mode selection. Tied to VDD: SPI, ADR6 = 1, pull-up: SPI,
MODE
20
I
No
No
ADR6 = 0, pull-down: H/W auto mode, tied to DGND: I
2
C
Input data for SPI, data for I
2
C
(1)
, de-emphasis control for hardware
MD/SDA/DEMP
21
I/O
No
Yes
control mode
MC/SCL/FMT
22
I
No
Yes
Clock for SPI, clock for I
2
C, format select for hardware control mode
Chip Select for SPI, address select 0 for I
2
C, reserve (set low) for
MS/ADR0/RSV
23
I
Yes
Yes
hardware control mode
Address select 5 for SPI, address select 1 for I
2
C, reserve (set low) for
ADR5/ADR1/RSV
24
I
No
Yes
hardware control mode
(1) Open-drain configuration in out mode.
6
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s):
PCM1789
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