Denon RBD-X1000, Service Manual

Page: 74 / 100

74
SEMICONDUCTORS
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
The semiconductor which described a detailed drawing in a schematic diagram are omitted to list.
1. IC's
R5F3650KNFB (MAIN : IC102)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 18 of 791
Under development
Preliminary Specification
This is a preliminary specification and is subject to change.
M16C/65 Group 1. Overview
Figure 1.8 Pin Assignment (100 pins) (Top View)
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0_0/AN0_0/D0
P0_1/AN0_1/D1
P0_2/AN0_2/D2
P0_3/AN0_3/D3
P0_4/AN0_4/D4
P0_5/AN0_5/D5
P0_6/AN0_6/D6
P0_7/AN0_7/D7
P1_0/CTS6/RTS6/D8
P1_1/CLK6/D9
P1_2/RXD6/SCL6/D10
VREF
AVSS
AVCC
P10_0/AN0
P10_1/AN1
P10_2/AN2
P10_3/AN3
P9_5/ANEX0/CLK4
P9_6/ANEX1/SOUT4
P9_7/ADTRG/SIN4
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
M16C/65 Group
PLQP0100KB-A
(100P6Q-A)
(top view)
P
1_
3/
T
X
D
6/
S
D
A
6/
D
11
P
1_
4/
D
12
P
3_
1/
A
9
P
3_
2/
A
10
P
3_
3/
A
11
P
3_
4/
A
12
P
3_
5/
A
13
P
3_
6/
A
14
P
3_
7/
A
15
P
4_
0/
A
16
P
4_
1/
A
17
V
C
C
2
V
S
S
P4_2/A18
P4_3/A19
P5_6/ALE
P5_5/HOLD
P5_4/HLDA
P5_3/BCLK
P5_2/RD
P5_7/RDY/CLKOUT
P6_3/TXD0/SDA0
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P6_1/CLK0
P6_2/RXD0/SCL0
P6_0/RTCOUT/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P5_0/WRL/WR
P5_1/WRH/BHE
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/SDAMM/TA0OUT (1)
V
C
C
1
X
IN
X
O
U
T
V
S
S
R
E
S
E
T
C
N
V
S
S
P
8_
7/
X
C
IN
P
8_
6/
X
C
O
U
T
B
Y
T
E
P
7_
4/
T
A
2O
U
T
/W
P
9_
3/
D
A
0/
T
B
3I
N
/P
W
M
0
P
9_
4/
D
A
1/
T
B
4I
N
/P
W
M
1
P
9_
1/
T
B
1I
N
/P
M
C
1/
S
IN
3
P
9_
2/
T
B
2I
N
/P
M
C
0/
S
O
U
T
3
P
8_
2/
IN
T
0
P
8_
3/
IN
T
1
P8_5/NMI/SD/
CE
C
(1
)
P
9_
0/
T
B
0I
N
/C
LK
3
P
8_
4/
IN
T
2/
Z
P
P
7_
5/
T
A
2I
N
/W
P
7_
3/
C
T
S
2/
R
T
S
2/
T
A
1I
N
/V
P
7_
6/
T
A
3OU
T
/T
X
D
5/
S
D
A
5
P
7_
7/
T
A
3I
N
/C
LK
5
P
8_
0/
T
A
4O
U
T
/U
/R
X
D
5/S
C
L5
P
8_
1/
T
A
4I
N
/U
/C
T
S
5/
R
T
S
5
P4_5/CLK7/CS1
P4_4/CTS7/RTS7/CS0
P
3_
0/
A
8 [
A
8/
D
7]
P
2_
0/
A
N
2_
0/
A
0,
[A
0/D
0]
, A
0
P
2_
1/
A
N
2_
1/
A
1,
[A
1/
D
1]
, [
A
1/
D
0]
P
2_
2/
A
N
2_
2/
A
2,
[A
2/D
2]
, [
A
2/
D
1]
P
2_
3/
A
N
2_
3/
A
3,
[A
3/D
3]
, [
A
3/
D
2]
P
2_
4/
IN
T
6/
A
N
2_
4/
A
4,
[A
4/
D
4]
, [
A
4/
D
3]
P
2_
5/
IN
T
7/
A
N
2_
5/
A
5,
[A
5/
D
5]
, [
A
5/
D
4]
P
2_
6/
A
N
2_
6/
A
6,
[A
6/
D
6]
, [
A
6/
D
5]
P
2_
7/
A
N
2_
7/
A
7,
[A
7/
D
7]
, [
A
7/
D
6]
(3)
P
1_
5/
IN
T
3/
ID
V
/D
13
P1_6/INT
4/ID
W/D1
4
P
1_
7/
IN
T
5/
ID
U
/D
15
P4_6/PWM0/RXD7/SCL7/CS2
P4_7/PWM1/TXD7/SDA7/CS3
VCC2 ports
VCC1 ports
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.