Glossary
BFLAG
Boot FLAG is the longword supplied in the SET BFLAG and
BOOT /R5: commands that qualify the bootstrap operation.
SHOW BFLAG displays the current value.
BHALT
Q22–bus Halt signal is usually tied to the front panel Halt
switch.
BIP
Boot In Progress flag in CPMBX<2>
Bugcheck
Software or hardware error fatal to VMS processor or system.
Cache memory
A small, high-speed memory placed between slower main
memory and the processor. A cache increases effective memory
transfer rates and processor speed.
CPMBX
Console Program Mailbox is used to pass information between
operating systems and the firmware.
CSR
Control and status register. A device or controller register that
resides in the processor’s I/O space. The CSR initiates device
activity and records its status.
CQBIC
CVAX to Q22–bus interface chip
DCOK
Q22–bus signal indicating dc power is stable. This signal is tied
to the Restart switch on the System Control Panel.
DE
Diagnostic Executive is a component of the ROM-based
diagnostics responsible for setup, execution, and cleanup of
component diagnostic tests.
DNA
Digital Network Architecture
DMA
Direct Memory Access. Access to the memory by an I/O device
that does not require processor intervention.
EPROM
Erasable Programmable Read-Only Memory is used on some
products to store firmware. Commonly used synonyms are
PROM or ROM. Erasable by using ultraviolet light.
Glossary–1
