DEC KA681, System Maintenance

Page: 281 / 358

Address Assignments
B.5 Processor Registers
Table B–1 (Cont.) Processor Registers
Number
Register Name Mnemonic (Dec) (Hex) Type Impl Cat
I/O
Address
I/O System Reset Register IORESET 55 37 W SSC 2-3 E10000DC
Memory Management Enable
1 3
MAPEN 56 38 RW NVAX 1-2
Translation Buffer Invalidate All
3
TBIA 57 39 W NVAX 1-1
Translation Buffer Invalidate
Single
3
TBIS 58 3A W NVAX 1-1
Reserved 59 3B 3 E10000EC
Reserved 60 3C 3 E10000F0
System Identification SID 62 3E R NVAX 1-1
Translation Buffer Check TBCHK 63 3F W NVAX 1-1
IPL 14 Interrupt ACK
5
IAK14 64 40 R SSC 2-3 E1000100
IPL 15 Interrupt ACK
5
IAK15 65 41 R SSC 2-3 E1000104
IPL 16 Interrupt ACK
5
IAK16 66 42 R SSC 2-3 E1000108
IPL 17 Interrupt ACK
5
IAK17 67 43 R SSC 2-3 E100010C
Clear Write Buffer
5
CWB 68 44 RW SSC 2-3 E1000110
Reserved 69–99 45 3 E1000114
Reserved for VM 100 64 3 E1000190
Reserved for VM 101 65 3 E1000194
Reserved for VM 102 66 3 E1000198
Reserved 103–
121
67 3 E100019C
Interrupt System Status Register INTSYS 122 7A RW NVAX 2-1
Performance Monitoring Facility
Count
PMFCNT 123 7B RW NVAX 2-1
Patchable Control Store Control
Register
PCSCR 124 7C WO NVAX 2-1
Ebox Control Register ECR 125 7D RW NVAX 2-1
Mbox TB Tag Fill
5
MTBTAG 126 7E W NVAX 2-1
1
Initialized on reset
3
Change broadcast to vector unit if present
5
Testability and diagnostic use only; not for software use in normal operation
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Address Assignments B–11