Configurable Machine State
PAMODE:
Physical Address Mode Register
(IPR E7)
----------------------------------------
0: Physical address mode
0 = 30-bit physical address space*
PCCTL:
PCache Control Register
(IPR F8)
---------------------------------
8: PCache Electrical disable
0 = PCache enabled*
7:5 MBox performance monitor mode
0 - diagnostic use only*
4: PCache error enable
1 = enables PCache error detection
3: Bank select during force hit mode
0 = left bank selected if force hit mode enabled*
- diagnostic use only
2: Force hit
0 = disabled* - diagnostic use only
1: I_enable
1 = enable PCache for IREAD, INVAL, I_CF commands
0: D_enable
1 = enable PCache for INVAL, D-stream read/write/fill
commands
CCTL:
CBox Control Register
(IPR A0)
-------------------------------
30: Software ETM
0 = disabled* - diagnostic use only
16: Force NDAL parity error
0 = off* - diagnostic use only
15:11: Performance monitoring BCache access and hit type
0 - configures BCache for performance monitoring* -
meaningful only during performance monitoring
10: Disable CBox write packer
0 = write packer enabled* - improves write latency
9: Read timeout counter test
0 = test disabled* - use external time base for read
timeout counter
8: Software ECC
0 = use correct ECC*
7: Disable BCache errors
0 = BCache errors detected*
6:
Force Hit
0 = disabled* - diagnostic use only
Configurable Machine State E–5
