Data Translation DT9800 Series, User Manual

Page: 86 / 162

Chapter 3
74
Counter/Timers (cont.)
Low Edge Gate Type with Input
Debounce Support
OLSSC_SUP_GATE_LOW_EDGE_
DEBOUNCE
Level Change Gate Type with Input
Debounce Support
OLSSC_SUP_GATE_LEVEL_
DEBOUNCE
Inter
rupt
Interrupt Support
OLSSC_SUP_INTERRUPT
FI
F
O
s
FIFO in Data Path Support
OLSSC_SUP_FIFO
Processor
Data Processing Capability
OLSSC_SUP_PROCESSOR
Softw
ar
e
Ca
libr
ation
Software Calibration Support
OLSSC_SUP_SWCAL Yes Yes
a. D/A subsystems are supported by the DT9802, DT9802-MAC, DT9802-EC, DT9802-EC-I,
DT9804, DT9804-MAC, DT9804-EC, DT9804-EC-I, and DT9806 modules only.
b. While the DIN subsystem itself is incapable of continuous operation, you can perform a con-
tinuous DIN operation by specifying channel 16 in the channel-gain list of the A/D subsystem
and starting the A/D subsystem. All 8 bits of the digital input lines from Port A are assigned to
A/D input channel 16.
c. The maximum retrigger frequency for all modules except the DT9805 and DT9806 is 100 kHz.
The DT9805 and DT9806 modules support a maximum retrigger frequency of 50 kHz. The
appropriate retrigger frequency to use depends on the number of samples in the channel-gain
list and the A/D sample clock frequency, as follows:
Min. Retrigger = # of CGL entries + 2
µ
s
Period A/D sample clock frequency
Max. Retrigger = 1
Frequency
Min. Retrigger Period
d. The value of 0.75 Hz assumes the minimum number of samples is 1.
Table 13: DT9800 Series Supported Options (cont.)
DT9800 Series A/D D/A
a
DIN DOUT SRL C/T
Total Subsystems on Module 1 1 1 1 0 2