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Index
143
gates, how to set for C/T operations
GCL depth
generating continuous pulses
H
HES14-21 power supply
high-edge gate type
high-level gate type
high-to-low pulse output
I
inprocess buffers
input ranges
internal clock
A/D sample
C/T
cascaded C/T
internal gate type
internal retrigger
internal retrigger clock
internally retriggered scan mode
J
J1 connector pin assignments
L
LabVIEW
level gate type
high
low
logic-high level gate type
logic-low level gate type
LongtoFreq macro
low-edge gate type
low-level gate type
low-to-high pulse output
M
macro
measuring frequency
messages
dealing with
dealing with for A/D operations
OLDA_WM_BUFFER_ DONE
OLDA_WM_BUFFER_DONE
OLDA_WM_BUFFER_REUSED
OLDA_WM_OVERRUN
OLDA_WM_PRETRIGGER_
BUFFER_DONE
OLDA_WM_QUEUE_DONE
OLDA_WM_QUEUE_STOPPED
OLDA_WM_TRIGGERERROR
multiple buffer wrap mode
N
number of
differential channels
DMA channels
extra clocks
extra triggers
filters
gains
I/O channels
resolutions
scans per trigger
single-ended channels
voltage ranges
Nyquist Theorem
Summary of Contents for DT9800 Series
Page 1: ...DT9800 Series UM 17473 L User s Manual ...
Page 4: ......
Page 13: ...1 1 Overview Features 2 Supported Software 7 Accessories 9 ...
Page 76: ...Chapter 2 64 ...
Page 77: ...65 3 Supported Device Driver Capabilities ...
Page 88: ...Chapter 3 76 ...
Page 112: ...Chapter 4 100 ...
Page 131: ...119 A Specifications ...
Page 143: ...131 B Connector Pin Assignments ...
Page 162: ...Index 150 ...