Dalsa PC2-CamLink, User Manual

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PC2-CamLink User's Manual Part I: PC2-CamLink Board
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Camera Control and Synchronization
FVAL, LVAL, and DVAL
LVAL is the line valid input. The rising edge of LVAL enables and clocks the horizontal offset and
clocks the horizontal active counters in the valid video window generator. This indicates a valid line is
output by the camera.
FVAL is the frame valid input. The rising edge of FVAL enables and clocks the vertical offset and
vertical active counters in the valid video window generator. This indicates a valid frame is output by
the camera.
DVAL is the data valid input, similar to a sample clock or pixel clock. The rising edge of DVAL
writes data into the Camera Link™ receivers.
Note : CameraLink specifies a minimum clock of 20MHz. If a camera does not reach this bandwidth, it
can use DVAL to indicate which data are actually valid (other data are dummy data and only are used
to increase bandwidth above the 20MHz limit). Typically, DVAL is not used in your camera
configuration file if the camera clock is above 20MHz.
SPR is the spare input, defined by the Camera Link™ specification. This input is reserved for future
use by the Camera Link™ standard.
The Camera Link™ transmission clock is recovered from the Camera Link™ interface.
Sapera Parameters for FVAL, LVAL and DVAL:
CORACQ_PRM_DATA_VALID_ENABLE = {TRUE, FALSE}
CORACQ_PRM_SCAN = { CORACQ_VAL_SCAN_AREA,
CORACQ_VAL_SCAN_LINE}
Note: In Sapera, polarity of FVAL, LVAL and DVAL follows the CameraLink standard
(always active high).
In CamExpert, these parameters are located under the ‘Basic Timing Parameters’ tab.
IFC
IFC Parameters for FVAL, LVAL and DVAL:
P_LEN_POLARITY = IFC_RISING_EDGE
P_FEN_ENABLE = {IFC_DISABLE, IFC_ENABLE}
P_FEN_POLARITY = IFC_RISING_EDGE
CL2_DVAL_ENABLE = {IFC_DISABLE, IFC_ENABLE}
CL2_DVAL_INPUT_MODE = CL2_DVAL_INPUT_VALID_DATA
Note: In IFC, the P_FEN_ENABLE parameter indicates if the camera is area scan
(P_FEN_ENABLE = IFC_ENABLE) or linescan (P_FEN_ENABLE = IFC_DISABLE).