MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D
Page 151 of 172
(V
CC
= 3.0 V to 5.5 V, AV
SS
= V
SS
= 0.0 V, T
A
=
−
40 °C to
+
85 °C)
Parameter Symbol Pin
name Condition
Value*
2
Unit
Remarks
Min
Max
SCL clock
“L” width
t
LOW
SCL
R = 1.7 k
Ω
,
C = 50 pF*
1
(2
+
nm/2)t
MCLK
−
20
—
ns Master mode
SCL clock
“H” width
t
HIGH
SCL
(nm/2)t
MCLK
−
20
(nm/2)t
MCLK
+
20
ns Master mode
START
condition
hold time
t
HD;STA
SCL,
SDA
(-1
+
nm/2)t
MCLK
−
20 (-1
+
nm)t
MCLK
+
20
ns
Master mode
Maximum value
is applied when
m, n = 1, 8.
Otherwise, the
minimum value is
applied.
STOP
condition
setup time
t
SU;STO
SCL,
SDA
(1
+
nm/2)t
MCLK
−
20 (1
+
nm/2)t
MCLK
+
20 ns Master mode
START
condition
setup time
t
SU;STA
SCL,
SDA
(1
+
nm/2)t
MCLK
−
20 (1
+
nm/2)t
MCLK
+
20 ns Master mode
Bus free time
between
STOP
condition
and START
condition
t
BUF
SCL,
SDA
(2 nm
+
4)t
MCLK
−
20
—
ns
Data hold
time
t
HD;DAT
SCL,
SDA
3 t
MCLK
−
20
—
ns Master mode
Data setup
time
t
SU;DAT
SCL,
SDA
(-2
+
nm/2)t
MCLK
−
20 (-1
+
nm/2)t
MCLK
+
20 ns
Master mode
It is assumed that
“L” of SCL is not
extended. The
minimum value is
applied to the first
bit of continuous
data. Otherwise,
the maximum
value is applied.
Setup time
between
clearing
interrupt and
SCL rising
t
SU;INT
SCL
(nm/2)t
MCLK
−
20
(1
+
nm/2)t
MCLK
+
20 ns
The minimum
value is applied
to the interrupt at
the ninth SCL
↓
.
The maximum
value is applied
to the interrupt at
the eighth SCL
↓
.
SCL clock
“L” width
t
LOW
SCL
4 t
MCLK
−
20
—
ns At reception
SCL clock
“H” width
t
HIGH
SCL
4 t
MCLK
−
20
—
ns At reception
