Cypress MB95710M Series, Manual

Page: 151 / 174

MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D Page 150 of 172
22.4.7 I
2
C Bus Interface Timing
(V
CC
= 3.0 V to 5.5 V, AV
SS
= V
SS
= 0.0 V, T
A
=
−
40 °C
to
+
85 °C)
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: The maximum t
HD;DAT
in the Standard-mode is applicable only when the time during which the device is holding the
SCL signal at “L” (t
LOW
) does not extend.
*3: A Fast-mode I 2 C-bus device can be used in a Standard-mode I 2 C-bus system, provided that the condition of t
SU;DAT
≥
250 ns is fulfilled.
Parameter Symbol Pin name Condition
Value
Unit
Standard-
mode
Fast-mode
Min Max Min Max
SCL clock frequency f
SCL
SCL
R = 1.7 k
Ω
,
C = 50 pF* 1
0 100 0 400 kHz
(Repeated) START condition hold
time
SDA
↓ →
SCL
↓
t
HD;STA
SCL, SDA 4.0 — 0.6 — µs
SCL clock “L” width t
LOW
SCL 4.7 — 1.3 — µs
SCL clock “H” width t
HIGH
SCL 4.0 — 0.6 — µs
(Repeated) START condition setup
time
SCL
↑ →
SDA
↓
t
SU;STA
SCL, SDA 4.7 — 0.6 — µs
Data hold time
SCL
↓ →
SDA
↓↑
t
HD;DAT
SCL, SDA 0 3.45 *2 0 0.9 *3 µs
Data setup time
SDA
↓↑ →
SCL
↑
t
SU;DAT
SCL, SDA 0.25 — 0.1 — µs
STOP condition setup time
SCL
↑ →
SDA
↑
t
SU;STO
SCL, SDA 4 — 0.6 — µs
Bus free time between STOP
condition and START condition
t
BUF
SCL, SDA 4.7 — 1.3 — µs
SDA
SCL
t
WAKEUP
t
HD;STA
t
SU;DAT
f
SCL
t
HD;STA
t
SU;STA
t
LOW
t
HD;DAT
t
HIGH
t
SU;STO
t
BUF