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MB95710M Series
MB95770M Series

Document Number: 002-09307 Rev. *D

Page 130 of 172

*9: On the MB95770M Series, TO00 is assigned to P01, TO0 to P10, TO01 to P13, and EC0 and TI0 to P14.
*10: Though input is blocked, an external interrupt can be input when the external interrupt request is enabled.
*11: The output function of the comparator is still in operation in stop mode and watch mode.
*12: Though input is blocked, an analog signal can also be input to generate a comparator interrupt when the comparator

interrupt is enabled.

*13: The I

2

C bus interface can wake up the MCU in stop mode or watch mode when its MCU standby mode wakeup

function is enabled. For details of the MCU standby mode wakeup function, refer to “CHAPTER 23 I

2

C BUS INTER-

FACE” in “New 8FX MB95710M/770M Series Hardware Manual”.

*14: P40/SEG21, P41/SEG20, P42/SEG19, P43/SEG18, P50/TO01, P51/EC0, P52/TI0/TO00, P53/TO0, P94/V0,

PB2/SEG37, PB3/SEG38, PB4/SEG39, PC4/SEG06, PC5/SEG07, PC6/SEG08 and PC7/SEG09 are only avail-
able on the MB95710M Series.

SEG17

P67

PE3

SEG18

P43

PE4

SEG19

P42

PE5

SEG20

P41

PE6

SEG21

P40

PE7

SEG22

PE0

P07

SEG23

PE1

P06

SEG24

PE2

P05

SEG25

PE3

P04

SEG26

PE4

P03

SEG27

PE5

P02

SEG28

PE6

P01

SEG29

PE7

P00

SEG30

P07

P16

SEG31

P06

P15

SEG32

P05

—

SEG33

P04

—

SEG34

P03

—

SEG35

P02

—

SEG36

P01

—

SEG output

Pin on MB95710M Series

Pin on MB95770M Series

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Summary of Contents for MB95710M Series

Page 1: ...ch has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions About Cypress Cypress is the leader in advance...

Page 2: ...IO 3 channels Full duplex double buffer Capable of clock asynchronous UART serial data transfer and clock synchronous SIO serial data transfer I2 C bus interface 1 channel Built in wake up function Ex...

Page 3: ...F776J F778J Built in low voltage detection function Comparator 1 channel Clock supervisor counter Built in clock supervisor counter Dual operation Flash memory The program erase operation and the rea...

Page 4: ...9 17 I O Map MB95770M Series 45 18 I O Ports MB95710M Series 51 18 1 Port 0 52 18 2 Port 1 56 18 3 Port 2 61 18 4 Port 4 64 18 5 Port 5 66 18 6 Port 6 69 18 7 Port 9 72 18 8 Port A 74 18 9 Port B 77 1...

Page 5: ...O I O port 75 CMOS I O 71 N ch open drain 4 I O port 74 CMOS I O 71 N ch open drain 3 Time base timer Interval time 0 256 ms to 8 3 s external clock frequency 4 MHz Hardware software watchdog timer Re...

Page 6: ...counter operating modes reload mode and one shot mode Event counter The event counter function is implemented by configuring the 16 bit reload timer and 8 16 bit com posite timer ch 1 When the event c...

Page 7: ...the completion of the operation of Embedded Algorithm Flash security feature for protecting the content of the Flash memory Standby mode There are four standby modes as follows Stop mode Sleep mode W...

Page 8: ...I O 55 N ch open drain 4 I O port 58 CMOS I O 55 N ch open drain 3 Time base timer Interval time 0 256 ms to 8 3 s external clock frequency 4 MHz Hardware software watchdog timer Reset generation cyc...

Page 9: ...counter operating modes reload mode and one shot mode Event counter The event counter function is implemented by configuring the 16 bit reload timer and 8 16 bit com posite timer ch 1 When the event c...

Page 10: ...feature for protecting the content of the Flash memory Standby mode There are four standby modes as follows Stop mode Sleep mode Watch mode Time base timer mode Package LQD064 LQG064 Part number Packa...

Page 11: ...etails of information on each package see Packages And Corresponding Products and Package Dimension Operating voltage The operating voltage varies depending on whether the on chip debug function is us...

Page 12: ...P11 UO0 P10 UI0 P53 TO0 P52 TI0 TO00 P51 EC0 P50 TO01 P13 ADTG P22 SCL P21 PPG01 CMP0_P P20 PPG00 CMP0_N P90 V4 P91 V3 P92 V2 P93 V1 P94 V0 PB2 SEG37 PB3 SEG38 PB4 SEG39 P23 SDA PA1 COM1 PA2 COM2 PA3...

Page 13: ...1 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVcc P12 DBG P11 UO0 P10 UI0 TO0 P13 ADTG TO01 P22 SCL P21 PPG01 CMP0_P P20 PPG00 CMP0_N P90 V4 P91 V3 P92 V2 P93 V1 P23 SDA PA1 COM1 PA2 COM2 PA3...

Page 14: ...12 bit A D converter analog input pin SEG32 LCDC SEG32 output pin UCK1 UART SIO ch 1 clock I O pin 5 P04 V General purpose I O port CMOS analog CMOS LCD INT04 External interrupt input pin AN04 8 12 bi...

Page 15: ...IO ch 0 data output pin 16 P10 G General purpose I O port CMOS CMOS UI0 UART SIO ch 0 data input pin 17 P53 H General purpose I O port Hysteresis CMOS TO0 16 bit reload timer ch 0 output pin 18 P52 H...

Page 16: ...LCD drive power supply pin 29 P94 R General purpose I O port Hysteresis LCD power supply CMOS LCD power supply V0 LCD drive power supply pin 30 PB2 M General purpose I O port Hysteresis CMOS LCD SEG3...

Page 17: ...ock input oscillation pin 47 VCC Power supply pin 48 PF2 A General purpose I O port Hysteresis CMOS RST Reset pin Dedicated reset pin on MB95F714M F716M F718M 49 P17 H General purpose I O port Hystere...

Page 18: ...DC SEG14 output pin 65 P65 M General purpose I O port Hysteresis CMOS LCD SEG15 LCDC SEG15 output pin 66 P66 M General purpose I O port Hysteresis CMOS LCD SEG16 LCDC SEG16 output pin 67 P67 M General...

Page 19: ...PE5 M General purpose I O port Hysteresis CMOS LCD SEG27 LCDC SEG27 output pin TO11 8 16 bit composite timer ch 1 output pin 78 PE6 M General purpose I O port Hysteresis CMOS LCD SEG28 LCDC SEG28 out...

Page 20: ...alog input pin SEG24 LCDC SEG24 output pin UCK1 UART SIO ch 1 clock I O pin 5 P04 V General purpose I O port CMOS analog CMOS LCD INT04 External interrupt input pin AN04 8 12 bit A D converter analog...

Page 21: ...CMOS ADTG 8 12 bit A D converter trigger input pin TO01 8 16 bit composite timer ch 0 output pin 14 P12 D General purpose I O port Hysteresis CMOS DBG DBG input pin 15 P11 H General purpose I O port...

Page 22: ...tput pin 27 PA2 M General purpose I O port Hysteresis CMOS LCD COM2 LCDC COM2 output pin 28 PA3 M General purpose I O port Hysteresis CMOS LCD COM3 LCDC COM3 output pin 29 PA4 M General purpose I O po...

Page 23: ...output pin 46 PC2 M General purpose I O port Hysteresis CMOS LCD SEG04 LCDC SEG04 output pin 47 PC3 M General purpose I O port Hysteresis CMOS LCD SEG05 LCDC SEG05 output pin 48 P60 M General purpose...

Page 24: ...s CMOS LCD SEG17 LCDC SEG17 output pin 60 PE4 M General purpose I O port Hysteresis CMOS LCD SEG18 LCDC SEG18 output pin 61 PE5 M General purpose I O port Hysteresis CMOS LCD SEG19 LCDC SEG19 output p...

Page 25: ...Pull up control N ch Reset output Digital output Reset input Hysteresis input Standby control Port select Clock input Port select Digital output Digital output Standby control Hysteresis input Digita...

Page 26: ...wer supply Hysteresis input N ch Standby control Hysteresis input Digital output N ch P ch P ch R Pull up control Digital output Digital output Standby control CMOS input N ch P ch P ch R Pull up cont...

Page 27: ...ol V CMOS output CMOS input LCD output Analog input N ch P ch Digital output Digital output Analog input LCD output LCD control A D control Standby control Hysteresis input N ch P ch R Pull up control...

Page 28: ...2 W CMOS output Hysteresis input Analog input Y CMOS output Hysteresis input Type Circuit Remarks N ch P ch Digital output Digital output Analog input Analog input control Standby control Hysteresis i...

Page 29: ...ins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input output functions 1 Preventing Over Voltage and Over Current Conditions Expos...

Page 30: ...ype or surface mount type In either case for heat resistance during soldering you should only mount under Cypress s recommended conditions For detailed information about mount conditions contact your...

Page 31: ...lectricity you must take the following precautions 1 Maintain relative humidity in the working environment between 40 and 70 Use of an apparatus for ion generation may be needed to remove electricity...

Page 32: ...though the fluctuation is within the guar anteed operating range of the VCC power supply voltage As a rule of voltage stabilization suppress voltage fluctuation so that the fluctuation in VCC ripple p...

Page 33: ...CC is larger than AVCC the current may flow through the AN00 to AN07 pins Treatment of power supply pins on the 8 12 bit A D converter Ensure that AVCC is equal to VCC and AVSS equal to VSS even when...

Page 34: ...P02 UCK2 P00 UO2 P01 UI2 P20 PPG00 P21 PPG01 P15 PPG11 P16 PPG10 P22 1 SCL P23 1 SDA P12 1 DBG P52 TO00 P50 TO01 P51 EC0 P00 AN00 to P07 AN07 P13 ADTG LCDC 4 COM or 8 COM P90 V4 to P94 V0 PA0 COM0 to...

Page 35: ...1 P04 UI1 UART SIO ch 2 P02 UCK2 P00 UO2 P01 UI2 P20 PPG00 P21 PPG01 P16 PPG10 P15 PPG11 P22 1 SCL P23 1 SDA P12 1 DBG P01 TO00 P13 TO01 P14 EC0 P00 AN00 to P07 AN07 P13 ADTG LCDC 4 COM or 8 COM P90 V...

Page 36: ...ea Access prohibited 0x0000 0x0080 0x0090 Registers 0x0100 0x0200 Flash memory 4 Kbyte 0x1000 0x2000 Flash memory 4 Kbyte Extended I O area 0x0F80 0x1000 Access prohibited Access prohibited 0x8000 0x2...

Page 37: ...accessed in the same way as the memory Data area Static RAM is incorporated in the data area as the internal data area The internal RAM size varies according to product The RAM area from 0x0090 to 0x...

Page 38: ...ap Direct addressing area Extended direct addressing area I O area Access prohibited 0x0000 0x0080 0x0090 Registers General purpose register area 0x0100 0x0200 0x047F Vector table area Extended I O ar...

Page 39: ...o 0xFFFF This area is used as the vector table for vector call instructions CALLV interrupts and resets The top of the Flash memory area is allocated to the vector table area The start address of a se...

Page 40: ...00C WDTC Watchdog timer control register R W 0b00XX0000 0x000D SYCC2 System clock control register 2 R W 0bXXXX0011 0x000E PDR2 Port 2 data register R W 0b00000000 0x000F DDR2 Port 2 direction registe...

Page 41: ...10CR1 8 16 bit composite timer 10 status control register 1 R W 0b00000000 0x003A PC01 8 16 bit PPG timer 01 control register R W 0b00000000 0x003B PC00 8 16 bit PPG timer 00 control register R W 0b00...

Page 42: ...R0 I2 C clock control register ch 0 R W 0b00000000 0x0066 SMC12 UART SIO serial mode control register 1 ch 2 R W 0b00000000 0x0067 SMC22 UART SIO serial mode control register 2 ch 2 R W 0b00100000 0x0...

Page 43: ...ch 2 R W 0b00000000 0x0F88 WRDR2 Wild register data setting register ch 2 R W 0b00000000 0x0F89 to 0x0F91 Disabled 0x0F92 T01CR0 8 16 bit composite timer 01 status control register 0 R W 0b00000000 0...

Page 44: ...rescaler select register ch 1 R W 0b00000000 0x0FAB BRSR1 UART SIO dedicated baud rate generator baud rate setting register ch 1 R W 0b00000000 0x0FAC PSSR2 UART SIO dedicated baud rate generator pres...

Page 45: ...b00000000 0x0FE7 CRTDA Main CR clock temperature dependent adjustment register R W 0b000XXXXX 0x0FE8 SYSC System configuration register R W 0b00111111 0x0FE9 CMCR Clock monitoring control register R W...

Page 46: ...gister R W 0b00000000 0x000C WDTC Watchdog timer control register R W 0b00XX0000 0x000D SYCC2 System clock control register 2 R W 0bXXXX0011 0x000E PDR2 Port 2 data register R W 0b00000000 0x000F DDR2...

Page 47: ...000 0x003D PC10 8 16 bit PPG timer 10 control register R W 0b00000000 0x003E TMCSRH0 16 bit reload timer control status register upper ch 0 R W 0b00000000 0x003F TMCSRL0 16 bit reload timer control st...

Page 48: ...DR2 UART SIO serial input data register ch 2 R 0b00000000 0x006B ADC3 8 12 bit A D converter control register 3 R W 0b01111100 0x006C ADC1 8 12 bit A D converter control register 1 R W 0b00000000 0x00...

Page 49: ...x0F96 TMCR0 8 16 bit composite timer 00 01 timer mode control register R W 0b00000000 0x0F97 T11CR0 8 16 bit composite timer 11 status control register 0 R W 0b00000000 0x0F98 T10CR0 8 16 bit composit...

Page 50: ...disable register lower R W 0b00000000 0x0FB0 LCDCC1 LCDC control register 1 R W 0b00000000 0x0FB1 Disabled 0x0FB2 LCDCE1 LCDC enable register 1 R W 0b00111110 0x0FB3 LCDCE2 LCDC enable register 2 R W...

Page 51: ...CR Clock monitoring control register R W 0b00000000 0x0FEA CMDR Clock monitoring data register R 0b00000000 0x0FEB WDTH Watchdog timer selection ID register upper R 0bXXXXXXXX 0x0FEC WDTL Watchdog tim...

Page 52: ...t 5 direction register DDR5 R W 0b00000000 Port 6 data register PDR6 R RM W 0b00000000 Port 6 direction register DDR6 R W 0b00000000 Port 9 data register PDR9 R RM W 0b00000000 Port 9 direction regist...

Page 53: ...is pin has the following peripheral functions External interrupt input pin INT02 8 12 bit A D converter analog input pin AN02 LCDC SEG35 output pin SEG35 UART SIO ch 2 clock I O pin UCK2 P03 INT03 AN0...

Page 54: ...T SIO ch 2 data input pin UI2 P04 INT04 AN04 SEG33 UI1 pin This pin has the following peripheral functions External interrupt input pin INT04 8 12 bit A D converter analog input pin AN04 LCDC SEG33 ou...

Page 55: ...s 1 As output port outputs H level DDR0 0 Port input enabled 1 Port output enabled AIDRL 0 Analog input enabled 1 Port input enabled Correspondence between related register bits and pins Pin name P07...

Page 56: ...CDC enable register 7 LCDCE7 SEG 36 32 to 0 to select the gen eral purpose I O port function and then set the PICTL bit in the LCDCE1 register to 1 Operation as a peripheral function output pin A pin...

Page 57: ...ter to 0 For a pin shared with other peripheral functions disable the output of such peripheral functions Operation as an external interrupt input pin Set the bit in the DDR0 register corresponding to...

Page 58: ...P12 DBG PDR1 Pin PDR1 read PDR1 write Executing bit manipulation instruction DDR1 read DDR1 write PUL1 read PUL1 write DDR1 PUL1 0 1 Stop mode watch mode SPL 1 Peripheral function input Peripheral fun...

Page 59: ...ng peripheral function UART SIO ch 0 clock I O pin UCK0 P17 CMP0_O pin This pin has the following peripheral function Comparator ch 0 digital output pin CMP0_O Block diagram of P11 UO0 P13 ADTG P14 UC...

Page 60: ...rt 1 Register abbreviation Data Read Read by read modify write RMW instruction Write PDR1 0 Pin state is L level PDR1 value is 0 As output port outputs L level 1 Pin state is H level PDR1 value is 1 A...

Page 61: ...the PDR1 register However if the read modify write RMW type of instruction is used to read the PDR1 register the PDR1 register value is returned Operation as a peripheral function input pin To set a...

Page 62: ...register PUL2 18 3 2 Block diagrams of port 2 P20 PPG00 CMP0_N pin This pin has the following peripheral functions 8 16 bit PPG ch 0 output pin PPG00 Comparator ch 0 inverting analog input negative in...

Page 63: ...abbreviation Data Read Read by read modify write RMW instruction Write PDR2 0 Pin state is L level PDR2 value is 0 As output port outputs L level 1 Pin state is H level PDR2 value is 1 As output port...

Page 64: ...struction is used to read the PDR2 register the PDR2 register value is returned Operation as a peripheral function input pin To set a pin as an input port set the bit in the DDR2 register correspondin...

Page 65: ...ster PDR4 Port 4 direction register DDR4 18 4 2 Block diagrams of port 4 P40 SEG21 pin This pin has the following peripheral function LCDC SEG21 output pin SEG21 P41 SEG20 pin This pin has the followi...

Page 66: ...written to the PDR4 register the value is stored in the output latch but is not output to the pin set as an input port Reading the PDR4 register returns the pin value However if the read modify write...

Page 67: ...on its functions as a general purpose I O port For details of peripheral functions refer to their respective chapters in New 8FX MB95710M 770M Series Hardware Manual 18 5 1 Port 5 configuration Port 5...

Page 68: ...puts L level 1 Pin state is H level PDR5 value is 1 As output port outputs H level DDR5 0 Port input enabled 1 Port output enabled PUL5 0 Pull up disabled 1 Pull up enabled Correspondence between rela...

Page 69: ...register even if the peripheral function output is enabled Therefore the output value of a peripheral function can be read by the read operation on the PDR5 register However if the read modify write...

Page 70: ...f port 6 P60 SEG10 pin This pin has the following peripheral function LCDC SEG10 output pin SEG10 P61 SEG11 pin This pin has the following peripheral function LCDC SEG11 output pin SEG11 P62 SEG12 pin...

Page 71: ...write RMW instruction Write PDR6 0 Pin state is L level PDR6 value is 0 As output port outputs L level 1 Pin state is H level PDR6 value is 1 As output port outputs H level DDR6 0 Port input enabled...

Page 72: ...eturns the pin value However if the read modify write RMW type of instruction is used to read the PDR6 register the PDR6 register value is returned To use a pin shared with the LCDC as an input port s...

Page 73: ...2 Block diagrams of port 9 P90 V4 pin This pin has the following peripheral function LCD drive power supply pin V4 P91 V3 pin This pin has the following peripheral function LCD drive power supply pin...

Page 74: ...t the bit corresponding to that pin in the VE 4 0 bits in the LCDCE1 register to 0 to select the general purpose I O port function Operation at reset If the CPU is reset all bits in the DDR9 register...

Page 75: ...k diagrams of port A PA0 COM0 pin This pin has the following peripheral function LCDC COM0 output pin COM0 PA1 COM1 pin This pin has the following peripheral function LCDC COM1 output pin COM1 PA2 COM...

Page 76: ...te RMW instruction Write PDRA 0 Pin state is L level PDRA value is 0 As output port outputs L level 1 Pin state is H level PDRA value is 1 As output port outputs H level DDRA 0 Port input enabled 1 Po...

Page 77: ...Reading the PDRA register returns the pin value However if the read modify write RMW type of instruction is used to read the PDRA register the PDRA register value is returned To use a pin shared with...

Page 78: ...ock diagrams of port B PB0 SEG00 pin This pin has the following peripheral function LCDC SEG00 output pin SEG00 PB1 SEG01 pin This pin has the following peripheral function LCDC SEG01 output pin SEG01...

Page 79: ...ripheral functions If data is written to the PDRB register the value is stored in the output latch but is not output to the pin set as an input port Reading the PDRB register returns the pin value How...

Page 80: ...etails of peripheral functions refer to their respective chapters in New 8FX MB95710M 770M Series Hardware Manual 18 10 1 Port C configuration Port C is made up of the following elements General purpo...

Page 81: ...write RMW instruction Write PDRC 0 Pin state is L level PDRC value is 0 As output port outputs L level 1 Pin state is H level PDRC value is 1 As output port outputs H level DDRC 0 Port input enabled...

Page 82: ...eturns the pin value However if the read modify write RMW type of instruction is used to read the PDRC register the PDRC register value is returned To use a pin shared with the LCDC as an input port s...

Page 83: ...Block diagrams of port E PE0 SEG22 pin This pin has the following peripheral function LCDC SEG22 output pin SEG22 PE1 SEG23 pin This pin has the following peripheral function LCDC SEG23 output pin SEG...

Page 84: ...rs Port E register functions Correspondence between registers and pins for port E Register abbreviation Data Read Read by read modify write RMW instruction Write PDRE 0 Pin state is L level PDRE value...

Page 85: ...bit in the LCDCE1 register to 1 Operation as a peripheral function output pin A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable...

Page 86: ...FX MB95710M 770M Series Hardware Manual 18 12 1 Port F configuration Port F is made up of the following elements General purpose I O pins peripheral function I O pins Port F data register PDRF Port F...

Page 87: ...F718M Register abbreviation Data Read Read by read modify write RMW instruction Write PDRF 0 Pin state is L level PDRF value is 0 As output port outputs L level 1 Pin state is H level PDRF value is 1...

Page 88: ...value is returned Operation at reset If the CPU is reset all bits in the DDRF register are initialized to 0 and port input is enabled Operation in stop mode and watch mode If the pin state setting bi...

Page 89: ...Pin state is L level PDRG value is 0 As output port outputs L level 1 Pin state is H level PDRG value is 1 As output port outputs H level DDRG 0 Port input enabled 1 Port output enabled PULG 0 Pull up...

Page 90: ...ch but is not output to the pin set as an input port Reading the PDRG register returns the pin value However if the read modify write RMW type of instruction is used to read the PDRG register the PDRG...

Page 91: ...R RM W 0b00000000 Port 6 direction register DDR6 R W 0b00000000 Port 9 data register PDR9 R RM W 0b00000000 Port 9 direction register DDR9 R W 0b00000000 Port A data register PDRA R RM W 0b00000000 P...

Page 92: ...SEG27 UCK2 pin This pin has the following peripheral functions External interrupt input pin INT02 8 12 bit A D converter analog input pin AN02 LCDC SEG27 output pin SEG27 UART SIO ch 2 clock I O pin U...

Page 93: ...imer ch 0 output pin TO00 UART SIO ch 2 data input pin UI2 P04 INT04 AN04 SEG25 UI1 pin This pin has the following peripheral functions External interrupt input pin INT04 8 12 bit A D converter analog...

Page 94: ...e is 1 As output port outputs H level DDR0 0 Port input enabled 1 Port output enabled AIDRL 0 Analog input enabled 1 Port input enabled Correspondence between related register bits and pins Pin name P...

Page 95: ...CDC enable register 6 LCDCE6 SEG 29 24 to 0 to select the gen eral purpose I O port function and then set the PICTL bit in the LCDCE1 register to 1 Operation as a peripheral function output pin A pin...

Page 96: ...ed with other peripheral functions disable the output of such peripheral functions Operation as an external interrupt input pin Set the bit in the DDR0 register corresponding to the external interrupt...

Page 97: ...1 write Executing bit manipulation instruction DDR1 read DDR1 write PUL1 read PUL1 write DDR1 PUL1 0 1 1 0 Stop mode watch mode SPL 1 Peripheral function input Peripheral function input enable Periphe...

Page 98: ...ns UART SIO ch 0 clock I O pin UCK0 8 16 bit composite timer ch 0 clock input pin EC0 16 bit reload timer ch 0 input pin TI0 P17 CMP0_O pin This pin has the following peripheral function Comparator ch...

Page 99: ...n registers and pins for port 1 Register abbreviation Data Read Read by read modify write RMW instruction Write PDR1 0 Pin state is L level PDR1 value is 0 As output port outputs L level 1 Pin state i...

Page 100: ...t a corresponding function select bit in the LCDC enable register 6 LCDCE6 SEG 31 30 to 0 to select the general purpose I O port function and then set the PICTL bit in the LCDCE1 register to 1 Operati...

Page 101: ...level is maintained Operation of the pull up register Setting the bit in the PUL1 register to 1 makes the pull up resistor be internally connected to the pin When the pin output is L level the pull up...

Page 102: ...SCL and P23 SDA PDR2 Pin PDR2 read PDR2 write Executing bit manipulation instruction DDR2 read DDR2 write PUL2 read PUL2 write DDR2 PUL2 0 1 1 0 Stop mode watch mode SPL 1 Peripheral function output e...

Page 103: ...port Reading the PDR2 register returns the pin value However if the read modify write RMW type of instruction is used to read the PDR2 register the PDR2 register value is returned Operation as a perip...

Page 104: ...is L level the pull up resistor is disconnected regardless of the value of the PUL2 register Operation as a comparator input pin Regardless of the value of the PDR2 register and that of the DDR2 regi...

Page 105: ...P66 SEG12 and P67 SEG13 19 4 3 Port 6 registers Port 6 register functions Correspondence between registers and pins for port 6 Register abbreviation Data Read Read by read modify write RMW instruction...

Page 106: ...eturns the pin value However if the read modify write RMW type of instruction is used to read the PDR6 register the PDR6 register value is returned To use a pin shared with the LCDC as an input port s...

Page 107: ...gister PDR9 Port 9 direction register DDR9 19 5 2 Block diagrams of port 9 P90 V4 pin This pin has the following peripheral function LCD drive power supply pin V4 P91 V3 pin This pin has the following...

Page 108: ...rt set the bit corresponding to that pin in the VE 4 1 bits in the LCDCE1 register to 0 to select the general purpose I O port function Operation at reset If the CPU is reset all bits in the DDR9 regi...

Page 109: ...ck diagrams of port A PA0 COM0 pin This pin has the following peripheral function LCDC COM0 output pin COM0 PA1 COM1 pin This pin has the following peripheral function LCDC COM1 output pin COM1 PA2 CO...

Page 110: ...te RMW instruction Write PDRA 0 Pin state is L level PDRA value is 0 As output port outputs L level 1 Pin state is H level PDRA value is 1 As output port outputs H level DDRA 0 Port input enabled 1 Po...

Page 111: ...Reading the PDRA register returns the pin value However if the read modify write RMW type of instruction is used to read the PDRA register the PDRA register value is returned To use a pin shared with...

Page 112: ...up of the following elements General purpose I O pins peripheral function I O pins Port B data register PDRB Port B direction register DDRB 19 7 2 Block diagrams of port B PB0 SEG00 pin This pin has t...

Page 113: ...If data is written to the PDRB register the value is stored in the output latch but is not output to the pin set as an input port Reading the PDRB register returns the pin value However if the read mo...

Page 114: ...9 8 Port C Port C is a general purpose I O port This section focuses on its functions as a general purpose I O port For details of peripheral functions refer to their respective chapters in New 8FX MB...

Page 115: ...rite RMW instruction Write PDRC 0 Pin state is L level PDRC value is 0 As output port outputs L level 1 Pin state is H level PDRC value is 1 As output port outputs H level DDRC 0 Port input enabled 1...

Page 116: ...ading the PDRC register returns the pin value However if the read modify write RMW type of instruction is used to read the PDRC register the PDRC register value is returned To use a pin shared with th...

Page 117: ...lock diagrams of port E PE0 SEG14 pin This pin has the following peripheral function LCDC SEG14 output pin SEG14 PE1 SEG15 pin This pin has the following peripheral function LCDC SEG15 output pin SEG1...

Page 118: ...rs Port E register functions Correspondence between registers and pins for port E Register abbreviation Data Read Read by read modify write RMW instruction Write PDRE 0 Pin state is L level PDRE value...

Page 119: ...bit in the LCDCE1 register to 1 Operation as a peripheral function output pin A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable...

Page 120: ...8FX MB95710M 770M Series Hardware Manual 19 10 1 Port F configuration Port F is made up of the following elements General purpose I O pins peripheral function I O pins Port F data register PDRF Port F...

Page 121: ...F778M Register abbreviation Data Read Read by read modify write RMW instruction Write PDRF 0 Pin state is L level PDRF value is 0 As output port outputs L level 1 Pin state is H level PDRF value is 1...

Page 122: ...r value is returned Operation at reset If the CPU is reset all bits in the DDRF register are initialized to 0 and port input is enabled Operation in stop mode and watch mode If the pin state setting b...

Page 123: ...Pin state is L level PDRG value is 0 As output port outputs L level 1 Pin state is H level PDRG value is 1 As output port outputs H level DDRG 0 Port input enabled 1 Port output enabled PULG 0 Pull up...

Page 124: ...ch but is not output to the pin set as an input port Reading the PDRG register returns the pin value However if the read modify write RMW type of instruction is used to read the PDRG register the PDRG...

Page 125: ...1 0 8 16 bit composite timer ch 0 upper IRQ06 0xFFEE 0xFFEF ILR1 L06 1 0 UART SIO ch 2 IRQ07 0xFFEC 0xFFED ILR1 L07 1 0 LCDC IRQ08 0xFFEA 0xFFEB ILR2 L08 1 0 8 16 bit PPG ch 1 lower IRQ09 0xFFE8 0xFFE...

Page 126: ...ut blocked 2 3 Hi Z Input blocked 2 3 Previous state kept Input blocked 2 3 Hi Z Input blocked 2 3 Hi Z Input enabled 4 However it does not function PG1 X0A Oscillation input Oscillation input Hi Z Hi...

Page 127: ...peripheral function I O Previous state kept Input blocked 3 Hi Z 7 Input blocked 3 Previous state kept Input blocked 3 Hi Z 7 Input blocked 3 Hi Z Input enabled 4 However it does not function P14 UCK...

Page 128: ...cked 3 Previous state kept Input blocked 3 Hi Z 7 Input blocked 3 Hi Z Input enabled 4 However it does not function P51 EC0 14 P52 TI0 TO00 14 P53 TO0 14 P60 SEG06 8 SEG10 8 I O port peripheral functi...

Page 129: ...PA3 COM3 PA4 COM4 PA5 COM5 PA6 COM6 PA7 COM7 PB0 SEG00 I O port peripheral function I O I O port peripheral function I O Previous state kept Input blocked 3 Hi Z Input blocked 3 Previous state kept I...

Page 130: ...figured as a reset pin 6 PG1 X0A and PG2 X1A transit to this state on a reset when configured as subclock oscillation pins 7 The pull up control setting is still effective 8 The MB95710M Series and th...

Page 131: ...the MCU in stop mode or watch mode when its MCU standby mode wakeup function is enabled For details of the MCU standby mode wakeup function refer to CHAPTER 23 I2 C BUS INTER FACE in New 8FX MB95710M...

Page 132: ...he microcontroller before applying the HV High Voltage signal Parameter Symbol Rating Unit Remarks Min Max Power supply voltage 1 VCC VSS 0 3 VSS 6 V Input voltage 1 VI VSS 0 3 VSS 6 V 2 Output voltag...

Page 133: ...ces If the HV High Voltage signal is input when the microcontroller power supply is off not fixed at 0 V since power is supplied from the pins incomplete operations may be executed If the HV High Volt...

Page 134: ...es will be under their recommended operating condition Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure No warra...

Page 135: ...C3 PC4 to PC7 2 PE0 to PE7 PF0 PF1 PG1 PG2 1 0 8 VCC VCC 0 3 V Hysteresis input VIHM PF2 0 7 VCC VCC 0 3 V Hysteresis input L level input voltage VILI P01 P04 P10 P22 P23 1 VSS 0 3 0 3 VCC V VILS P00...

Page 136: ...el output voltage VOL All output pins IOL 4 mA 4 0 4 V Input leak current Hi Z output leak current ILI All input pins 0 0 V VI VCC 5 5 A When the internal pull up resistor is disabled Internal pull up...

Page 137: ...g Flash memory programming and erasing ICCS FCH 32 MHz FMP 16 MHz Main sleep mode divided by 2 2 1 3 4 mA ICCL FCL 32 kHz FMPL 16 kHz Subclock mode divided by 2 TA 25 C 35 60 A ICCLS FCL 32 kHz FMPL 1...

Page 138: ...nsumption with the A D converter halted 0 1 1 7 A IV FCH 16 MHz Current consumption of the comparator 160 700 A IPLVD VCC Current consumption of the low voltage detection reset circuit in operation 6...

Page 139: ...voltage detection reset circuit are always in operation and current consumption therefore increases accordingly See 4 AC Characteristics Clock Timing for FCH FCL FCRH FMCRPLL and FMPLL See 4 AC Charac...

Page 140: ...is used PLL multiplication rate 3 4 4 06 MHz Operating conditions The main clock is used PLL multiplication rate 4 FCRH 3 92 4 4 08 MHz Operating conditions The main CR clock is used 0 C TA 70 C 3 8 4...

Page 141: ...ck is used Clock cycle time tHCYL X0 X1 61 5 1000 ns When the main oscillation circuit is used X0 30 8 1000 ns When an external clock is used X0 X1 250 ns When the main PLL clock is used tLCYL X0A X1A...

Page 142: ...When an external clock is used When a crystal oscillator or a ceramic oscillator is used Figure of main clock input port external connection X0A 0 8 VCC 0 2 VCC 0 2 VCC 0 8 VCC tWH2 tWL2 0 2 VCC tLCY...

Page 143: ...waveform generated when an internal clock main CR clock is used tCRLWK 1 FCRL Sub CR clock Oscillation starts Oscillation stabilizes Input waveform generated when an internal clock sub CR clock is use...

Page 144: ...the main oscillation clock is used 4 MHz When the main CR clock is used 8 16 MHz When the main PLL clock is used 8 16 MHz When the main CR PLL clock is used FSPL 16 384 kHz When the sub oscillation cl...

Page 145: ...from 2 2 5 3 and 4 Main CR clock PLL multiplication of main CR clock Select a multiplication rate from 2 2 5 3 and 4 Subclock divided by 2 Sub CR clock divided by 2 2 This is the operating clock of t...

Page 146: ...MPLL Main PLL clock SCLK Source clock MCLK Machine clock Machine clock divide ratio select bits SYCC DIV 1 0 Clock mode select bits SYCC SCS 2 0 Division circuit 1 1 4 1 8 1 16 Schematic diagram of th...

Page 147: ...el pulse width tRSTL 2 tMCLK ns Parameter Symbol Pin name Value Unit Remarks Min Typ Max Power supply rising time dV dt VCC 0 1 V ms Power supply cutoff time Toff 1 ms Reset release voltage Vdeth 1 44...

Page 148: ...rise Interrupt detection voltage 2 VIDL2 2 61 2 8 2 99 V At power supply fall Interrupt release voltage 3 VIDL3 3 06 3 3 3 54 V At power supply rise Interrupt detection voltage 3 VIDL3 2 98 3 2 3 42 V...

Page 149: ...detection voltage 1 VIDLL1 2 25 2 5 2 75 V At power supply fall Interrupt release voltage 2 VIDLL2 2 6 2 9 3 2 V At power supply rise Interrupt detection voltage 2 VIDLL2 2 52 2 8 3 08 V At power supp...

Page 150: ...ries MB95770M Series Document Number 002 09307 Rev D Page 149 of 172 tdp2 tdi2 tdiL2 tdp1 tdi1 tdiL1 tr trL tf tfL VCC Von VonL Voff VoffL VPDL VIDL VPDL VIDL Time Time Internal reset signal or interr...

Page 151: ...n of tSU DAT 250 ns is fulfilled Parameter Symbol Pin name Condition Value Unit Standard mode Fast mode Min Max Min Max SCL clock frequency fSCL SCL R 1 7 k C 50 pF 1 0 100 0 400 kHz Repeated START co...

Page 152: ...START condition setup time tSU STA SCL SDA 1 nm 2 tMCLK 20 1 nm 2 tMCLK 20 ns Master mode Busfreetime between STOP condition and START condition tBUF SCL SDA 2 nm 4 tMCLK 20 ns Data hold time tHD DAT...

Page 153: ...mode m and n can be set to values in the following range 3 3 MHz tMCLK machine clock 16 25 MHz The usable frequencies of the machine clock are determined by the settings of m and n as shown below m n...

Page 154: ...id UI UCK tIVSH UCK0 UCK1 UCK2 UI0 UI1 UI2 2 tMCLK ns UCK valid UI hold time tSHIX UCK0 UCK1 UCK2 UI0 UI1 UI2 2 tMCLK ns Serial clock H pulse width tSHSL UCK0 UCK1 UCK2 External clock operation output...

Page 155: ...20 20 mV Delay time CMP0_O 600 1200 ns Overdrive 5 mV 120 420 ns Overdrive 50 mV Power down delay CMP0_O 1200 ns Power down recovery PD 1 0 0 150 ns Power down PD 0 1 Power up stabilization time CMP0...

Page 156: ...esolution 12 bit Total error 6 6 LSB VCC 2 7 V 10 10 LSB VCC 2 7 V Linearity error 3 3 LSB VCC 2 7 V 5 5 LSB VCC 2 7 V Differential linearity error 1 9 1 9 LSB VCC 2 7 V 2 9 2 9 LSB VCC 2 7 V Zero tra...

Page 157: ...o that the sampling time is longer than the minimum value In addition if sufficient sampling time cannot be secured connect a capacitor of about 0 1 F to the analog input pin Relationship between exte...

Page 158: ...voltage required to change the output code by 1 LSB deviates from an ideal value Total error unit LSB It indicates the difference between an actual value and a theoretical value The error can be cause...

Page 159: ...ctual conversion characteristic Actual conversion characteristic VFST measurement value VSS VCC VSS VCC VSS VCC VSS VCC Analog input Digital output Analog input Ideal characteristic 1 LSB N V0T Actual...

Page 160: ...lue Unit Remarks Min Typ Max Sector erase time 2 Kbyte sector 0 3 1 1 6 2 s The time of writing 0x00 prior to erasure is excluded Sector erase time 24 Kbyte sector and 32 Kbyte sector 0 6 1 3 1 2 s Th...

Page 161: ...C mA FMP 16 MHz FMP 10 MHz FMP 8 MHz FMP 4 MHz FMP 2 MHz 50 0 50 100 150 TA C 0 1 3 2 4 1 2 3 4 5 6 7 I CCS mA VCC V FMP 16 MHz FMP 10 MHz FMP 8 MHz FMP 4 MHz FMP 2 MHz 0 1 2 4 3 I CCS mA FMP 16 MHz F...

Page 162: ...5 6 7 I CCT A VCC V 0 200 100 400 300 600 500 1 2 3 4 5 6 7 I CCTS A VCC V FMP 16 MHz FMP 10 MHz FMP 8 MHz FMP 4 MHz FMP 2 MHz 0 100 300 200 600 500 400 I CCTS A FMP 16 MHz FMP 10 MHz FMP 8 MHz FMP 4...

Page 163: ...3 I CCMCR mA 50 0 50 100 150 TA C 0 2 6 4 10 8 1 2 3 4 5 6 7 I CCMCRPLL mA VCC V 0 2 4 10 8 6 I CCMCRPLL mA 50 0 50 100 150 TA C ICCH VCC TA 25 C FMPL stop Substop mode with the external clock stoppin...

Page 164: ...0 2 6 4 10 8 1 2 3 4 5 6 7 I CCMPLL mA VCC V 0 2 4 10 8 6 I CCMPLL mA 50 0 50 100 150 TA C ICCMPLL VCC TA 25 C FMP 16 MHz PLL multiplication rate 4 Main PLL clock mode ICCMPLL TA VCC 3 3 V FMP 16 MHz...

Page 165: ...nput voltage characteristics 0 1 2 4 5 1 3 4 5 6 2 V IHI V ILI V VCC V 3 VIHI VILI VIHI VCC and VILI VCC TA 25 C 0 1 2 4 5 1 3 4 5 6 2 V IHS V ILS V VCC V 3 VIHS VILS 0 1 2 4 5 1 3 4 5 6 2 V IHM V ILM...

Page 166: ...0 11 12 13 14 15 V OL V IOL mA 0 6 VCC 2 0 V VCC 2 4 V VCC 2 7 V VCC 3 0 V VCC 3 6 V VCC 4 0 V VCC 1 8 V VCC 4 5 V VCC 5 0 V VCC 5 5 V VOL IOL TA 25 C 0 0 0 2 0 4 0 8 1 0 0 2 1 3 5 7 9 4 6 8 10 11 12...

Page 167: ...B95F718J MB95F774J MB95F776J MB95F778J MB95F714M MB95F716M MB95F718M MB95F774M MB95F776M MB95F778M Selectable Fixed Fixed 1 Low voltage detection reset With low voltage detection reset Without low vol...

Page 168: ...F716MPMC G SNE2 MB95F718JPMC G UNE2 MB95F718MPMC G SNE2 80 pin plastic LQFP LQH080 MB95F774JPMC1 G SNE2 MB95F774MPMC1 G SNE2 MB95F776JPMC1 G SNE2 MB95F776MPMC1 G SNE2 MB95F778JPMC1 G SNE2 MB95F778MPMC...

Page 169: ...09 0 20 D 14 00 BSC D1 12 00 BSC e 0 50 BSC E E1 L 0 45 0 60 0 75 L1 0 30 0 50 0 70 14 00 BSC 12 00 BSC SYMBOL BOTTOM VIEW A A1 0 25 1 80 D1 D e b D 0 20 C A B D 0 10 C A B D 0 08 C A B D E E1 4 5 7 3...

Page 170: ...9 0 20 D 12 00 BSC D1 10 00 BSC e 0 50 BSC E E1 L 0 45 0 60 0 75 L1 0 30 0 50 0 70 12 00 BSC 10 00 BSC D1 D e 1 16 64 4 5 7 E E1 4 5 7 3 6 3 0 20 C A B D b 0 10 C A B D 0 08 C A B D 8 7 5 2 A A1 0 25...

Page 171: ...0 20 D 14 00 BSC D1 12 00 BSC e 0 65 BSC E E1 L 0 45 0 60 0 75 L1 0 30 0 50 0 70 14 00 BSC 12 00 BSC 0 8 D1 D e 1 16 64 E E1 4 5 7 4 5 7 3 3 0 20 C A B D b 0 10 C A B D 0 13 C A B D 8 7 5 2 2 0 10 C...

Page 172: ...ed to Cypress template B 5633448 HTER 03 07 2017 Changed the package codes as the following from FPT 80P M37 to LQH080 from FPT 64P M38 to LQD064 from FPT 64P M39 to LQG064 in chapter 1 Product Line u...

Page 173: ...y sample design information or programming code is provided only for reference purposes It is the responsibility of the user of this document to properly design program and test the functionality and...

Page 174: ...4JPMC1 G SNE2 MB95F776MPMC1 G SNE2 MB95F778MPMC2 G SNE2 MB95F776JPMC1 G SNE2 MB95F778JPMC1 G SNE2 MB95F776MPMC2 G SNE2 MB95F716MPMC G SNE2 MB95F778MPMC1 G SNE2 MB95F714JPMC G SNE2 MB95F778JPMC2 G UNE2...

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