MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D
Page 68 of 172
18.5.4 Port 5 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR5 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR5 register to external pins.
• If data is written to the PDR5 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR5 register returns the PDR5 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR5 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR5 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR5 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR5 register, the PDR5 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR5 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can be read by the read operation on the PDR5 register. However, if the read-
modify-write (RMW) type of instruction is used to read the PDR5 register, the PDR5 register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR5 register corresponding to the input pin of a peripheral function
to “0”.
• Reading the PDR5 register returns the pin value, regardless of whether the peripheral function uses that pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR5 register, the PDR5
register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR5 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR5 reg-
ister value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL5 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL5 register.
