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MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D
Page 67 of 172
• Block diagram of P50/TO01, P51/EC0, P52/TI0/TO00 and P53/TO0
18.5.3 Port 5 registers
• Port 5 register functions
• Correspondence between registers and pins for port 5
Register
abbreviation
Data
Read
Read by read-modify-write
(RMW) instruction
Write
PDR5
0
Pin state is “L” level.
PDR5 value is “0”.
As output port, outputs “L” level.
1
Pin state is “H” level.
PDR5 value is “1”.
As output port, outputs “H” level.
DDR5
0
Port input enabled
1
Port output enabled
PUL5
0
Pull-up disabled
1
Pull-up enabled
Correspondence between related register bits and pins
Pin name
-
-
-
-
P53
P52
P51
P50
PDR5
-
-
-
-
bit3
bit2
bit1
bit0
DDR5
PUL5
PDR5
Pin
PDR5 read
PDR5 write
Executing bit manipulation instruction
DDR5 read
DDR5 write
PUL5 read
PUL5 write
DDR5
PUL5
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Pull-up
Inter
nal b
u
s