PSoC® 4000S Prototyping Kit Guide, Doc. # 002-11504 Rev. *A
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Functionality of J4 and J5 Headers (PSoC 4000S to KitProg2)
KitProg2 and target boards each contains a 1 × 5-pin header. These headers provide a physical con-
nection between the two devices. Specifically, the connection includes the SWD interface, required
to program/debug the target PSoC 4000S device/EZ-BLE PRoC Module, power, ground, and reset.
Figure A-6. J4 and J5 Headers
Table A-2. J2 Header Pin details
PSoC 4000S Prototyping board GPIO (J2)
Pin
Signal
Description
J2_01
VDDA
Power
J2_02
GND
Ground
J2_03
P0_0/SLD0
GPIO/Slider 0 Rx
J2_04
P0_1/SLD1
GPIO/Slider 1 Rx
J2_05
P0_2/SLD2
GPIO/Slider 2 Rx
J2_06
P0_3/SLD3
GPIO/Slider 3 Rx
J2_07
P0_4/UART_RX
GPIO/UART Receive
J2_08
P0_5/UART_TX
GPIO/UART Transmit
J2_09
P0_6/SLD4
GPIO/Slider 4 Rx
J2_10
P0_7/USER BUTTON
GPIO/User Button
J2_11
P2_0/LED4
GPIO/Slider 0 LED
J2_12
P2_1/LED5
GPIO/Slider 1 LED
J2_13
P2_2/LED6
GPIO/Slider 2 LED
J2_14
P2_3/LED7
GPIO/Slider 3 LED
J2_15
P2_4/LED8
GPIO/Slider 4 LED
J2_16
P2_5/LED1
GPIO/User LED
J2_17
P2_6/SLD TX
GPIO/Slider Tx
J2_18
P2_7
GPIO
J2_19
P4_0/CTANK
GPIO/CTANK
J2_20
P4_1/CMOD
GPIO/CMOD
J2_21
GND
Ground
J2_22
VDDD
Power